Multilayer ceramic electronic component

Abstract

To provide a multilayer ceramic electronic component capable of suppressing the occurrence of cracks in a laminate.SOLUTION: A multilayer ceramic electronic component 1 includes an external electrode 40, which has a main surface side base electrode layer 502 and a main surface side plating layer 602, and in a cross section along a plane parallel to the length direction and height direction, the main surface side plating layer 602 has one or more crack portions C extending into a region between the boundary line between the main surface side base electrode layer 502 and the main surface side plating layer 602 and a profile line Sp on the surface of the main surface side plating layer 602.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present invention relates to a multilayer ceramic electronic component. [Background technology]

[0002] Multilayer ceramic capacitors have been known as multilayer ceramic electronic components. Generally, a multilayer ceramic capacitor includes a laminate in which dielectric layers and internal electrode layers are alternately stacked, and external electrodes provided on both end surfaces of the laminate. For example, Patent Document 1 discloses a multilayer ceramic capacitor having the above-described structure, in which the external electrodes include base electrode layers formed by baking. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2003-243249 Summary of the Invention [Problem to be solved by the invention]

[0004] In the multilayer ceramic capacitor described in Patent Document 1, the external electrodes (external electrode layers) serve to electrically connect to the internal electrodes (internal electrode layers). However, there is a risk that cracks will occur in the laminate of the multilayer ceramic capacitor when force is applied to these external electrodes.

[0005] An object of the present invention is to provide a multilayer ceramic electronic component that can suppress the occurrence of cracks in the laminate. [Means for solving the problem]

[0006] A multilayer ceramic electronic component according to the present invention comprises a laminate including a plurality of laminated ceramic layers and a plurality of internal conductor layers, the laminate having a first main surface and a second main surface that face each other in a height direction, a first side surface and a second side surface that face each other in a width direction perpendicular to the height direction, and a first end surface and a second end surface that face each other in a length direction perpendicular to the height direction and the width direction, and a first external electrode arranged on the first end surface and a second external electrode arranged on the second end surface, wherein at least one of the first external electrode and the second external electrode has a main surface-side base electrode layer that is arranged on at least one of the first and second main surfaces, and a main surface-side plating layer formed above the main surface-side base electrode layer, and in a cross section along a plane parallel to the length direction and the height direction, the main surface-side plating layer has one or more cracks that extend into a region between a boundary line between the main surface-side base electrode layer and the main surface-side plating layer and a profile line on the surface of the main surface-side plating layer. [Effects of the Invention]

[0007] According to the present invention, it is possible to provide a multilayer ceramic electronic component that can suppress the occurrence of cracks in the laminate. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is an external perspective view of a multilayer ceramic capacitor according to an embodiment of the present invention; [Figure 2] 2 is a cross-sectional view taken along line II-II of the multilayer ceramic capacitor shown in FIG. [Figure 3] 3 is a cross-sectional view taken along line III-III of the multilayer ceramic capacitor shown in FIG. 2. [Figure 4] 4 is a cross-sectional view taken along line IV-IV of the multilayer ceramic capacitor shown in FIG. 2. [Figure 5] 3 is an enlarged view of a cross section of an external electrode at a V portion of the multilayer ceramic capacitor shown in FIG. 2. [Figure 6] 6 is a view corresponding to FIG. 5 of the multilayer ceramic capacitor according to the first modified example. FIG. [Figure 7] 6 is a view corresponding to FIG. 5 of the multilayer ceramic capacitor according to the second modified example. FIG. [Figure 8] FIG. 1 is a schematic diagram showing an example of the configuration of a double-structure multilayer ceramic capacitor. [Figure 9] FIG. 1 is a schematic diagram showing an example of the configuration of a triple-structure multilayer ceramic capacitor. [Figure 10] FIG. 1 is a schematic diagram showing an example of the configuration of a four-layer structure multilayer ceramic capacitor. DETAILED DESCRIPTION OF THE INVENTION

[0009] <Embodiment> A multilayer ceramic capacitor 1 as a multilayer ceramic electronic component according to one embodiment of the present disclosure will now be described with reference to FIGS. 1 to 4. FIG. 1 is an external perspective view of the multilayer ceramic capacitor 1 of this embodiment. FIG. 2 is a cross-sectional view taken along line II-II of the multilayer ceramic capacitor 1 of FIG. 1. FIG. 3 is a cross-sectional view taken along line III-III of the multilayer ceramic capacitor 1 of FIG. 2. FIG. 4 is a cross-sectional view taken along line IV-IV of the multilayer ceramic capacitor 1 of FIG. 2.

[0010] The drawings may be simplified and schematic for the purpose of explaining the invention, and the dimensional ratios of the depicted components or between the components may not match those described in the specification. Furthermore, components described in the specification may be omitted from the drawings, or the number of components may be omitted. For example, the number of internal electrode layers shown in Figures 2 and 3 is 10 for the sake of convenience, but this does not represent the actual number of internal electrode layers 30. Terms used in the present invention that specify shapes and geometric conditions, as well as their degrees of similarity, such as "parallel," "orthogonal," and "identical," as well as values ​​of length and angle, are not limited to their strict meanings but are interpreted to encompass a range within which similar functionality can be expected.

[0011] The multilayer ceramic capacitor 1 includes a laminate 10 and external electrodes 40.

[0012] 1 to 4 show an XYZ Cartesian coordinate system. The length direction L of the multilayer ceramic capacitor 1 and the laminate 10 corresponds to the X direction. The width direction W of the multilayer ceramic capacitor 1 and the laminate 10 corresponds to the Y direction. The stacking direction T as the height direction of the multilayer ceramic capacitor 1 and the laminate 10 corresponds to the Z direction. Here, the cross section shown in FIG. 2 is also referred to as the LT cross section. The cross section shown in FIG. 3 is also referred to as the WT cross section. The cross section shown in FIG. 4 is also referred to as the LW cross section.

[0013] As shown in Figures 1 to 4, the laminate 10 includes a first main surface TS1 and a second main surface TS2 facing in a stacking direction T, a first side surface WS1 and a second side surface WS2 facing in a width direction W perpendicular to the stacking direction T, and a first end surface LS1 and a second end surface LS2 facing in a length direction L perpendicular to the stacking direction T and the width direction W.

[0014] As shown in FIG. 1, the laminate 10 has a substantially rectangular parallelepiped shape. The dimension of the laminate 10 in the length direction L is not necessarily longer than the dimension in the width direction W. The corners and ridges of the laminate 10 are preferably rounded. A corner is a portion where three surfaces of the laminate intersect, and a ridge is a portion where two surfaces of the laminate intersect. Incidentally, some or all of the surfaces constituting the laminate 10 may be formed with irregularities.

[0015] The dimensions of the laminate 10 are not particularly limited, but if the dimension of the laminate 10 in the length direction L is defined as the L dimension, then the L dimension is preferably 0.2 mm or more and 10 mm or less. If the dimension of the laminate 10 in the stacking direction T is defined as the T dimension, then the T dimension is preferably 0.1 mm or more and 10 mm or less. If the dimension of the laminate 10 in the width direction W is defined as the W dimension, then the W dimension is preferably 0.1 mm or more and 10 mm or less.

[0016] As shown in Figures 2 and 3, the laminate 10 has an inner layer portion 11, and a first outer layer portion (first main surface side outer layer portion 12A) and a second outer layer portion (second main surface side outer layer portion 12B) arranged to sandwich the inner layer portion 11 in the stacking direction T.

[0017] The internal layer portion 11 includes a plurality of dielectric layers 20 as a plurality of ceramic layers and a plurality of internal electrode layers 30 as a plurality of internal conductor layers. The internal layer portion 11 includes the internal electrode layer 30 located closest to the first principal surface TS1 in the stacking direction T to the internal electrode layer 30 located closest to the second principal surface TS2. In the internal layer portion 11, the multiple internal electrode layers 30 are arranged opposite each other with the dielectric layer 20 interposed therebetween. The internal layer portion 11 is a portion that generates electrostatic capacitance and essentially functions as a capacitor.

[0018] The plurality of dielectric layers 20 are made of a dielectric material. The dielectric material may be, for example, a dielectric ceramic containing components such as BaTiO3, CaTiO3, SrTiO3, or CaZrO3. The dielectric material may also be one in which a secondary component such as a Mn compound, an Fe compound, a Cr compound, a Co compound, or a Ni compound is added to the above main components.

[0019] The thickness of the dielectric layer 20 is preferably 0.5 μm or more and 15 μm or less. The number of laminated dielectric layers 20 is preferably 10 or more and 700 or less. Note that this number of dielectric layers 20 is the total number of the dielectric layers in the inner layer portion 11 and the dielectric layers in the first main surface side outer layer portion 12A and the second main surface side outer layer portion 12B.

[0020] The multiple internal electrode layers 30 include first internal electrode layers 31 as multiple first internal conductor layers and second internal electrode layers 32 as multiple second internal conductor layers. The multiple first internal electrode layers 31 are arranged on the multiple dielectric layers 20. The multiple second internal electrode layers 32 are arranged on the multiple dielectric layers 20. The multiple first internal electrode layers 31 and the multiple second internal electrode layers 32 are arranged alternately in the stacking direction T of the laminate 10, with the dielectric layers 20 interposed between them. The first internal electrode layers 31 and the second internal electrode layers 32 are arranged so as to sandwich the dielectric layers 20 therebetween.

[0021] The first internal electrode layer 31 has a first opposing portion 31A opposing the second internal electrode layer 32, and a first lead portion 31B led from the first opposing portion 31A to the first end face LS1. The first lead portion 31B is exposed at the first end face LS1.

[0022] The second internal electrode layer 32 has a second opposing portion 32A opposing the first internal electrode layer 31, and a second lead portion 32B led from the second opposing portion 32A to the second end face LS2. The second lead portion 32B is exposed at the second end face LS2.

[0023] In this embodiment, the first opposing portion 31A and the second opposing portion 32A face each other via the dielectric layer 20, thereby forming capacitance and exhibiting the characteristics of a capacitor.

[0024] The shapes of the first opposing portion 31A and the second opposing portion 32A are not particularly limited, but are preferably rectangular. However, the corners of the rectangular shape may be rounded or the corners of the rectangular shape may be formed at an angle. The shapes of the first lead portion 31B and the second lead portion 32B are not particularly limited, but are preferably rectangular. However, the corners of the rectangular shape may be rounded or the corners of the rectangular shape may be formed at an angle.

[0025] The width direction W dimension of the first facing portion 31A and the width direction W dimension of the first lead portion 31B may be the same dimension, or one of the dimensions may be smaller. The width direction W dimension of the second facing portion 32A and the width direction W dimension of the second lead portion 32B may be the same dimension, or one of the dimensions may be smaller.

[0026] The first internal electrode layer 31 and the second internal electrode layer 32 are made of an appropriate conductive material, such as a metal such as Ni, Cu, Ag, Pd, or Au, or an alloy containing at least one of these metals. When an alloy is used, the first internal electrode layer 31 and the second internal electrode layer 32 may be made of, for example, an Ag-Pd alloy.

[0027] The thickness of each of the first internal electrode layers 31 and the second internal electrode layers 32 is preferably, for example, about 0.2 μm or more and 2.0 μm or less. The total number of the first internal electrode layers 31 and the second internal electrode layers 32 is preferably 10 or more and 700 or less.

[0028] The first main surface side outer layer portion 12A is located on the first main surface TS1 side of the laminate 10. The first main surface side outer layer portion 12A is an assembly of multiple dielectric layers 20 located between the first main surface TS1 and the internal electrode layer 30 closest to the first main surface TS1. The dielectric layers 20 used in the first main surface side outer layer portion 12A may be the same as the dielectric layers 20 used in the internal layer portion 11, or may be dielectric layers made of a different material.

[0029] The second main surface side outer layer portion 12B is located on the second main surface TS2 side of the laminate 10. The second main surface side outer layer portion 12B is an assembly of multiple dielectric layers 20 located between the second main surface TS2 and the internal electrode layer 30 closest to the second main surface TS2. The dielectric layers 20 used in the second main surface side outer layer portion 12B may be the same as the dielectric layers 20 used in the internal layer portion 11, or may be dielectric layers made of a different material.

[0030] The laminate 10 has a counter electrode portion 11E. The counter electrode portion 11E is a portion where the first counter portion 31A of the first internal electrode layer 31 and the second counter portion 32A of the second internal electrode layer 32 face each other. The counter electrode portion 11E is configured as a part of the inner layer portion 11. FIG. 4 shows the range of the counter electrode portion 11E in the width direction W and the length direction L. The counter electrode portion 11E is also called the effective portion of the capacitor.

[0031] The laminate 10 has side surface outer layer portions. The side surface outer layer portions include a first side surface outer layer portion WG1 and a second side surface outer layer portion WG2. The first side surface outer layer portion WG1 is a portion including the dielectric layer 20 located between the counter electrode portion 11E and the first side surface WS1. The second side surface outer layer portion WG2 is a portion including the dielectric layer 20 located between the counter electrode portion 11E and the second side surface WS2. Figures 3 and 4 show the ranges in the width direction W of the first side surface outer layer portion WG1 and the second side surface outer layer portion WG2. The side surface outer layer portions are also referred to as W gaps or side gaps.

[0032] The laminate 10 has end surface side outer layer portions. The end surface side outer layer portions include a first end surface side outer layer portion LG1 and a second end surface side outer layer portion LG2. The first end surface side outer layer portion LG1 is a portion including the dielectric layer 20 located between the counter electrode portion 11E and the first end surface LS1. The second end surface side outer layer portion LG2 is a portion including the dielectric layer 20 located between the counter electrode portion 11E and the second end surface LS2. Figures 2 and 4 show the ranges in the length direction L of the first end surface side outer layer portion LG1 and the second end surface side outer layer portion LG2. The end surface side outer layer portions are also referred to as L gaps or end gaps.

[0033] The external electrode 40 has a first external electrode 40A arranged on the first end face LS1 side and a second external electrode 40B arranged on the second end face LS2 side.

[0034] The first external electrode 40A is disposed on the first end face LS1. The first external electrode 40A is connected to the first internal electrode layer 31. The first external electrode 40A is disposed on at least a portion of either the first main surface TS1 or the second main surface TS2, among a portion of the first main surface TS1 and a portion of the second main surface TS2, and a portion of the first side surface WS1 and a portion of the second side surface WS2. In this embodiment, the first external electrode 40A includes a first end face side external electrode 40A1, a first main surface side external electrode 40A2, and a first side face side external electrode 40A3.

[0035] The first end surface side external electrode 40A1 is disposed on the first end surface LS1. The first main surface side external electrode 40A2 is connected to the first end surface side external electrode 40A1 and is disposed on parts of the first main surface TS1 and second main surface TS2 on the first end surface LS1 side. The first side surface side external electrode 40A3 is connected to the first end surface side external electrode 40A1 and is disposed on parts of the first side surface WS1 and second side surface WS2 on the first end surface LS1 side.

[0036] In this way, the first external electrode 40A is formed to extend from the first end face LS1 to a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0037] The second external electrode 40B is disposed on the second end face LS2. The second external electrode 40B is connected to the second internal electrode layer 32. The second external electrode 40B is disposed on at least a portion of either the first main surface TS1 or the second main surface TS2, among a portion of the first main surface TS1 and a portion of the second main surface TS2, and a portion of the first side surface WS1 and a portion of the second side surface WS2. In this embodiment, the second external electrode 40B has a second end face side external electrode 40B1, a second main surface side external electrode 40B2, and a second side face side external electrode 40B3.

[0038] The second end surface side external electrode 40B1 is disposed on the second end surface LS2. The second main surface side external electrode 40B2 is connected to the second end surface side external electrode 40B1 and is disposed on parts of the first main surface TS1 and the second main surface TS2 on the second end surface LS2 side. The second side surface side external electrode 40B3 is connected to the second end surface side external electrode 40B1 and is disposed on parts of the first side surface WS1 and the second side surface WS2 on the second end surface LS2 side.

[0039] In this way, the second external electrode 40B is formed to extend from the second end face LS2 to a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0040] As described above, in the laminate 10, the first opposing portion 31A of the first internal electrode layer 31 and the second opposing portion 32A of the second internal electrode layer 32 face each other via the dielectric layer 20, thereby forming a capacitance. Therefore, the characteristics of a capacitor are exhibited between the first external electrode 40A connected to the first internal electrode layer 31 and the second external electrode 40B connected to the second internal electrode layer 32.

[0041] The first external electrode 40A has a first base electrode layer 50A containing a metal component and a first plating layer 60A disposed on the first base electrode layer 50A. The first base electrode layer 50A has at least one layer selected from a baked layer, a conductive resin layer, a thin film layer, etc.

[0042] The second external electrode 40B has a second base electrode layer 50B containing a metal component and a second plating layer 60B disposed on the second base electrode layer 50B. The second base electrode layer 50B has at least one layer selected from a baked layer, a conductive resin layer, a thin film layer, etc.

[0043] The baking layer is a layer containing a metal component and either a glass component or a ceramic component, or both. The baking layer can improve adhesion between the laminate 10 and the base electrode layer 50. The metal component includes at least one selected from, for example, Cu, Ni, Ag, Pd, Ag-Pd alloy, Au, etc. The glass component includes at least one selected from, for example, B, Si, Ba, Mg, Al, Li, etc. The presence of the glass component can help sinter the metal component in the base electrode layer and promote sintering. The ceramic component may be the same type of ceramic material as that of the dielectric layer 20, or a different type of ceramic material. The ceramic component may include at least one selected from, for example, BaTiO3, CaTiO3, (Ba,Ca)TiO3, SrTiO3, CaZrO3, etc.

[0044] The baked layer is formed by, for example, applying a conductive paste containing glass and metal to the laminate and baking it. The baked layer may be formed by simultaneously firing a laminated chip having internal electrode layers and a dielectric layer with a conductive paste applied to the laminated chip, or by simultaneously firing a laminated chip having internal electrode layers and a dielectric layer to obtain a laminate and then applying a conductive paste to the laminate and baking it. When simultaneously firing a laminated chip having internal electrode layers and a dielectric layer with a conductive paste applied to the laminated chip, it is preferable to form the baked layer by adding a ceramic material instead of a glass component and baking it. In this case, it is particularly preferable to use the same type of ceramic material as the dielectric layer 20 as the added ceramic material. The baked layer may be formed in multiple layers.

[0045] The conductive resin layer is a layer having a resin portion and conductive fillers dispersed in the resin portion.

[0046] The resin portion of the conductive resin layer may contain at least one selected from various known thermosetting resins, such as epoxy resin, phenoxy resin, phenol resin, urethane resin, silicone resin, and polyimide resin. Among these, epoxy resin, which has excellent heat resistance, moisture resistance, and adhesion, is one of the most suitable resins. Furthermore, the resin portion of the conductive resin layer preferably contains a curing agent in addition to the thermosetting resin. When an epoxy resin is used as the base resin, the curing agent for the epoxy resin may be any of various known compounds, such as phenol-based, amine-based, acid anhydride-based, imidazole-based, active ester-based, and amide-imide-based compounds.

[0047] Because the conductive resin layer contains such a resin portion, it is more flexible than, for example, a plating film or a baked layer made of a baked product of a metal component and a glass component. Therefore, even if the multilayer ceramic capacitor 1 is subjected to a physical shock or a shock due to a thermal cycle, the conductive resin layer functions as a buffer layer. Therefore, the conductive resin layer suppresses the occurrence of cracks in the multilayer ceramic capacitor 1.

[0048] The conductive filler particles are dispersed in a substantially uniform distribution within the resin portion. The conductive filler particles are primarily responsible for the electrical conductivity of the conductive resin layer. Specifically, when multiple conductive filler particles come into contact with each other, a conductive path is formed within the conductive resin layer.

[0049] The metal constituting the conductive filler may be Ag alone, an alloy containing Ag, or a metal powder with Ag coated on its surface. Ag has the lowest resistivity of all metals, making it suitable as an electrode material. Furthermore, Ag is a noble metal, so it is resistant to oxidation and highly weather-resistant. Therefore, Ag metal powder is suitable as a conductive filler. Furthermore, when using a metal powder with Ag coated on its surface, it is preferable to use Cu, Ni, Sn, Bi, or an alloy powder containing any of these metals as the metal powder.

[0050] Furthermore, the conductive filler may be Cu or Ni that has been subjected to an anti-oxidation treatment. Furthermore, the conductive filler may be a metal powder whose surface is coated with Sn, Ni, or Cu. When using metal powder whose surface is coated with Sn, Ni, or Cu, the metal powder is preferably Ag, Cu, Ni, Sn, Bi, or an alloy powder thereof.

[0051] The shape of the conductive filler is not particularly limited. The conductive filler may be spherical, flat, or the like, but it is preferable to use a mixture of spherical metal powder and flat metal powder.

[0052] The conductive filler may have an average particle size of, for example, 0.3 μm or more and 10 μm or less.

[0053] The average particle size of the conductive filler contained in the conductive resin layer is measured by calculation using a laser diffraction particle size measurement method based on ISO 13320, regardless of the shape of the conductive filler.

[0054] The thin film layer is a layer of 1 μm or less in thickness on which metal particles are deposited. The thin film layer preferably contains at least one metal selected from the group consisting of Mg, Al, Ti, W, Cr, Cu, Ni, Ag, Co, Mo, and V. This can increase the adhesive strength of the external electrodes 40 to the laminate 10. The thin film layer may be a single layer or may be formed of multiple layers. For example, it may be formed of a two-layer structure consisting of a NiCr layer and a NiCu layer.

[0055] The thin film layer is formed by a thin film formation method such as sputtering or vapor deposition. When the thin film layer serving as the base electrode is formed by a sputtering electrode, the sputtered electrode is preferably formed on a portion of the first main surface TS1 and a portion of the second main surface TS2 of the laminate 10. The sputtered electrode preferably contains at least one metal selected from, for example, Ni, Cr, Cu, etc. The thickness of the sputtered electrode is preferably 50 nm or more and 400 nm or less, and more preferably 50 nm or more and 130 nm or less.

[0056] As the base electrode layer, sputtered electrodes may be formed on a portion of the first main surface TS1 and a portion of the second main surface TS2 of the laminate 10, while baked layers may be formed on the first end face LS1 and the second end face LS2. Alternatively, a plating layer (described later) may be formed directly on the laminate 10 without forming a base electrode layer on the first end face LS1 and the second end face LS2. When a baked layer is formed on the first end face LS1 and the second end face LS2, the baked layer may be disposed so as to extend not only over the first end face LS1 and the second end face LS2, but also over a portion of the first main surface TS1 and a portion of the second main surface TS2. In this case, the sputtered electrodes may be disposed so as to overlap the baked layer.

[0057] The first base electrode layer 50A according to this embodiment has a first baked layer 51A and a first conductive resin layer 52A disposed on the first baked layer 51 A. The second base electrode layer 50B according to this embodiment has a second baked layer 51B and a second conductive resin layer 52B disposed on the second baked layer 51B.

[0058] The first base electrode layer 50A includes a first end face side base electrode layer 50A1, a first main face side base electrode layer 50A2, and a first side face side base electrode layer 50A3. The first baked layer 51A includes a first end face side baked layer 51A1, a first main face side baked layer 51A2, and a first side face side baked layer 51A3. The first conductive resin layer 52A includes a first end face side conductive resin layer 52A1, a first main face side conductive resin layer 52A2, and a first side face side conductive resin layer 52A3.

[0059] The first plating layer 60A has a two-layer structure including a first lower plating layer 61A and a first upper plating layer 62A. The first plating layer 60A may have a single layer structure or a three or more layer structure.

[0060] The first plating layer 60A includes a first end surface side plating layer 60A1, a first main surface side plating layer 60A2, and a first side surface side plating layer 60A3. The first lower-layer plating layer 61A includes a first end surface side lower-layer plating layer 61A1, a first main surface side lower-layer plating layer 61A2, and a first side surface side lower-layer plating layer 61A3. The first upper-layer plating layer 62A includes a first end surface side upper-layer plating layer 62A1, a first main surface side upper-layer plating layer 62A2, and a first side surface side upper-layer plating layer 62A3.

[0061] The second base electrode layer 50B includes a second edge-side base electrode layer 50B1, a second main surface-side base electrode layer 50B2, and a second side surface-side base electrode layer 50B3. The second baked layer 51B includes a second edge-side baked layer 51B1, a second main surface-side baked layer 51B2, and a second side surface-side baked layer 51B3. The second conductive resin layer 52B includes a second edge-side conductive resin layer 52B1, a second main surface-side conductive resin layer 52B2, and a second side surface-side conductive resin layer 52B3.

[0062] The second plating layer 60B has a two-layer structure including a second lower plating layer 61 B and a second upper plating layer 62 B. The second plating layer 60B may have a single layer structure or a three or more layer structure.

[0063] The second plating layer 60B includes a second end surface side plating layer 60B1, a second main surface side plating layer 60B2, and a second side surface side plating layer 60B3. The second lower-layer plating layer 61B includes a second end surface side lower-layer plating layer 61B1, a second main surface side lower-layer plating layer 61B2, and a second side surface side lower-layer plating layer 61B3. The second upper-layer plating layer 62B includes a second end surface side upper-layer plating layer 62B1, a second main surface side upper-layer plating layer 62B2, and a second side surface side upper-layer plating layer 62B3.

[0064] Fig. 5 is an enlarged view of the cross section of the external electrodes at part V of the multilayer ceramic capacitor 1 shown in Fig. 2. In Fig. 5, the lamination direction T is oriented left-to-right on the paper, and the length direction L is oriented up-to-down on the paper.

[0065] Here, the layers constituting the first external electrode 40A and the second external electrode 40B have the same basic configuration. Furthermore, the first external electrode 40A and the second external electrode 40B are generally symmetrical with respect to the LW cross section at the center in the length direction L of the multilayer ceramic capacitor 1. Therefore, when there is no need to particularly distinguish between the first external electrode 40A and the second external electrode 40B, the first external electrode 40A and the second external electrode 40B may be collectively referred to as the external electrodes 40.

[0066] Furthermore, when there is no need to particularly distinguish between the first main surface side external electrode 40A2 and the second main surface side external electrode 40B2, the first main surface side external electrode 40A2 and the second main surface side external electrode 40B2 may be collectively referred to as the main surface side external electrode 402.

[0067] Furthermore, when there is no need to particularly distinguish between the first base electrode layer 50A and the second base electrode layer 50B, the first base electrode layer 50A and the second base electrode layer 50B may be collectively referred to as the base electrode layer 50.

[0068] Furthermore, when there is no need to particularly distinguish between the first baking layer 51A and the second baking layer 51B, the first baking layer 51A and the second baking layer 51B may be collectively referred to as the baking layer 51.

[0069] Furthermore, when there is no need to particularly distinguish between the first principal surface side base electrode layer 50A2 and the second principal surface side base electrode layer 50B2, the first principal surface side base electrode layer 50A2 and the second principal surface side base electrode layer 50B2 may be collectively referred to as the principal surface side base electrode layer 502.

[0070] Furthermore, when there is no need to particularly distinguish between the first main surface side baking layer 51A2 and the second main surface side baking layer 51B2, the first main surface side baking layer 51A2 and the second main surface side baking layer 51B2 may be collectively referred to as the main surface side baking layer 512.

[0071] Furthermore, when there is no need to particularly distinguish between the first conductive resin layer 52A and the second conductive resin layer 52B, the first conductive resin layer 52A and the second conductive resin layer 52B may be collectively referred to as the conductive resin layer 52.

[0072] Furthermore, when there is no need to particularly distinguish between the first main surface side conductive resin layer 52A2 and the second main surface side conductive resin layer 52B2, the first main surface side conductive resin layer 52A2 and the second main surface side conductive resin layer 52B2 may be collectively referred to as the main surface side conductive resin layer 522.

[0073] Furthermore, when there is no need to particularly distinguish between the first plating layer 60A and the second plating layer 60B, the first plating layer 60A and the second plating layer 60B may be collectively referred to as plating layer 60.

[0074] Furthermore, when there is no need to particularly distinguish between the first lower layer plating layer 61A and the second lower layer plating layer 61B, the first lower layer plating layer 61A and the second lower layer plating layer 61B may be collectively referred to as the lower layer plating layer 61.

[0075] Furthermore, when there is no need to particularly distinguish between the first upper plating layer 62A and the second upper plating layer 62B, the first upper plating layer 62A and the second upper plating layer 62B may be collectively referred to as the upper plating layer 62.

[0076] Furthermore, when there is no need to particularly distinguish between the first main surface side plating layer 60A2 and the second main surface side plating layer 60B2, the first main surface side plating layer 60A2 and the second main surface side plating layer 60B2 may be collectively referred to as the main surface side plating layer 602.

[0077] Furthermore, when there is no need to particularly distinguish between the first main surface side underlayer plating layer 61A2 and the second main surface side underlayer plating layer 61B2, the first main surface side underlayer plating layer 61A2 and the second main surface side underlayer plating layer 61B2 may be collectively referred to as the main surface side underlayer plating layer 612.

[0078] Furthermore, when there is no need to particularly distinguish between the first main surface side upper plating layer 62A2 and the second main surface side upper plating layer 62B2, the first main surface side upper plating layer 62A2 and the second main surface side upper plating layer 62B2 may be collectively referred to as the main surface side upper plating layer 622.

[0079] Furthermore, when there is no need to particularly distinguish between the first main surface TS1 and the second main surface TS2 of the laminate 10, the first main surface TS1 and the second main surface TS2 may be collectively referred to as the main surface TS.

[0080] Next, a description will be given of the baking layer 51. The baking layer 51 has a first baking layer 51A and a second baking layer 51B.

[0081] The first baked layer 51A is disposed on the first end face LS1. The first baked layer 51A is connected to the first internal electrode layer 31. The first baked layer 51A is also disposed on at least a portion of either the first main surface TS1 or the second main surface TS2, or a portion of the first side surface WS1 or the second side surface WS2. In this embodiment, the first baked layer 51A is formed to extend from the first end face LS1 to a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0082] More specifically, the first baking layer 51A is arranged such that the above-mentioned first end face side baking layer 51A1 is arranged on the first end face LS1, the above-mentioned first main face side baking layer 51A2 is arranged so as to extend from above the first end face LS1 to a portion of the first main face TS1 and a portion of the second main face TS2, and the above-mentioned first side face side baking layer 51A3 is arranged so as to extend from above the first end face LS1 to a portion of the first side face WS1 and a portion of the second side face WS2.

[0083] The second baked layer 51B is disposed on the second end face LS2. The second baked layer 51B is connected to the second internal electrode layer 32. The second baked layer 51B is also disposed on at least a portion of either the first main surface TS1 or the second main surface TS2, among a portion of the first main surface TS1 and a portion of the second main surface TS2, or a portion of the first side surface WS1 and a portion of the second side surface WS2. In this embodiment, the second baked layer 51B is formed to extend from the second end face LS2 to a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0084] More specifically, the second baking layer 51B is arranged such that the above-mentioned second end face side baking layer 51B1 is arranged on the second end face LS2, the above-mentioned second main face side baking layer 51B2 is arranged so as to extend from the second end face LS2 to a portion of the first main face TS1 and a portion of the second main face TS2, and the above-mentioned second side face side baking layer 51B3 is arranged so as to extend from the second end face LS2 to a portion of the first side face WS1 and a portion of the second side face WS2.

[0085] The thickness in the longitudinal direction L of the first end face side baking layer 51A1 located on the first end face LS1 is preferably, for example, approximately 2 μm or more and 220 μm or less at the center of the first end face side baking layer 51A1 in the stacking direction T and width direction W.

[0086] The thickness in the longitudinal direction L of the second end face side baking layer 51B1 located on the second end face LS2 is preferably, for example, approximately 2 μm or more and 220 μm or less at the center of the second end face side baking layer 51B1 in the stacking direction T and width direction W.

[0087] The thickness in the stacking direction T of the first main surface side baking layer 51A2 provided on at least one of the first main surface TS1 or the second main surface TS2 is preferably, for example, approximately 4 μm or more and 40 μm or less at the center of the length direction L and width direction W of the first main surface side baking layer 51A2 provided in this portion.

[0088] When the first baking layer 51A is provided on a portion of at least one of the first side surface WS1 or the second side surface WS2, it is preferable that the thickness in the width direction W of the first side surface baking layer 51A3 provided in this portion is, for example, approximately 4 μm or more and 40 μm or less at the center in the length direction L and stacking direction T of the first side surface baking layer 51A3 provided in this portion.

[0089] The thickness in the stacking direction T of the second main surface side baking layer 51B2 provided on at least one of the first main surface TS1 or the second main surface TS2 is preferably, for example, approximately 4 μm or more and 40 μm or less at the center of the length direction L and width direction W of the second main surface side baking layer 51B2 provided in this portion.

[0090] When the second baking layer 51B is provided on a portion of at least one of the first side surface WS1 or the second side surface WS2, it is preferable that the thickness in the width direction W of the second side surface baking layer 51B3 provided in this portion is, for example, approximately 4 μm or more and 40 μm or less at the center in the length direction L and stacking direction T of the second side surface baking layer 51B3 provided in this portion.

[0091] The external electrode 40 has a base electrode layer 50. The base electrode layer 50 has a baked layer 51 and a conductive resin layer 52 containing a resin component and a metal component that is disposed on the baked layer 51. The conductive resin layer 52 has a first conductive resin layer 52A and a second conductive resin layer 52B.

[0092] The first conductive resin layer 52A is disposed so as to cover the first baked layer 51A. Preferably, an end of the first conductive resin layer 52A is in contact with the laminate 10. The end of the first conductive resin layer 52A refers to a portion of the first conductive resin layer 52A that is closer to the second end face LS2 than the first baked layer 51A in the longitudinal direction L.

[0093] In this embodiment, the first conductive resin layer 52A is arranged such that the above-mentioned first end face side conductive resin layer 52A1 is arranged on the first end face LS1, the above-mentioned first main face side conductive resin layer 52A2 is arranged so as to extend from on the first end face LS1 to a portion of the first main face TS1 and a portion of the second main face TS2, and the above-mentioned first side face side conductive resin layer 52A3 is arranged so as to extend from on the first end face LS1 to a portion of the first side face WS1 and a portion of the second side face WS2.

[0094] The second conductive resin layer 52B is disposed so as to cover the second baked layer 51B. Preferably, an end of the second conductive resin layer 52B is in contact with the laminate 10. The end of the second conductive resin layer 52B refers to a portion of the second conductive resin layer 52B that is closer to the first end face LS1 than the second baked layer 51B in the longitudinal direction L.

[0095] In this embodiment, the second conductive resin layer 52B is arranged such that the above-mentioned second end face side conductive resin layer 52B1 is arranged on the second end face LS2, the above-mentioned second main face side conductive resin layer 52B2 is arranged so as to extend from the second end face LS2 to a portion of the first main face TS1 and a portion of the second main face TS2, and the above-mentioned second side face side conductive resin layer 52B3 is arranged so as to extend from the second end face LS2 to a portion of the first side face WS1 and a portion of the second side face WS2.

[0096] The thickness in the longitudinal direction L of the first end face side conductive resin layer 52A1 located on the first end face LS1 side is preferably, for example, approximately 10 μm or more and 200 μm or less at the center of the first end face side conductive resin layer 52A1 in the stacking direction T and width direction W.

[0097] The thickness in the longitudinal direction L of the second end face side conductive resin layer 52B1 located on the second end face LS2 side is preferably, for example, approximately 10 μm or more and 200 μm or less at the center of the second end face side conductive resin layer 52B1 in the stacking direction T and width direction W.

[0098] The thickness in the stacking direction T of the first principal surface side conductive resin layer 52A2 provided on at least one part of the first principal surface TS1 side and the second principal surface TS2 side is preferably, for example, approximately 10 μm or more and 200 μm or less at the center part in the length direction L and width direction W of the first principal surface side conductive resin layer 52A2 provided in this part.

[0099] When the first side surface side conductive resin layer 52A3 is provided on a portion of the first side surface WS1 side and a portion of the second side surface WS2 side, the thickness in the width direction W of the first side surface side conductive resin layer 52A3 provided on this portion is preferably, for example, approximately 10 μm or more and 200 μm or less at the center in the length direction L and stacking direction T of the first side surface side conductive resin layer 52A3 provided on this portion.

[0100] The thickness in the stacking direction T of the second principal surface side conductive resin layer 52B2 provided on at least a portion of the first principal surface TS1 side or the second principal surface TS2 side is preferably, for example, approximately 10 μm or more and 200 μm or less at the center in the length direction L and width direction W of the second principal surface side conductive resin layer 52B2 provided in this portion.

[0101] When the second side surface side conductive resin layer 52B3 is provided on a portion of the first side surface WS1 side and a portion of the second side surface WS2 side, the thickness in the width direction W of the second side surface side conductive resin layer 52B3 provided on this portion is preferably, for example, approximately 10 μm or more and 200 μm or less at the center in the length direction L and stacking direction T of the second side surface side conductive resin layer 52B3 provided on this portion.

[0102] The conductive resin layer 52 is disposed on the baked layer 51. Then, the plating layer 60 is disposed so as to cover the conductive resin layer 52. The plating layer 60 has a lower plating layer 61 and an upper plating layer 62.

[0103] The plating layer 60 includes a first plating layer 60A and a second plating layer 60B.

[0104] The first plating layer 60A is disposed so as to cover the first conductive resin layer 52A. In this embodiment, the first plating layer 60A is disposed so as to extend from the first end face LS1 to a portion of the first main surface TS1 and a portion of the second main surface TS2, and a portion of the first side surface WS1 and a portion of the second side surface WS2. More specifically, the first plating layer 60A is disposed such that the first end face-side plating layer 60A1 described above is disposed on the first end face LS1, the first main face-side plating layer 60A2 described above is disposed so as to extend from the first end face LS1 to a portion of the first main surface TS1 and a portion of the second main surface TS2, and the first side face-side plating layer 60A3 described above is disposed so as to extend from the first end face LS1 to a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0105] The second plating layer 60B is disposed so as to cover the second conductive resin layer 52B. In this embodiment, the second plating layer 60B is disposed so as to extend from the first end face LS1 to a portion of the first main surface TS1 and a portion of the second main surface TS2, and a portion of the first side surface WS1 and a portion of the second side surface WS2. More specifically, the second plating layer 60B is disposed such that the second end face-side plating layer 60B1 described above is disposed on the second end face LS2, the second main face-side plating layer 60B2 described above is disposed so as to extend from the second end face LS2 to a portion of the first main surface TS1 and a portion of the second main surface TS2, and the second side face-side plating layer 60B3 described above is disposed so as to extend from the second end face LS2 to a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0106] The plating layer 60 preferably has a two-layer structure consisting of a lower plating layer 61 and an upper plating layer 62. The lower plating layer 61 is a Ni plating layer, and the upper plating layer 62 is a Sn plating layer. Therefore, the main surface-side lower plating layer 612 is a Ni plating layer, and the main surface-side upper plating layer 622 is a Sn plating layer.

[0107] Specifically, the first lower plating layer 61A is a Ni plating layer, and the first upper plating layer 62A is a Sn plating layer.

[0108] The second lower plating layer 61B is a Ni plating layer, and the second upper plating layer 62B is a Sn plating layer.

[0109] The first end surface side lower layer plating layer 61A1, the first main surface side lower layer plating layer 61A2, and the first side surface side lower layer plating layer 61A3 are Ni plating layers, and the first end surface side upper layer plating layer 62A1, the first main surface side upper layer plating layer 62A2, and the first side surface side upper layer plating layer 62A3 are Sn plating layers.

[0110] The second end surface side lower layer plating layer 61B1, the second main surface side lower layer plating layer 61B2, and the second side surface side lower layer plating layer 61B3 are Ni plating layers, and the second end surface side upper layer plating layer 62B1, the second main surface side upper layer plating layer 62B2, and the second side surface side upper layer plating layer 62B3 are Sn plating layers.

[0111] The Ni plating layer prevents the baked layer 51 and the conductive resin layer 52 of the base electrode layer 50 from being eroded by solder when mounting the multilayer ceramic capacitor 1. The Sn plating layer improves the wettability of the solder when mounting the multilayer ceramic capacitor 1, thereby facilitating the mounting of the multilayer ceramic capacitor 1.

[0112] Therefore, it is preferable that a first upper plating layer 62A is disposed on the first lower plating layer 61A, and it is preferable that a second upper plating layer 62B is disposed on the second lower plating layer 61B.

[0113] In this embodiment, the first end face side lower layer plating layer 61A1 and the first end face side upper layer plating layer 62A1 are arranged on the first end face LS1, the above-mentioned first main surface side lower layer plating layer 61A2 and first main surface side upper layer plating layer 62A2 are arranged so as to extend from the first end face LS1 to a portion of the first main surface TS1 and a portion of the second main surface TS2, and the above-mentioned first side face side lower layer plating layer 61A3 and first side face side upper layer plating layer 62A3 are arranged so as to extend from the first end face LS1 to a portion of the first side face WS1 and a portion of the second side face WS2.

[0114] Similarly, the second end face side lower layer plating layer 61B1 and the second end face side upper layer plating layer 62B1 are arranged on the second end face LS2, the above-mentioned second main surface side lower layer plating layer 61B2 and second main surface side upper layer plating layer 62B2 are arranged so as to extend from above the second end face LS2 to a portion of the first main surface TS1 and a portion of the second main surface TS2, and the above-mentioned second side face side lower layer plating layer 61B3 and second side face side upper layer plating layer 62B3 are arranged so as to extend from above the second end face LS2 to a portion of the first side face WS1 and a portion of the second side face WS2.

[0115] The thickness of each of the first lower plating layer 61A and the first upper plating layer 62A is preferably 1 μm or more and 15 μm or less.

[0116] The thickness of each of the second lower plating layer 61B and the second upper plating layer 62B is preferably 1 μm or more and 15 μm or less.

[0117] FIG. 5 is an enlarged view of the external electrode cross section at portion V of the multilayer ceramic capacitor 1 shown in FIG. 2. As described above, the layers constituting the first external electrode 40A and the second external electrode 40B have the same basic configuration, and therefore, in the description using FIG. 5, the layers constituting the first external electrode 40A and the second external electrode 40B will be collectively referred to. For example, the first main surface-side lower-layer plating layer 61A2 and the second main surface-side lower-layer plating layer 61B2 have the same basic configuration, and therefore, in the description using FIG. 5, they will be collectively referred to as main surface-side lower-layer plating layer 612. The first main surface-side upper-layer plating layer 62A2 and the second main surface-side upper-layer plating layer 62B2 have the same basic configuration, and therefore, in the description using FIG. 5, they will be collectively referred to as main surface-side upper-layer plating layer 622. For example, the main surface-side lower-layer plating layer 612 is a Ni plating layer, and the main surface-side upper-layer plating layer 622 is a Sn plating layer.

[0118] 5, the external electrode 40 has a main surface-side base electrode layer 502 disposed on the main surface TS, and a main surface-side plating layer 602 disposed on the main surface-side base electrode layer 502. A profile line Sp of the surface of the main surface-side plating layer 602 is shown in FIG.

[0119] The main surface-side base electrode layer 502 has a main surface-side baked layer 512 disposed on the main surface TS, and a main surface-side conductive resin layer 522 disposed on the main surface-side baked layer 512.

[0120] The main surface-side plating layer 602 has a main surface-side lower plating layer 612 disposed on the main surface-side conductive resin layer 522, and a main surface-side upper plating layer 622 disposed on the main surface-side lower plating layer 612. The main surface-side upper plating layer 622 is located as the uppermost layer in the main surface-side plating layer 602. Therefore, it can be said that the profile line on the surface of the main surface-side upper plating layer 622 is the profile line Sp on the surface of the main surface-side plating layer 602.

[0121] 5 , the main surface-side plating layer 602 has one or more cracks C extending into a region between a first boundary line B1, which serves as the boundary line between the main surface-side base electrode layer 502 and the main surface-side plating layer 602, and a profile line Sp on the surface of the main surface-side plating layer 602. Note that the first boundary line B1 can also be said to be a surface profile line of the main surface-side conductive resin layer 522 that constitutes the main surface-side base electrode layer 502.

[0122] More specifically, in the LT cross section, the crack C extends within a region between a first boundary line B1, which is the boundary line between the main surface-side base electrode layer 502 and the main surface-side plating layer 602, and a second boundary line B2, which is the boundary line between the plating layers, between the main surface-side lower plating layer 612 and the main surface-side upper plating layer 622. The second boundary line B2 can also be said to be a surface profile line of the main surface-side lower plating layer 612.

[0123] In this embodiment, the main surface side lower plating layer 612 is a Ni plating layer, and the main surface side upper plating layer 622 is a Sn plating layer. The crack C extends within the Ni plating layer.

[0124] At least one of the one or more cracks C extends in a shape that follows the second boundary line B2, which is the boundary line between the plating layers. The crack C extends along the second boundary line B2 in a curved line parallel to the second boundary line B2. In this specification, "extending in a parallel curved line" means that two or more curves extend while maintaining a substantially constant distance from each other.

[0125] The crack portion C has a shape that is linked to the second boundary line B2. The crack portion C has a shape that is linked to the first boundary line B1. The crack portion C may be located closer to the second boundary line B2 than to the first boundary line B1. The shape linkage between the crack portion C and the second boundary line B2 may be higher than the shape linkage between the crack portion C and the first boundary line B1. The crack portion C has an uneven shape that follows the uneven shape of the second boundary line B2. The crack portion C may have an uneven shape that follows the uneven shape of the first boundary line B1.

[0126] The length of the crack C is preferably 10 μm or more and 200 μm or less. This allows the stress on the laminate to be more effectively alleviated even when force is applied to the external electrode while maintaining the basic strength of the external electrode. If the length is less than 10 μm, the effects of the present disclosure may be limited. If the length exceeds 200 μm, the strength of the external electrode may be slightly reduced. The length of the crack C may be 30 μm or more and 100 μm or less. The length of the crack C may be equal to or greater than the thickness of the main surface-side plating layer 602.

[0127] The maximum width perpendicular to the extension direction of the crack portion C, i.e., the maximum gap created by the crack portion C, is preferably 0.05 μm or more and 5 μm or less, and more preferably 0.05 μm or more and 1 μm or less. This allows the stress on the laminate to be more effectively alleviated even when force is applied to the external electrode while maintaining the basic strength of the external electrode. If it is less than 0.05 μm, the effects of the present disclosure may be limited. If it exceeds 1 μm, the strength of the external electrode may be slightly reduced, and if it exceeds 5 μm, the strength of the external electrode may be reduced. The maximum width perpendicular to the extension direction of the crack portion C may be 0.1 μm or more and 0.5 μm or less.

[0128] The second boundary line B2 has a rising portion B2s that rises and extends from the main surface TS of the laminate 10, an extending portion B2e that extends along the main surface TS of the laminate 10, and a rounded portion B2r that connects the rising portion B2s and the extending portion B2e.

[0129] Preferably, the crack C has at least a rising portion Cs rising from and extending from the main surface TS of the laminate 10, and a rounded portion Cr bending in a direction along the main surface TS of the laminate 10. In this embodiment, the rounded portion Cr corresponds to a curved portion. This allows for more effective relaxation of stress on the laminate even when force is applied to the external electrode. More preferably, the crack C further has an extending portion Ce extending along the main surface TS of the laminate 10, as shown in FIG. 5. That is, the crack C preferably has a rising portion Cs rising from and extending from the main surface TS of the laminate 10, an extending portion Ce extending along the main surface TS of the laminate 10, and a rounded portion Cr connecting the rising portion Cs and the extending portion Ce. The extending portion Ce may be longer than the rising portion Cs. The rising portion Cs, the extending portion Ce, and the rounded portion Cr of the crack portion C are disposed at positions corresponding to the rising portion B2s, the extending portion B2e, and the rounded portion B2r of the second boundary line B2.

[0130] The radius of curvature of the rounded portion Cr of the crack portion C is smaller than the radius of curvature of the rounded portion Br of the second boundary line B2. The radius of curvature of the rounded portion Cr of the crack portion C may be smaller than the minimum radius of curvature of the curve near the end of the first boundary line B1.

[0131] As shown in this embodiment, for example, when the plating layer 60 has a Ni plating layer as the main surface-side lower plating layer 612 and a Sn plating layer as the main surface-side upper plating layer 622, it is preferable that the crack portion C be provided in the Ni plating layer, which is made of a metal that is less likely to melt during soldering, rather than in the Sn plating layer, which is made of a metal that is more likely to melt during soldering. This makes it possible to leave the plating layer having the crack portion C even after soldering, and more effectively suppress the occurrence of cracks in the laminate 10 in an assembled state. Note that the main surface-side lower plating layer 612 is not limited to a Ni plating layer and may be, for example, a Cu plating layer. Even in this case, it is preferable that the crack portion C be provided in the main surface-side lower plating layer 612 (e.g., a Cu plating layer) made of a metal that is less likely to melt during soldering than the main surface-side upper plating layer 622. However, this is not limited to this. For example, the plating layer 60 may be a single layer, and within the single layer plating layer 60, one or more crack portions C may be arranged extending into the region between a first boundary line B1 as the boundary line between the main surface side base electrode layer 502 and the main surface side plating layer 602, and a profile line Sp on the surface of the main surface side plating layer 602.

[0132] The plating layer in which the crack C is located may be thicker than the other plating layers. For example, the main surface-side lower plating layer 612 in which the crack C is located may be thicker than the main surface-side upper plating layer 622. This makes it easier to locate the crack C within the plating layer. However, this is not limited to this.

[0133] <First Modification> In the above-described embodiment, the external electrode 40 of the multilayer ceramic capacitor 1 having the plating layer 60 with a two-layer structure has been described, but this is not limiting. For example, the plating layer 60 of the multilayer ceramic capacitor 1 may be a single layer, or may be three or more layers. Below, a multilayer ceramic capacitor 1 according to a first modified example having the plating layer 60 with a three-layer structure will be described. FIG. 6 is a view corresponding to FIG. 5 of the multilayer ceramic capacitor 1 of the first modified example. Components similar to those of the multilayer ceramic capacitor 1 according to the above-described embodiment will be assigned the same reference numerals, and descriptions thereof may be omitted.

[0134] The main surface-side plating layer 602 of this modification has a main surface-side lower-layer plating layer 612 arranged on the main surface-side base electrode layer 502, a main surface-side upper-layer plating layer 622 located in the uppermost layer of the main surface-side plating layer 602, and a main surface-side intermediate plating layer 632 arranged between the main surface-side lower-layer plating layer 612 and the main surface-side upper-layer plating layer 622. In this modification, the inter-plating layer boundary line has a first inter-plating layer boundary line B3 which is the boundary line between the main surface-side lower-layer plating layer 612 and the main surface-side intermediate plating layer 632, and a second inter-plating layer boundary line B4 which is the boundary line between the main surface-side intermediate plating layer 632 and the main surface-side upper plating layer 622.

[0135] In the LT cross section shown in Figure 6, the main surface side plating layer 602 has one or more cracks C extending into the region between a first boundary line B1, which is the boundary line between the main surface side base electrode layer 502 and the main surface side plating layer 602, and a profile line Sp on the surface of the main surface side plating layer 602.

[0136] The crack C may extend within the main surface-side lower plating layer 612 or within the main surface-side intermediate plating layer 632. The crack C may extend within either one of the plating layers. Alternatively, one or more cracks C may extend within each of both plating layers. It is preferable that each crack C extends within a single plating layer without reaching the boundaries between multiple plating layers. This allows the basic strength of the external electrode to be maintained, and stress on the laminate to be more effectively alleviated even when force is applied to the external electrode. However, this is not limited to this.

[0137] In the modification shown in FIG. 6, the crack portion C has, as the plurality of crack portions C, a first crack portion C10 and a second crack portion C20.

[0138] In the LT cross section, the first crack portion C10 extends within the region between a first boundary line B1, which is the boundary line between the main surface-side base electrode layer 502 and the main surface-side plating layer 602, and a first inter-plating layer boundary line B3, which is the boundary line between the main surface-side lower-layer plating layer 612 and the main surface-side intermediate plating layer 632. In other words, the main surface-side lower-layer plating layer 612 has a first crack portion C10 that extends within the region between the first boundary line B1 and the first inter-plating layer boundary line B3.

[0139] In the LT cross section, the second crack portion C20 extends within the region between a first inter-plating layer boundary line B3, which is the boundary line between the main surface-side lower plating layer 612 and the main surface-side intermediate plating layer 632, and a second inter-plating layer boundary line B4, which is the boundary line between the main surface-side intermediate plating layer 632 and the main surface-side upper plating layer 622. In other words, the main surface-side intermediate plating layer 632 has a second crack portion C20 that extends within the region between the first inter-plating layer boundary line B3 and the second inter-plating layer boundary line B4.

[0140] The plating layer 60 in this modification has a three-layer structure of, for example, a Cu plating layer, a Ni plating layer, and a Sn plating layer. Therefore, the main surface-side lower plating layer 612 is a Cu plating layer, the main surface-side intermediate plating layer 632 is a Ni plating layer, and the main surface-side upper plating layer is a Sn plating layer. The first crack C10 extends within the Cu plating layer. The second crack C20 extends within the Ni plating layer.

[0141] In addition, the first boundary line B1 is also the surface profile line of the main surface side base electrode layer 502, the first inter-plating layer boundary line B3 is also the surface profile line of the main surface side lower plating layer 612, and the second inter-plating layer boundary line B4 is also the surface profile line of the main surface side intermediate plating layer 632.

[0142] At least one of the one or more crack portions C extends in a shape along the first inter-plating layer boundary line B3 or the second inter-plating layer boundary line B4 as the inter-plating layer boundary line. The crack portion C extends along the first inter-plating layer boundary line B3 or the second inter-plating layer boundary line B4 in a curved shape parallel to the first inter-plating layer boundary line B3 or the second inter-plating layer boundary line B4.

[0143] The crack portion C has a shape that is linked to the first inter-plating layer boundary line B3 or the second inter-plating layer boundary line B4 as the plating layer boundary line. The crack portion C may have a shape that is linked to the first boundary line B1. The crack portion C has an uneven shape that follows the uneven shape of the first inter-plating layer boundary line B3 or the second inter-plating layer boundary line B4 as the plating layer boundary line. The crack portion C may have an uneven shape that follows the uneven shape of the first boundary line B1.

[0144] The first crack portion C10 extends along the first inter-plating layer boundary line B3 in a curved shape parallel to the first inter-plating layer boundary line B3. The first crack portion C10 may also extend along the second inter-plating layer boundary line B4 in a curved shape parallel to the second inter-plating layer boundary line B4.

[0145] The first crack portion C10 has an uneven shape that follows the uneven shape of the boundary line B3 between the first plating layers. The first crack portion C10 may have an uneven shape that follows the uneven shape of the first boundary line B1 or the boundary line B4 between the second plating layers. The shape interlocking between the first crack portion C10 and the boundary line B3 between the first plating layers may be higher than the shape interlocking between the first crack portion C10 and the first boundary line B1.

[0146] The second crack portion C20 extends along the first inter-plating layer boundary line B3 in a curved line parallel to the first inter-plating layer boundary line B3. The second crack portion C20 also extends along the second inter-plating layer boundary line B4 in a curved line parallel to the second inter-plating layer boundary line B4.

[0147] The second crack portion C20 has an uneven shape that follows the uneven shape of the boundary line B3 between the first plating layers. The second crack portion C20 has an uneven shape that follows the uneven shape of the boundary line B4 between the second plating layers. The second crack portion C20 may have an uneven shape that follows the uneven shape of the first boundary line B1.

[0148] The multiple crack portions C may extend in parallel curved lines. For example, the second crack portion C20 may extend along the first crack portion C10 in a parallel curved line to the first crack portion C10. The second crack portion C20 may have an uneven shape that follows the uneven shape of the first crack portion C10. The uneven shape of the first crack portion C10 and the uneven shape of the second crack portion C20 may have a shape interlocking relationship.

[0149] The length of the crack C is preferably 10 μm or more and 200 μm or less. This allows the stress on the laminate to be more effectively alleviated even when force is applied to the external electrode while maintaining the basic strength of the external electrode. If the length is less than 10 μm, the effects of the present disclosure may be limited. If the length exceeds 200 μm, the strength of the external electrode may be slightly reduced. The length of the crack C may be 30 μm or more and 100 μm or less. In the example of FIG. 6, the first crack C10 is longer than the second crack C20. However, this is not limited to this. The length of the crack C may be equal to or greater than the thickness of the main surface-side plating layer 602.

[0150] The maximum width perpendicular to the extension direction of the crack portion C, i.e., the maximum gap created by the crack portion C, is preferably 0.05 μm or more and 5 μm or less, and more preferably 0.05 μm or more and 1 μm or less. This allows the stress on the laminate to be more effectively alleviated even when force is applied to the external electrode while maintaining the basic strength of the external electrode. If it is less than 0.05 μm, the effects of the present disclosure may be limited. If it exceeds 1 μm, the strength of the external electrode may be slightly reduced, and if it exceeds 5 μm, the strength of the external electrode may be reduced. The maximum width perpendicular to the extension direction of the crack portion C may be 0.1 μm or more and 0.5 μm or less.

[0151] The first inter-plated layer boundary line B3 has a rising portion B3s that extends upward from the main surface TS of the laminate 10, an extending portion B3e that extends along the main surface TS of the laminate 10, and a rounded portion B3r that connects the rising portion B3s and the extending portion B3e.

[0152] The boundary line B4 between the second plating layers has a rising portion B4s that rises and extends from the main surface TS of the laminate 10, an extending portion B4e that extends along the main surface TS of the laminate 10, and a rounded portion B4r that connects the rising portion B4s and the extending portion B4e.

[0153] The first crack portion C10 preferably has at least a rising portion C10s rising from and extending from the main surface TS of the laminate 10, and a rounded portion C10r bending in a direction along the main surface TS of the laminate 10. The rounded portion C10r in this modification corresponds to a curved portion. This allows for more effective relaxation of stress on the laminate even when force is applied to the external electrode. More preferably, the first crack portion C10 further has an extending portion C10e extending along the main surface TS of the laminate 10, as shown in FIG. 6. That is, the first crack portion C10 preferably has a rising portion C10s rising from and extending from the main surface TS of the laminate 10, an extending portion C10e extending along the main surface TS of the laminate 10, and a rounded portion C10r connecting the rising portion C10s and the extending portion C10e. The rising portion C10s, the extending portion C10e, and the rounded portion C10r of the first crack portion C10 are disposed at positions corresponding to the rising portion B3s, the extending portion B3e, and the rounded portion B3r of the first inter-plating layer boundary line B3.

[0154] The second crack portion C20 preferably has at least a rising portion C20s rising from and extending from the main surface TS of the laminate 10, and a rounded portion C20r bending in a direction along the main surface TS of the laminate 10. The rounded portion C20r in this modification corresponds to a curved portion. This allows for more effective relaxation of stress on the laminate even when force is applied to the external electrode. More preferably, the second crack portion C20 further has an extending portion C20e extending along the main surface TS of the laminate 10, as shown in FIG. 6. That is, the second crack portion C20 preferably has a rising portion C20s rising from and extending from the main surface TS of the laminate 10, an extending portion C20e extending along the main surface TS of the laminate 10, and a rounded portion C20r connecting the rising portion C20s and the extending portion C20e. The rising portion C20s, extending portion C20e, and rounded portion C20r of the second crack portion C20 are arranged at positions corresponding to the rising portion B3s, extending portion B3e, and rounded portion B3r of the first inter-plating layer boundary line B3. The rising portion C20s, extending portion C20e, and rounded portion C20r of the second crack portion C20 are arranged at positions corresponding to the rising portion B3s, extending portion B3e, and rounded portion B3r of the second inter-plating layer boundary line B4.

[0155] The radius of curvature of the rounded portion C10r of the first crack portion C10 may be smaller than the radius of curvature of the rounded portion B3r of the first inter-plating layer boundary line B3.

[0156] The radius of curvature of the rounded portion C20r of the second crack portion C20 may be smaller than the radius of curvature of the rounded portion B4r of the second inter-plating layer boundary line B4, and may be larger than the radius of curvature of the rounded portion C10r of the first crack portion C10.

[0157] As shown in this modified example, for example, when the plating layer 60 has a three-layer structure of a Cu plating layer, a Ni plating layer, and a Sn plating layer, it is preferable that the crack portion C be provided in the Ni plating layer or the Cu plating layer, which is made of a metal that does not melt easily when soldering, rather than in the Sn plating layer, which is made of a metal that melts easily when soldering.

[0158] <Second Modification> Although the multilayer ceramic capacitor 1 according to the above-described embodiment has one crack portion C in the main-surface-side external electrode 402, this is not limiting. For example, the multilayer ceramic capacitor 1 may have multiple crack portions C. For example, multiple crack portions C may be present in a single plating layer. Below, a multilayer ceramic capacitor 1 according to a second modified example having multiple crack portions C in a single plating layer will be described with reference to FIG. 7. FIG. 7 is a view of the multilayer ceramic capacitor 1 according to the second modified example, corresponding to FIG. 5. Configurations similar to those of the multilayer ceramic capacitor 1 according to the above-described embodiment will be assigned the same reference numerals, and descriptions thereof may be omitted.

[0159] 7, multiple cracks C extend within a region between a first boundary line B1, which serves as the boundary line between the main surface-side base electrode layer 502 and the main surface-side plating layer 602, and a second boundary line B2, which serves as the boundary line between the plating layers, the main surface-side lower plating layer 612 and the main surface-side upper plating layer 622. In other words, the main surface-side lower plating layer 612 has multiple cracks C that extend within a region between the first boundary line B1 and the second boundary line B2.

[0160] In the modified example shown in Figure 7, the crack portion C has multiple crack portions C, including a first crack portion C11 on the second boundary line B2 side and a second crack portion C12 on the first boundary line B1 side of the first crack portion C11.

[0161] The first crack portion C11 and the second crack portion C12 extend within the Ni plating layer. The first crack portion C11 and the second crack portion C12 extend in parallel curved lines. For example, the second crack portion C12 may extend along the first crack portion C11 in a parallel curved line to the first crack portion C11. The second crack portion C12 may have an uneven shape that follows the uneven shape of the first crack portion C11. The uneven shape of the first crack portion C11 and the uneven shape of the second crack portion C12 may have a shape interlocking relationship. This allows the external electrode to maintain its basic strength while more effectively mitigating stress on the laminate even when force is applied to the external electrode.

[0162] The first crack portion C11 extends along the second boundary line B2 in a curved line parallel to the second boundary line B2. The second crack portion C12 extends along the second boundary line B2 in a curved line parallel to the second boundary line B2.

[0163] The first crack portion C11 may be located closer to the second boundary line B2 than to the first boundary line B1. The second crack portion C12 may be located closer to the second boundary line B2 than to the first boundary line B1. The first crack portion C11 preferably has a shape that is linked to the second boundary line B2. The second crack portion C12 preferably has a shape that is linked to the second boundary line B2. At least one of the first crack portion C11 and the second crack portion C12 preferably extends in a shape that follows the second boundary line B2, which serves as a boundary line between plating layers.

[0164] The shape interlocking between the first crack portion C11 and the second boundary line B2 is higher than the shape interlocking between the first crack portion C11 and the first boundary line B1. The first crack portion C11 has an uneven shape that follows the uneven shape of the second boundary line B2. The first crack portion C11 may have an uneven shape that follows the uneven shape of the first boundary line B1.

[0165] The shape interlocking between the second crack portion C12 and the second boundary line B2 is higher than the shape interlocking between the second crack portion C12 and the first boundary line B1. The second crack portion C12 has an uneven shape that follows the uneven shape of the second boundary line B2. The second crack portion C12 may have an uneven shape that follows the uneven shape of the first boundary line B1. It can be said that at least one of the first crack portion C11 and the second crack portion C12 extends in a shape that follows the second boundary line B2, which is the boundary line between the plating layers.

[0166] The length of the crack C is preferably 10 μm or more and 200 μm or less. This allows the stress on the laminate to be more effectively alleviated even when force is applied to the external electrode while maintaining the basic strength of the external electrode. If the length is less than 10 μm, the effects of the present disclosure may be limited. If the length exceeds 200 μm, the strength of the external electrode may be slightly reduced. The length of the crack C may be 30 μm or more and 100 μm or less. In the example of FIG. 6, the first crack C11 is longer than the second crack C12. However, this is not limited to this. The length of the crack C may be equal to or greater than the thickness of the main surface-side plating layer 602.

[0167] The maximum width perpendicular to the extension direction of the crack portion C, i.e., the maximum gap created by the crack portion C, is preferably 0.05 μm or more and 5 μm or less, and more preferably 0.05 μm or more and 1 μm or less. This allows the external electrode to maintain its basic strength while more effectively alleviating stress on the laminate even when force is applied to the external electrode. If the width is less than 0.05 μm, the effects of the present disclosure may be limited. If the width exceeds 1 μm, the strength of the external electrode may be slightly reduced, and if the width exceeds 5 μm, the strength of the external electrode may be reduced. The maximum width perpendicular to the extension direction of the crack portion C may be 0.1 μm or more and 0.5 μm or less. In the example of FIG. 7, the first crack portion C11 is longer than the second crack portion C12. However, this is not limited to this.

[0168] The first crack portion C11 preferably has at least a rising portion C11s rising from and extending from the main surface TS of the laminate 10, and a rounded portion C11r bending in a direction along the main surface TS of the laminate 10. The rounded portion C11r in this modification corresponds to a curved portion. This allows for more effective relaxation of stress on the laminate even when force is applied to the external electrode. More preferably, the first crack portion C11 further has an extending portion C11e extending along the main surface TS of the laminate 10, as shown in FIG. 7. That is, the first crack portion C11 preferably has a rising portion C11s rising from and extending from the main surface TS of the laminate 10, an extending portion C11e extending along the main surface TS of the laminate 10, and a rounded portion C11r connecting the rising portion C11s and the extending portion C11e. The extending portion C11e may be longer than the rising portion C11s. The rising portion C11s, the extending portion C11e, and the rounded portion C11r of the first crack portion C11 are disposed at positions corresponding to the rising portion B2s, the extending portion B2e, and the rounded portion B2r of the second boundary line B2.

[0169] The second crack portion C12 preferably has at least a rising portion C12s that rises and extends from the main surface TS of the laminate 10 and a rounded portion C12r that curves in a direction along the main surface TS of the laminate 10. The rounded portion C12r in this modification corresponds to a curved portion. This allows for more effective relaxation of stress on the laminate even when force is applied to the external electrode. As shown in FIG. 7, the second crack portion C12 in this modification does not have an extending portion C12e that extends along the main surface TS of the laminate 10, but is not limited to this and may have an extending portion C12e. The rising portion C12s and rounded portion C12r of the second crack portion C12 are located at positions corresponding to the rising portion B2s and rounded portion B2r of the second boundary line B2.

[0170] The radius of curvature of the rounded portion C11r of the first crack portion C11 may be smaller than the radius of curvature of the rounded portion B2r of the second boundary line B2.

[0171] The radius of curvature of the rounded portion C12r of the second crack portion C12 may be smaller than the radius of curvature of the rounded portion B2r of the second boundary line B2. The radius of curvature of the rounded portion C12r of the second crack portion C12 may be smaller than the radius of curvature of the rounded portion C11r of the first crack portion C11.

[0172] In this way, by creating cracks in the Ni plating of the chip from the beginning before mounting on the board, stress from the mounting area is alleviated when the chip bends after being mounted on the board, improving bending resistance.

[0173] The cracks C may be located in at least one of the first external electrode 40A and the second external electrode 40B. However, if the cracks C are located in both the first external electrode 40A and the second external electrode 40B, the occurrence of cracks in the laminate 10 can be more effectively suppressed.

[0174] If the lengthwise dimension of the multilayer ceramic capacitor 1 including the laminate 10 and the external electrodes 40 is defined as L, then the L dimension is preferably 0.2 mm or more and 10 mm or less. If the lengthwise dimension of the multilayer ceramic capacitor 1 in the stacking direction is defined as T, then the T dimension is preferably 0.1 mm or more and 10 mm or less. The widthwise dimension of the multilayer ceramic capacitor 1 is defined as W. The W dimension is preferably 0.1 mm or more and 10 mm or less.

[0175] <Method for measuring crack length and curvature radius> The LT cross section at the center of the width direction W of the laminate 10 is exposed by polishing. Next, the exposed LT cross section is used as the measurement object, and the length of the crack and the radius of curvature of the crack, etc. are measured using a digital microscope. Note that the rounded portion of the crack is curve-fitted to an arc, and then its radius of curvature is measured.

[0176] <Manufacturing method> Next, a method for manufacturing the multilayer ceramic capacitor 1 of this embodiment will be described. The method for manufacturing the multilayer ceramic capacitor 1 of this embodiment is not limited as long as it satisfies the above-mentioned requirements. However, a suitable manufacturing method includes the following steps. Each step will be described in detail below.

[0177] A dielectric sheet for the dielectric layer 20 and a conductive paste for the internal electrode layer 30 are prepared. The dielectric sheet and the conductive paste for the internal electrode contain a binder and a solvent. The binder and the solvent may be known.

[0178] On the dielectric sheets, a conductive paste for the internal electrode layers 30 is printed in a predetermined pattern by, for example, screen printing, gravure printing, etc. In this way, a dielectric sheet on which the pattern of the first internal electrode layer 31 is formed and a dielectric sheet on which the pattern of the second internal electrode layer 32 is formed are prepared.

[0179] A predetermined number of dielectric sheets without a printed internal electrode layer pattern are stacked to form a portion that will become the first main surface-side outer layer portion 12A on the first main surface TS1 side. A dielectric sheet with a printed first internal electrode layer pattern and a dielectric sheet with a printed second internal electrode layer pattern are stacked in this order on top of that to form a portion that will become the internal layer portion 11. A predetermined number of dielectric sheets without a printed internal electrode layer pattern are stacked on top of this portion that will become the internal layer portion 11 to form a portion that will become the second main surface-side outer layer portion 12B on the second main surface TS2 side. In this way, a laminated sheet is produced.

[0180] The laminated sheets are pressed in the lamination direction by means of a hydrostatic press or the like to produce a laminated block.

[0181] The laminated block is cut to a predetermined size to cut out laminated chips, and at this time, corners and ridges of the laminated chips may be rounded by barrel polishing or the like.

[0182] The laminated chip is fired to produce the laminate 10. The firing temperature depends on the materials of the dielectric layers 20 and the internal electrode layers 30, but is preferably 900°C or higher and 1400°C or lower.

[0183] A conductive paste that will become the baked layer 51 of the base electrode layer 50 is applied to both end surfaces of the laminate 10. The conductive paste containing a glass component and a metal is applied to the laminate 10 by a method such as dipping. A baking process is then performed to form the baked layer 51 of the base electrode layer 50. The temperature of the baking process at this time is preferably 700°C or higher and 950°C or lower.

[0184] In this embodiment, dipping is performed so that the first baking layer 51A extends from the first end face LS1 to parts of the first main surface TS1 and the second main surface TS2. Dipping is also performed so that the second baking layer 51B extends from the second end face LS2 to parts of the first main surface TS1 and the second main surface TS2. At the same time, dipping is preferably performed so that the first baking layer 51A extends to parts of the first side surface WS1 and the second side surface WS2. Dipping is also preferably performed so that the second baking layer 51B extends to parts of the first side surface WS1 and the second side surface WS2.

[0185] The laminated chip before firing and the conductive paste applied to the laminated chip may be fired simultaneously. In this case, the fired layer is preferably formed by firing a material containing a ceramic material instead of a glass component. In this case, it is particularly preferable to use the same type of ceramic material as the dielectric layer 20 as the added ceramic material. In this case, the conductive paste is applied to the laminated chip before firing, and the laminated chip and the conductive paste applied to the laminated chip are fired simultaneously to form the laminate 10 with the fired layer.

[0186] Next, the conductive resin layer 52 of the base electrode layer 50 is formed. The conductive resin layer 52 may be formed on the surface of the baked layer 51 of the base electrode layer 50, or may be formed directly on the laminate 10. In this embodiment, the conductive resin layer 52 is formed on the surface of the baked layer 51 of the base electrode layer 50. The conductive resin layer 52 does not necessarily have to be provided.

[0187] First, a conductive resin paste is prepared by dispersing conductive fillers in a thermosetting resin as a base resin for the resin portion. This conductive resin paste is produced by stirring and mixing the thermosetting resin and conductive fillers. Therefore, the conductive fillers are uniformly dispersed within the conductive resin paste. Here, the thermosetting resin is, for example, an epoxy resin. The conductive filler is, for example, Ag metal powder.

[0188] Thereafter, a conductive resin paste is applied onto the base electrode layer 50 using a dipping method, and a heat treatment is performed at a temperature of 200°C to 550°C. This causes the resin to thermally harden, forming the conductive resin layer 52. The atmosphere during this heat treatment is preferably an N2 atmosphere. Furthermore, to prevent the resin from scattering and the various metal components from oxidizing, it is preferable that the oxygen concentration be kept below 100 ppm.

[0189] In this embodiment, dipping is performed so that the first conductive resin layer 52A extends from the first end face LS1 to parts of the first main surface TS1 and the second main surface TS2. Also, dipping is performed so that the second conductive resin layer 52B extends from the second end face LS2 to parts of the first main surface TS1 and the second main surface TS2. At the same time, dipping is preferably performed so that the first conductive resin layer 52A extends to parts of the first side surface WS1 and the second side surface WS2. Also, dipping is preferably performed so that the second conductive resin layer 52B extends to parts of the first side surface WS1 and the second side surface WS2.

[0190] Thereafter, a plating layer 60 is formed on the surface of the conductive resin layer 52. In this embodiment, a Ni plating layer as a lower plating layer 61 and a Sn plating layer as an upper plating layer 62 are formed on the conductive resin layer 52. The Ni plating layer and the Sn plating layer are formed sequentially using an electrolytic plating method. As the plating method, for example, barrel plating is preferably used.

[0191] Here, during the plating process using barrel plating, current is applied for a predetermined time, then temporarily stopped, and then resumed. By adjusting the time when current is stopped and the amount of current applied, a crystal layer interface where cracks occur can be formed, and cracks can be formed along the second boundary line of the present disclosure. By making such adjustments, it is possible to form cracks C having an uneven shape that is linked to the second boundary line. Cracks may also be formed along the first boundary line. Furthermore, by adjusting the timing of stopping current application, the positional relationship between the first boundary line, the second boundary line, and the cracks can be adjusted. Furthermore, the number of cracks can be adjusted by the number of times current application is stopped.

[0192] By the above manufacturing method, the multilayer ceramic capacitor 1 is manufactured.

[0193] The multilayer ceramic capacitor 1 of this embodiment provides the following advantages.

[0194] In recent years, ceramic electronic components, such as multilayer ceramic capacitors, have come to be used in harsher environments than before. For example, electronic components used in mobile devices such as mobile phones and portable music players are required to be able to withstand shocks when dropped. Specifically, it is necessary to ensure that the electronic components do not fall off the mounting board or crack even when subjected to a drop shock.

[0195] Furthermore, electronic components used in in-vehicle devices such as ECUs (Electronic Control Units) are required to withstand the impact of thermal cycles. Specifically, they must be able to withstand the bending stresses that occur when the mounting board expands and contracts during thermal cycles, preventing cracks from forming in the electronic components.

[0196] In response to this, the use of thermosetting conductive resin paste for the external electrodes of ceramic electronic components has been proposed as a measure to prevent cracks from occurring in the ceramic electronic component body even in harsh environments. For example, an epoxy-based thermosetting resin layer is formed between the conventional baked layer and the Ni-plated layer.

[0197] In this configuration, when stress is applied due to an impact when dropped or large board deflection stress generated by the thermal expansion and contraction of the mounting board due to a thermal cycle, the stress transmitted to the mounting board due to the distortion of the mounting board is transferred to the mounting board by causing fracture cracks starting from the tip of the conductive resin layer of the external electrode inside the conductive resin layer, at the interface between the conductive resin layer and the plating layer, or at the interface between the conductive resin layer and the laminate, thereby providing a fail-safe function that releases the stress applied to the laminated chip and preventing cracks from progressing in the laminate.

[0198] However, when a larger stress is applied, the fracture crack may not occur at the above-mentioned point, but may propagate into the interior of the laminate.

[0199] In the present invention, by initially creating cracks in the plating layer of the laminated chip before mounting it on a substrate, stress from the mounting portion can be alleviated when the chip bends after being mounted on the substrate, thereby improving resistance to bending.

[0200] (1) The multilayer ceramic capacitor 1 (multilayer ceramic electronic component 1) according to this embodiment includes a laminate 10 including a plurality of laminated dielectric layers 20 (ceramic layers 20) and a plurality of internal electrode layers 30 (internal conductor layers 30), and having a first main surface TS1 and a second main surface TS2 facing in a height direction T, a first side surface WS1 and a second side surface WS2 facing in a width direction W perpendicular to the height direction T, and a first end surface LS1 and a second end surface LS2 facing in a length direction L perpendicular to the height direction T and the width direction W, a first external electrode 40A arranged on the first end surface LS1, and a second external electrode 40B arranged on the second end surface LS2. In the multilayer ceramic capacitor 1 (multilayer ceramic electronic component 1), at least one of the first external electrode 40A and the second external electrode 40B has a main surface-side base electrode layer 502 arranged on at least one of the first main surface TS1 and the second main surface TS2, and a main surface-side plating layer 602 formed above the main surface-side base electrode layer 502, and in a cross section along a plane parallel to the length direction and the height direction, the main surface-side plating layer 602 has one or more crack portions C extending into a region between a boundary line (first boundary line B1) between the main surface-side base electrode layer 502 and the main surface-side plating layer 602 and a profile line Sp on the surface of the main surface-side plating layer 602.

[0201] This makes it possible to provide a multilayer ceramic electronic component that can suppress the occurrence of cracks in the laminate.

[0202] (2) In the multilayer ceramic capacitor 1 of this embodiment, the main surface side plating layer 602 includes a main surface side lower layer plating layer 612 arranged on the main surface side base electrode layer 502 and a main surface side upper layer plating layer 622 located in the uppermost layer of the main surface side plating layer 602.

[0203] This makes it possible to provide a multilayer ceramic electronic component that can suppress the occurrence of cracks in the laminate while providing the plating layer with multiple properties.

[0204] (3) In the multilayer ceramic capacitor 1 of this embodiment, the main surface side upper plating layer 622 is arranged on the main surface side lower plating layer 612, and in a cross section parallel to the length and height directions, the crack portion C extends within the region between the first boundary line B1 and the inter-plating layer boundary line (second boundary line B2), which is the boundary line between the main surface side lower plating layer 612 and the main surface side upper plating layer 622.

[0205] By providing a crack portion in the lower plating layer, which is less likely to melt during soldering than the upper plating layer, it is possible to leave the plating layer with the crack portion even after soldering, which more effectively suppresses the occurrence of cracks in the laminate when mounted.

[0206] (4) In the multilayer ceramic capacitor 1 of this embodiment, the main surface-side lower plating layer 612 is a Ni plating layer, the main surface-side upper plating layer 622 is a Sn plating layer, and the crack C extends within the Ni plating layer.

[0207] By providing the crack portion C in the Ni plating layer, which is made of a metal that does not melt easily during soldering, rather than in the Sn plating layer, which is made of a metal that melts easily during soldering, it is possible to leave the plating layer with the crack portion even after soldering, and the occurrence of cracks in the laminate can be more effectively suppressed when mounted.

[0208] (5) In the multilayer ceramic capacitor 1 of this embodiment, at least one of the one or more crack portions C extends in a shape that follows the boundary line between the plating layers.

[0209] This reduces local increases and decreases in the thickness of the plating layer on both sides of the crack and avoids stress concentration, thereby maintaining the basic strength of the external electrode and more effectively alleviating the stress on the laminate even when force is applied to the external electrode.

[0210] (6) In the multilayer ceramic capacitor 1 of this embodiment, the main surface side plating layer 602 has a main surface side intermediate plating layer 632 arranged between the main surface side lower layer plating layer 612 and the main surface side upper layer plating layer 622, and the crack portion C (first crack portion C10) extends within the region between the first boundary line B1 and the first inter-plating layer boundary line B3, which is the boundary line between the main surface side lower layer plating layer 621 and the main surface side intermediate plating layer 632.

[0211] By providing the cracks in the lower plating layer, which is less likely to melt during soldering than the upper plating layer, the occurrence of cracks in the laminate can be more effectively suppressed in the mounted state.

[0212] (7) In the multilayer ceramic capacitor 1 of this embodiment, the main surface side plating layer 602 has a main surface side intermediate plating layer 632 arranged between the main surface side lower layer plating layer 612 and the main surface side upper layer plating layer 622, and the crack portion (second crack portion C20) extends within the region between the first inter-plating layer boundary line B3, which is the boundary line between the main surface side lower layer plating layer 612 and the main surface side intermediate plating layer 632, and the second inter-plating layer boundary line B4, which is the boundary line between the main surface side intermediate plating layer 632 and the main surface side upper layer plating layer 622.

[0213] By providing the cracks in the intermediate plating layer, which is less likely to melt during soldering than the upper plating layer, the occurrence of cracks in the laminate can be more effectively suppressed.

[0214] (8) In the multilayer ceramic capacitor 1 of this embodiment, the main-surface-side base electrode layer 502 includes a main-surface-side conductive resin layer 522 .

[0215] This makes it possible to further suppress the occurrence of cracks in the laminate due to the presence of both the conductive resin layer, which has the function of sacrificial fracture and stress relief through deformation, and the cracks in the plating layer.

[0216] (9) In the multilayer ceramic capacitor 1 of this embodiment, the one or more cracks C are a plurality of cracks C, and the plurality of cracks C extend in parallel curved lines.

[0217] This reduces local increases and decreases in the thickness of the plating layer between multiple cracks, and avoids stress concentration, so that the basic strength of the external electrode is maintained while more effectively alleviating the stress on the laminate even when force is applied to the external electrode.

[0218] In the multilayer ceramic capacitor 1 according to the above embodiment, the external electrode 40 includes the main surface-side conductive resin layer 522 disposed on the main surface-side baked layer 512. However, this is not limiting. For example, the external electrode 40 does not need to include the main surface-side conductive resin layer 522 on the main surface-side baked layer 512. In this case, the main surface-side lower plating layer 612 may include a crack C extending into the region between the second boundary line B2, which is the boundary line between the main surface-side lower plating layer 612 and the main surface-side upper plating layer 622, and the first boundary line B1, which is the boundary line between the main surface-side lower plating layer 612 and the main surface-side baked layer 512. By initially generating a crack in the Ni plating of the chip before mounting on the substrate, the multilayer ceramic capacitor 1 can relieve stress from the mounting portion when the chip bends after mounting on the substrate, improving bending resistance and achieving the effects of the present disclosure.

[0219] The configuration of the multilayer ceramic capacitor 1 is not limited to the configurations shown in Figures 1 to 7. For example, the multilayer ceramic capacitor 1 may be a multilayer ceramic capacitor having a series structure such as a double structure, a triple structure, or a quadruple structure, as shown in Figures 8, 9, and 10. The effects of the present disclosure can be obtained even when the multilayer ceramic capacitor 1 has the above structure.

[0220] The multilayer ceramic capacitor 1 shown in FIG. 8 is a double-structure multilayer ceramic capacitor 1, and includes, as the internal electrode layers 30, a first internal electrode layer 33, a second internal electrode layer 34, and a floating internal electrode layer 35 that is not extended to either the first end face LS1 or the second end face LS2. The multilayer ceramic capacitor 1 shown in FIG. 9 is a triple-structure multilayer ceramic capacitor 1, which includes a first floating internal electrode layer 35A and a second floating internal electrode layer 35B as the floating internal electrode layers 35. The multilayer ceramic capacitor 1 shown in FIG. 10 is a quadruple-structure multilayer ceramic capacitor 1, which includes a first floating internal electrode layer 35A, a second floating internal electrode layer 35B, and a third floating internal electrode layer 35C as the floating internal electrode layers 35. By providing the floating internal electrode layers 35 as the internal electrode layers 30 in this way, the multilayer ceramic capacitor 1 has a structure in which the opposing electrode portion is divided into multiple parts. As a result, multiple capacitor components are formed between the opposing internal electrode layers 30, and these capacitor components are connected in series. This reduces the voltage applied to each capacitor component, thereby achieving a high withstand voltage for the multilayer ceramic capacitor 1. It goes without saying that the multilayer ceramic capacitor 1 of this embodiment may have a multi-row structure of four or more rows.

[0221] The multilayer ceramic capacitor 1 may be a two-terminal type having two external electrodes, or may be a multi-terminal type having many external electrodes. The effects of the present disclosure can be obtained even when the multilayer ceramic capacitor 1 has a multi-terminal structure.

[0222] In the above-described embodiment, a multilayer ceramic capacitor is used as an example of a multilayer ceramic electronic component, in which the dielectric layers 20 made of a dielectric ceramic are used as ceramic layers. However, the multilayer ceramic electronic component of the present disclosure is not limited to this. For example, the ceramic electronic component of the present disclosure can also be applied to various other multilayer ceramic electronic components, such as piezoelectric components using piezoelectric ceramic as ceramic layers, thermistors using semiconductor ceramic as ceramic layers, and inductors using magnetic ceramic as ceramic layers. Examples of piezoelectric ceramics include PZT (lead zirconate titanate) ceramics, examples of semiconductor ceramics include spinel ceramics, and examples of magnetic ceramics include ceramics such as ferrite. The effects of the present disclosure can also be obtained with multilayer ceramic electronic components other than multilayer ceramic capacitors.

[0223] The present invention is not limited to the configurations of the above-described embodiments, and can be appropriately modified and applied within the scope of the present invention. Note that the present invention also includes a combination of two or more of the individual desirable configurations described in the above-described embodiments.

[0224] <1> a laminate including a plurality of laminated ceramic layers and a plurality of internal conductor layers, the laminate having a first main surface and a second main surface opposing each other in a height direction, a first side surface and a second side surface opposing each other in a width direction perpendicular to the height direction, and a first end surface and a second end surface opposing each other in a length direction perpendicular to the height direction and the width direction; a first external electrode disposed on the first end face; and a second external electrode disposed on the second end face. A multilayer ceramic electronic component having: At least one of the first external electrode and the second external electrode is a main surface-side base electrode layer disposed on at least one of the first main surface and the second main surface; a main surface-side plating layer formed above the main surface-side base electrode layer, a multilayer ceramic electronic component, wherein, in a cross section taken along a plane parallel to the length direction and the height direction, the main surface side plating layer has one or more cracks extending into a region between a boundary line between the main surface side base electrode layer and the main surface side plating layer and a profile line on the surface of the main surface side plating layer. <2> The main surface side plating layer is a main surface-side underlayer plating layer disposed on the main surface-side base electrode layer; a main surface-side upper plating layer located as an uppermost layer in the main surface-side plating layer, <1> The multilayer ceramic electronic component according to claim 1. <3> the main surface-side upper plating layer is disposed on the main surface-side lower plating layer, and in a cross section along a plane parallel to the length direction and the height direction, the crack portion extends within a region between the boundary line and an inter-plating layer boundary line which is a boundary line between the main surface-side lower plating layer and the main surface-side upper plating layer. <2> The multilayer ceramic electronic component according to claim 1. <4> the main surface-side lower plating layer is a Ni plating layer, the main surface-side upper plating layer is a Sn plating layer, and the crack portion extends within the Ni plating layer; <2> or <3> The multilayer ceramic electronic component according to claim 1. <5> At least one of the one or more crack portions extends in a shape along the boundary line between the plating layers. <3> or <4> The multilayer ceramic electronic component according to claim 1. <6> the main surface side plating layer has a main surface side intermediate plating layer disposed between the main surface side lower layer plating layer and the main surface side upper layer plating layer, the crack portion extends within a region between the boundary line and a first inter-plating layer boundary line, which is a boundary line between the main surface-side lower plating layer and the main surface-side intermediate plating layer. <2> The multilayer ceramic electronic component according to claim 1. <7> the main surface side plating layer has a main surface side intermediate plating layer disposed between the main surface side lower layer plating layer and the main surface side upper layer plating layer, the crack portion extends within a region between a first inter-plating layer boundary line, which is a boundary line between the main surface side lower plating layer and the main surface side intermediate plating layer, and a second inter-plating layer boundary line, which is a boundary line between the main surface side intermediate plating layer and the main surface side upper plating layer. <2> The multilayer ceramic electronic component according to claim 1. <8> the principal surface-side base electrode layer includes a principal surface-side conductive resin layer, <1> ~ <7> 10. The multilayer ceramic electronic component according to claim 9, wherein the first and second electrodes are formed on the first and second substrates. <9> The one or more crack portions are a plurality of crack portions, and the plurality of crack portions extend in parallel curved lines to each other. <1> ~ <8> 10. The multilayer ceramic electronic component according to claim 9, wherein the first and second electrodes are formed on the first and second substrates. [Explanation of symbols]

[0225] 1. Multilayer ceramic capacitors (multilayer ceramic electronic components) 10 Laminate 20 Dielectric layer (ceramic layer) 31 First internal electrode layer (first internal conductor layer) 32 Second internal electrode layer (second internal conductor layer) 40 External electrode 40A First outer electrode 40B Second external electrode 502 Main surface side base electrode layer 522 Main surface conductive resin layer 602 Main surface plating layer 612 Main surface undercoat layer 622 Main surface upper plating layer C Cracked part B1 1st boundary line B2 2nd boundary line T Height direction TS1 First principal surface TS2 Second principal surface W width direction WS1 First Aspect WS2 Second Aspect L lengthwise LS1 First end face LS2 Second end face

Claims

1. a laminate including a plurality of laminated ceramic layers and a plurality of internal conductor layers, the laminate having a first main surface and a second main surface opposing each other in a height direction, a first side surface and a second side surface opposing each other in a width direction perpendicular to the height direction, and a first end surface and a second end surface opposing each other in a length direction perpendicular to the height direction and the width direction; a first external electrode disposed on the first end surface; and a second external electrode disposed on the second end surface. A multilayer ceramic electronic component having: At least one of the first external electrode and the second external electrode is a main surface-side base electrode layer disposed on at least one of the first main surface and the second main surface; a main surface-side plating layer formed above the main surface-side base electrode layer, a multilayer ceramic electronic component, wherein, in a cross section taken along a plane parallel to the length direction and the height direction, the main surface side plating layer has one or more cracks extending into a region between a boundary line between the main surface side base electrode layer and the main surface side plating layer and a profile line on the surface of the main surface side plating layer.

2. The main surface side plating layer is a main surface-side underlayer plating layer disposed on the main surface-side base electrode layer; 2. The multilayer ceramic electronic component according to claim 1, further comprising: a main surface-side upper plating layer located as an uppermost layer of the main surface-side plating layers.

3. 3. The multilayer ceramic electronic component according to claim 2, wherein the main surface-side upper plating layer is disposed on the main surface-side lower plating layer, and in a cross section along a plane parallel to the length direction and the height direction, the crack portion extends within a region between the boundary line and an inter-plating layer boundary line that is the boundary line between the main surface-side lower plating layer and the main surface-side upper plating layer.

4. 4. The multilayer ceramic electronic component according to claim 3, wherein the main surface-side lower plating layer is a Ni plating layer, the main surface-side upper plating layer is a Sn plating layer, and the crack portion extends within the Ni plating layer.

5. The multilayer ceramic electronic component according to claim 3 , wherein at least one of the one or more crack portions extends in a shape that follows the boundary line between the plating layers.

6. the main surface side plating layer has a main surface side intermediate plating layer disposed between the main surface side lower layer plating layer and the main surface side upper layer plating layer, 3. The multilayer ceramic electronic component according to claim 2, wherein the crack portion extends within a region between the boundary line and a first inter-plating layer boundary line, which is a boundary line between the main surface-side lower layer plating layer and the main surface-side intermediate plating layer.

7. the main surface side plating layer has a main surface side intermediate plating layer disposed between the main surface side lower layer plating layer and the main surface side upper layer plating layer, 3. The multilayer ceramic electronic component according to claim 2, wherein the crack portion extends within a region between a first inter-plating layer boundary line, which is a boundary line between the main surface side lower-layer plating layer and the main surface side intermediate plating layer, and a second inter-plating layer boundary line, which is a boundary line between the main surface side intermediate plating layer and the main surface side upper-layer plating layer.

8. 3. The multilayer ceramic electronic component according to claim 1, wherein the main-surface-side base electrode layer includes a main-surface-side conductive resin layer.

9. 3. The multilayer ceramic electronic component according to claim 1, wherein the one or more cracks comprise a plurality of cracks, and the plurality of cracks extend in parallel curved lines.

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