Semiconductor Package

Abstract

A semiconductor package according to an embodiment includes a first substrate including first and second pads, a first connection portion arranged on the first pad of the first substrate, a second substrate coupled onto the first connection portion, a second connection portion arranged on the second pad of the first substrate, an element mounted on the second connection portion, and a molding layer arranged on the first substrate for molding the element, the element including at least one of a capacitor and an inductor, and the second substrate includes a pattern layer that performs a function different from that of the element among the capacitor and the inductor.

Description

[Technical field]

[0001] The embodiments relate to a semiconductor package, and more particularly to a semiconductor package including an inductor substrate. [Background technology]

[0002] In the current electronic product market, the demand for portable electronic products is increasing rapidly, and in order to satisfy this demand, it is essential that the components mounted in the systems be made lighter, thinner, shorter and smaller.

[0003] In order to make the above components lighter, thinner, shorter, and smaller, technology is required to reduce the individual size of mounted components, SOC (System On Chip) technology to integrate multiple individual elements into one chip, and SIP (System In Package) technology to integrate multiple individual elements into one package.

[0004] Recently, in response to the trend toward multi-functionality and miniaturization of mobile communication terminals such as mobile phones, PDAs (Personal Digital Assistants), and smartphones, as well as various media terminals, various components built into terminals or modules built into handsets are being developed with a tendency to become smaller. In order to miniaturize such modules, research is being conducted into realizing components such as RF (Radio Frequency) elements and IC chips in a single package.

[0005] As a result, conventional semiconductor packages reduce the overall volume by mounting an integrated passive device (IPD) on a substrate. However, when multiple integrated passive devices are placed on a single substrate, problems with electrical reliability arise due to interference between them. Summary of the Invention [Problem to be solved by the invention]

[0006] The embodiments provide a semiconductor package with improved electrical reliability.

[0007] Also, the embodiment provides a semiconductor package capable of minimizing interference between them by arranging a second substrate fulfilling the function of a second element on a first substrate on which a first element is arranged.

[0008] Furthermore, the embodiment provides a semiconductor package that can dramatically reduce the thickness of the second substrate that performs the function of the second element.

[0009] Also, an embodiment provides a semiconductor package including a second substrate on which a plurality of coil patterns having different inductance values ​​are formed on one insulating layer.

[0010] Moreover, the embodiment provides a semiconductor package that can be slimmed down in thickness.

[0011] The technical problems to be solved in the embodiments are not limited to those mentioned above, and other technical problems not mentioned will be clearly understood by a person having ordinary skill in the art to which the present invention pertains from the following description. [Means for solving the problem]

[0012] A semiconductor package according to an embodiment includes a first substrate including first and second pads, a first connection portion arranged on the first pad of the first substrate, a second substrate coupled onto the first connection portion, a second connection portion arranged on the second pad of the first substrate, an element mounted on the second connection portion, and a molding layer arranged on the first substrate for molding the element, the element including at least one of a capacitor and an inductor, and the second substrate includes a pattern layer that performs a function different from that of the element among the capacitor and the inductor.

[0013] The second substrate also includes a second insulating layer, a second circuit pattern disposed on the second insulating layer and corresponding to the pattern layer, and a second through electrode penetrating the second insulating layer.

[0014] The second substrate further includes a second protective layer disposed on an upper surface and a lower surface of the second insulating layer, and the molding layer molds the element at a position spaced apart from the second substrate.

[0015] Additionally, the molding layer molds the second insulating layer and the second circuit pattern of the second substrate.

[0016] The second substrate is an inductor substrate including a coil pattern that forms an inductance, and the elements include a first element corresponding to a capacitor and a second element that is spaced apart from the first element and corresponds to an inductor.

[0017] The second substrate is a capacitor substrate including a capacitor pattern forming a capacitance, and the elements include a first element corresponding to a capacitor and a second element spaced apart from the first element and corresponding to an inductor.

[0018] The second circuit pattern also includes a first pattern layer disposed on an upper surface of the second insulating layer and a second pattern layer disposed on a lower surface of the second insulating layer, the first pattern layer including a plurality of coil patterns, the plurality of coil patterns including a first coil pattern having a first separation distance from the second pattern layer and a second coil pattern having a second separation distance from the second pattern layer that is different from the first separation distance.

[0019] The first coil pattern is disposed in a pattern groove formed in the upper surface of the second insulating layer, and the second coil pattern protrudes above the upper surface of the second insulating layer.

[0020] In addition, the first coil pattern is disposed in a first groove having a first depth formed in the upper surface of the second insulating layer, and the second coil pattern is disposed in a second groove having a second depth different from the first depth formed in the upper surface of the second insulating layer.

[0021] The second insulating layer includes a photo-imaginable dielectric resin (PID). Effect of the Invention

[0022] The semiconductor package of the embodiment includes a first substrate and a second substrate, and the semiconductor package includes at least one element mounted on the first substrate, and the second substrate is mounted on the first substrate and can function as an inductor or a capacitor.

[0023] Specifically, in the embodiment, one of the inductor and the capacitor is configured as an element having a die shape, and the other is configured as an element having a substrate shape. As a result, the embodiment can secure design space for the semiconductor package, thereby securing design freedom. Furthermore, the embodiment can realize the inductor and the capacitor as different types from each other, thereby solving a reliability problem that may occur between them. For example, when the inductor and the capacitor are arranged adjacent to each other, a problem may occur in that the characteristics of each function are deteriorated due to interference between them. As a result, the embodiment can realize the inductor and the capacitor as different types from each other, thereby solving the problem of deterioration of the characteristics of each function. Furthermore, the embodiment can maximize the characteristics of the inductor function and the capacitor function, thereby further improving the reliability of the product.

[0024] Also, the embodiment includes a plurality of inductors or a plurality of capacitors. Any one of the plurality of inductors is configured as a die-shaped element, and another inductor is configured as a substrate. Also, in the embodiment, another capacitor of the plurality of capacitors is configured as a die-shaped element, and another capacitor is configured as a substrate.

[0025] Through this, the embodiment can further maximize the inductor function or capacitor function, thereby further improving product performance.

[0026] Also, the second substrate of the embodiment includes a second insulating layer including a photosensitive material. And, the pattern layer of the second substrate is inserted into the groove of the second insulating layer or has a protruding structure. Also, the groove of the second insulating layer may include a plurality of grooves having different depths, and the pattern layer may be disposed in each of the plurality of grooves. Through this, the embodiment can realize a plurality of inductances with one second substrate. Through this, the embodiment can further improve product performance. [Brief description of the drawings]

[0027] [Figure 1] FIG. 1 is a diagram showing a semiconductor package according to a first embodiment. [Diagram 2] FIG. 13 is a diagram showing a semiconductor package according to a second embodiment. [Figure 3a] 3 is a diagram showing a first pattern layer of a second circuit pattern of the second substrate of FIG. 1 or FIG. 2; [Figure 3b] 3 shows a second pattern layer of a second circuit pattern of the second substrate of FIG. 1 or FIG. 2. FIG. [Figure 3c] 1 or 2. FIG. 4 shows a third pattern layer of the second circuit pattern of the second substrate of FIG. [Figure 4] FIG. 4 is a diagram showing a specific layer structure of a second substrate in the first embodiment. [Diagram 5] FIG. 11 is a diagram showing a specific layer structure of a second substrate according to the second embodiment. [Figure 6] FIG. 13 is a diagram showing a specific layer structure of a second substrate in accordance with the third embodiment. [Figure 7] FIG. 13 is a diagram showing a specific layer structure of a second substrate in accordance with a fourth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0028] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0029] However, the technical concept of the present invention is not limited to the embodiments described, but may be realized in various different forms, and one or more of the components of the embodiments may be selectively combined or substituted for each other within the scope of the technical concept of the present invention.

[0030] Furthermore, unless otherwise clearly defined and described, terms (including technical and scientific terms) used in the embodiments of the present invention are to be interpreted as meanings that may be commonly understood by a person having ordinary knowledge in the technical field to which the present invention belongs, and commonly used terms, such as terms defined in a dictionary, may be interpreted in light of the contextual meaning of the relevant art.

[0031] In addition, the terms used in the examples of the present invention are intended to describe the examples and are not intended to limit the present invention. In this specification, the singular form can include the plural form unless otherwise specified in the phrase, and when it is described as "A and (and) at least one (or one or more) of B and C", it can include one or more of all combinations that can be combined with A, B, and C.

[0032] In addition, when describing components of the embodiments of the present invention, terms such as first, second, A, B, (a), (b), etc. may be used. Such terms are merely used to distinguish the components from other components, and do not limit the essence, order, or procedure of the components. Furthermore, when a component is described as being "coupled," "coupled," or "connected" to another component, it may include not only the case where the component is directly coupled, coupled, or connected to the other component, but also the case where the component is "coupled," "coupled," or "connected" between the other component and the other component or by another component.

[0033] In addition, when described as being formed or located "above or below" each component, "above" or "below" includes not only the case where two components are in direct contact with each other, but also the case where one or more other components are formed or located between the two components. In addition, when described as "above or below," it can include not only the upper direction based on one component, but also the lower direction.

[0034] -Electronic Devices-

[0035] Prior to describing the embodiment, an electronic device including a semiconductor package of the embodiment will be briefly described. The electronic device includes a main board (not shown). The main board may be physically and / or electrically connected to various components. For example, the main board may be connected to the semiconductor package of the embodiment. Various chips may be mounted on the semiconductor package. Mainly, the semiconductor package may include various elements or chips. The elements or chips may include memory chips such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM), and flash memory, application processor chips such as central processors (e.g., CPUs), graphic processors (e.g., GPUs), digital signal processors, encryption processors, microprocessors, and microcontrollers, and logic chips such as analog-to-digital converters and application-specific ICs (ASICs).

[0036] Additionally, the device or chip may include active and passive devices.

[0037] The active element means an element that actively utilizes the nonlinear portion of the signal characteristics. And the passive element means an element that does not utilize the nonlinear signal characteristics even if both linear and nonlinear signal characteristics exist. For example, the active element may include a transistor, an IC semiconductor element, etc., and the passive element may include a capacitor, a resistor, an inductor, etc. The passive element may increase the signal processing speed of the semiconductor chip that is the active element, or perform a filtering function, etc. In addition, the chip may be a wireless communication chip that can be used for Wi-Fi or 5G communication.

[0038] Meanwhile, the product group to which the semiconductor package of the embodiment is applied may be any one of CSP (Chip Scale Package), FC-CSP (Flip Chip-Chip Scale Package), FC-BGA (Flip Chip Ball Grid Array), POP (Package On Package), and SIP (System In Package), but is not limited thereto.

[0039] In this case, the electronic device may be a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a network system, a computer, a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automotive, etc. However, it is not limited thereto, and in addition to these, it may be any other electronic device that processes data.

[0040] FIG. 1 is a diagram showing a semiconductor package of a first embodiment, FIG. 2 is a diagram showing a semiconductor package of a second embodiment, FIG. 3a is a diagram showing a first pattern layer of the second circuit pattern of the second substrate of FIG. 1 or FIG. 2, FIG. 3b is a diagram showing the second pattern layer of the second circuit pattern of the second substrate of FIG. 1 or FIG. 2, and FIG. 3c is a diagram showing the third pattern layer of the second circuit pattern of the second substrate of FIG. 1 or FIG. 2.

[0041] 1 to 3c, a semiconductor package of the embodiment includes a first substrate 100 and a second substrate 200. The first substrate 100 includes a plurality of pads. The semiconductor package of the embodiment may include an element disposed on at least one of the plurality of pads of the first substrate 100. For example, the semiconductor package of the embodiment may include a first element 300 and a second element 400 mounted on the first substrate 100.

[0042] The first substrate 100 may have a multi-layer structure.

[0043] The first substrate 100 may have a six-layer structure based on the number of insulating layers, but the embodiment is not limited thereto.

[0044] For example, the first substrate 100 may have a layer structure of 5 or less insulating layers. Alternatively, the first substrate 100 may have a layer structure of 7 or more insulating layers. For ease of explanation, the following description will be given assuming that the first substrate 100 has a 6-layer structure based on the number of insulating layers.

[0045] The first substrate 100 includes a first insulating layer 110. The first insulating layer 110 may have a six-layer structure.

[0046] For example, the first insulating layer 110 may include, from the bottom, a 1-1 insulating layer 111, a 1-2 insulating layer 112, a 1-3 insulating layer 113, a 1-4 insulating layer 114, a 1-5 insulating layer 115, and a 1-6 insulating layer 116. The 1-2 insulating layer 112, the 1-3 insulating layer 113, the 1-4 insulating layer 114, and the 1-5 insulating layer 115 may be inner insulating layers arranged in inner layers in the stacked structure of the first substrate 100. The 1-1 insulating layer 111 may be a first outer insulating layer arranged in the lowermost position in the stacked structure of the first substrate 100. The 1-6 insulating layer 116 may be a second outer insulating layer arranged in the uppermost position in the stacked structure of the first substrate 100.

[0047] The first insulating layer 110 is a substrate on which an electric circuit capable of changing wiring is formed, and may include any of a printed circuit board, a wiring board, and an insulating substrate made of an insulating material on which a circuit pattern can be formed.

[0048] The first insulating layer 110 may be rigid or flexible. For example, the first insulating layer 110 may include glass or plastic. In particular, the first insulating layer 110 may include chemically strengthened / semi-strengthened glass, such as soda lime glass or aluminosilicate glass. Alternatively, the first insulating layer 110 may include reinforced or ductile plastic, such as polyimide (PI), polyethylene terephthalate (PET), propylene glycol (PPG), polycarbonate (PC), or the like. Alternatively, the first insulating layer 110 may include sapphire.

[0049] Also, the first insulating layer 110 may include an optical isotropic film. For example, the first insulating layer 110 may include a cyclic olefin copolymer (COC), a cyclic olefin polymer (COP), an optical isotropic polycarbonate (PC), or an optical isotropic polymethyl methacrylate (PMMA).

[0050] The first insulating layer 110 may be formed of a material including an inorganic filler and an insulating resin. For example, the first insulating layer 110 may include a structure in which an inorganic filler such as silica or alumina is dispersed in a thermosetting resin such as an epoxy resin or a thermoplastic resin such as a polyimide. For example, the first insulating layer 110 may include Ajinomoto Build-up Film (ABF), FR-4, Bismaleimide Triazine (BT), Photo Imagable Dielectric resin (PID), BT, etc.

[0051] In addition, the first insulating layer 110 may be bent while partially having a curved surface. That is, the first insulating layer 110 may be bent while partially having a flat surface and partially having a curved surface. More specifically, the first insulating layer 110 may be bent while an end portion has a curved surface, or may be bent or folded while having a surface including a random curvature.

[0052] Also, the first insulating layer 110 may be a flexible substrate having a flexible characteristic. Also, the first insulating layer 110 may be a curved or bent substrate. In this case, the first insulating layer 110 may express electrical wiring for connecting circuit components based on a circuit design as a wiring diagram, and reproduce an electrical conductor on an insulator. Also, the first insulating layer 110 may mount elements and form wiring for connecting the elements in a circuit manner. Also, the first insulating layer 110 may mechanically fix elements other than the electrical connection function of the elements.

[0053] Each of the first insulating layers 110 may have a thickness in the range of 10 μm to 60 μm. Preferably, each of the first insulating layers 110 may have a thickness in the range of 12 μm to 50 μm. More preferably, each of the first insulating layers 110 may have a thickness in the range of 15 μm to 40 μm.

[0054] If the thickness of at least one of the layers of the first insulating layer 110 is less than 10 μm, the circuit pattern on the first substrate 100 may not be stably protected. If the thickness of at least one of the layers of the first insulating layer 110 exceeds 60 μm, the thickness of the first substrate 100 and the thickness of the semiconductor package including the first substrate 100 may increase. If the thickness of at least one of the layers of the first insulating layer 110 exceeds 60 μm, the thickness of the circuit pattern and the through electrode may increase accordingly. If the thickness of the circuit pattern and the through electrode increase, the signal transmission loss may increase.

[0055] Meanwhile, the first substrate 100 may be, but is not limited to, a coreless substrate. For example, the first substrate 100 may be a core substrate. When the first substrate 100 is a core substrate, at least one of the inner insulating layers of the first insulating layer 110 may be a core layer. The core layer may have a thickness greater than the other layers of the first insulating layer 110.

[0056] The first substrate 100 includes a first circuit pattern 120 disposed on a first insulating layer 110. The first circuit pattern 120 may be disposed on the surface of each layer of the first insulating layer 110.

[0057] The first circuit pattern 120 is a wiring that transmits an electric signal and may be formed of a metal material having high electrical conductivity. To this end, the first circuit pattern 120 may be formed of at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn). Also, the first circuit pattern 120 may be formed of a paste or solder paste including at least one metal material selected from gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper (Cu), and zinc (Zn) that has excellent bonding strength. Preferably, the first circuit pattern 120 may be formed of copper (Cu), which has high electrical conductivity and is relatively inexpensive.

[0058] The first circuit pattern 120 can be formed by a typical circuit board manufacturing process such as an additive process, a subtractive process, a modified semi-additive process (MSAP), or a semi-additive process (SAP), and a detailed description thereof will be omitted here.

[0059] The first circuit pattern 120 includes traces and pads. The traces refer to long line-shaped wiring that transmits electrical signals. The pads may be mounting pads on which components such as chips are mounted, terminal pads, core pads, or BGA pads for connection to an external board, or via pads connected to vias.

[0060] Preferably, the first circuit pattern 120 may include a plurality of pads. Here, the plurality of pads may refer to a portion of the first circuit pattern disposed on the uppermost side of the first circuit pattern 120.

[0061] The first circuit pattern 120 includes a pad disposed on an upper surface of the first insulating layer 110. For example, the first circuit pattern 120 includes a pad disposed on an upper surface of the 1st to 6th insulating layers 116, which are disposed on the uppermost side of the first insulating layer 110.

[0062] The first circuit pattern 120 includes a first pad 123. The first pad 123 may function as a bonding pad for bonding the second substrate 200 onto the first substrate 100.

[0063] A plurality of the first pads 123 may be formed on the upper surface of the first insulating layer 110. The first pads 123 may be electrically connected to pads (not shown) of the second substrate 200, respectively.

[0064] The first circuit pattern 120 may include a second pad 121 disposed on an upper surface of the first insulating layer 110. The second pad 121 may function as a first mounting pad for mounting the first element 340 on the first substrate 100. A plurality of the second pads 121 may be included. The number of the second pads 121 may correspond to the number of the first terminals 345 of the first element 340. As an example, the first element 340 may include two first terminals 345. Thus, the number of the second pads 121 may be two.

[0065] The first circuit pattern 120 may include a third pad 122 disposed on the upper surface of the first insulating layer 110. The third pad 122 may function as a second mounting pad for mounting the second element 350 on the first substrate 100. A plurality of the third pads 122 may be included. The number of the third pads 122 may correspond to the number of the second terminals 355 of the second element 350.

[0066] The first element 340 and the second element 355 may be active elements, or may be passive elements. As an example, at least one of the first element 340 and the second element 355 may include an integrated passive element IPD (Integrated Passive Device). For example, the integrated passive element may include a capacitor. For example, at least one of the first element 340 and the second element 355 may be a multi-layer ceramic capacitor MLCC (Multi Layer Ceramic Condenser, Multi Layer Ceramic Capacitor). The multi-layer ceramic capacitor may have a two-terminal structure, or may have a three-terminal structure. However, the embodiment is not limited thereto. For example, at least one of the first element 340 and the second element 355 may include an inductor. Specifically, in the embodiment, at least one of the capacitor and the inductor is configured as an element in the shape of a die. And, in the embodiment, at least the other of the capacitor and the inductor is configured as a substrate.

[0067] For example, the second substrate 200 may be an inductor substrate including a coil pattern that performs an inductor function. In this case, at least one of the first element 340 and the second element 355 may include a capacitor.

[0068] Also, the second substrate 200 may be a capacitor substrate including a pattern that performs a capacitor function, in which case at least one of the first element 340 and the second element 355 may include an inductor.

[0069] The semiconductor package of the embodiment includes a first substrate and a second substrate, and the semiconductor package includes at least one element mounted on the first substrate, and the second substrate is mounted on the first substrate and can function as an inductor or a capacitor.

[0070] Specifically, in the embodiment, one of the inductor and the capacitor is configured as an element having a die shape, and the other is configured as an element having a substrate shape. As a result, the embodiment can secure design space for the semiconductor package, thereby securing design freedom. Furthermore, the embodiment can realize the inductor and the capacitor as different types from each other, thereby solving a reliability problem that may occur between them. For example, when the inductor and the capacitor are arranged adjacent to each other, a problem may occur in that the characteristics of each function are deteriorated due to interference between them. As a result, the embodiment can realize the inductor and the capacitor as different types from each other, thereby solving the problem of deterioration of the characteristics of each function. Furthermore, the embodiment can maximize the characteristics of the inductor function and the capacitor function, thereby further improving the reliability of the product.

[0071] Also, the embodiment includes a plurality of inductors or a plurality of capacitors. Any one of the plurality of inductors is configured as a die-shaped element, and another inductor is configured as a substrate. Also, in the embodiment, another capacitor of the plurality of capacitors is configured as a die-shaped element, and another capacitor is configured as a substrate.

[0072] Through this, the embodiment can further maximize the inductor function or capacitor function, thereby further improving product performance.

[0073] Meanwhile, the first circuit pattern 120 may have a thickness of 10 μm to 25 μm. Preferably, the first circuit pattern 120 may have a thickness of 12 μm to 23 μm. More preferably, the first circuit pattern 120 may have a thickness of 15 μm to 20 μm. If the thickness of the first circuit pattern 120 exceeds 25 μm, it may be difficult to miniaturize the line width or space of the first circuit pattern 120. If the thickness of the first circuit pattern 120 is less than 10 μm, it may be difficult to realize a normal circuit.

[0074] The first substrate 100 may include a first through electrode 130. The first through electrode 130 may penetrate the first insulating layer 110. For example, the first through electrode 130 may penetrate at least one of a plurality of insulating layers constituting the first insulating layer 110. The first through electrode 130 may individually penetrate each insulating layer constituting the first insulating layer 110. Alternatively, the first through electrode 130 may commonly penetrate at least two insulating layers constituting the first insulating layer 110.

[0075] The first through electrode 130 may be formed by forming a first through hole penetrating the first insulating layer 110 and then filling the formed first through hole with a conductive material. The first through hole may be formed by any one of mechanical, laser, and chemical processing. The first through hole may be formed by a mechanical processing method such as milling, drilling, and routing. In addition, the first through hole may be formed by filling the first through hole with a conductive material such as UV or CO. 2 A laser method can be used, and a chemical processing method using a chemical containing aminosilane, ketones, etc. can be used to form the first through hole.

[0076] When the first through hole is formed, the inside of the first through hole may be filled with a conductive material to form the first through electrode 130. The first through electrode 130 may be formed of any one metal material selected from copper (Cu), silver (Ag), tin (Sn), gold (Au), nickel (Ni), and palladium (Pd). In addition, the conductive material may be filled by any one or a combination of electroless plating, electrolytic plating, screen printing, sputtering, evaporation, inkjetting, and desfencing.

[0077] The first substrate 100 may include a first protective layer. For example, the first substrate 100 may include a first-1 protective layer 141 disposed on a lower surface of the first insulating layer 110. The first substrate 100 may also include a first-2 protective layer 142 disposed on an upper surface of the first insulating layer 110.

[0078] The first protective layer may be disposed to cover a surface of the first insulating layer 110 and a surface of the first circuit patterns 120. The first protective layer may include an opening overlapping at least one of the first circuit patterns 120 in a thickness direction.

[0079] For example, the first protective layer may include a first opening overlapping a first pad 123 of the first circuit pattern 120 in a thickness direction. The first protective layer may also include a second opening overlapping a second pad 121 of the first circuit pattern 120 in a thickness direction. The first protective layer may also include a third opening overlapping a third pad 122 of the first circuit pattern 120 in a thickness direction.

[0080] The first protective layer may include an insulating material. The first protective layer may include various materials that can be applied and then heated and cured to protect the surface of the first insulating layer 110 and the surface of the first circuit pattern 120. The first protective layer may be a resist layer. For example, the first protective layer 150 and the second protective layer 160 may be a solder resist layer including an organic polymer material. As an example, the first protective layer may include an epoxy acrylate resin. In detail, the first protective layer may include a resin, a hardener, a photoinitiator, a pigment, a solvent, a filler, an additive, an acrylic monomer, and the like. However, the embodiment is not limited thereto, and it goes without saying that the first protective layer may be any one of a photo solder resist layer, a cover-lay, and a polymer material.

[0081] The first protective layer may have a thickness of 1 μm to 20 μm. The first protective layer may have a thickness of 1 μm to 15 μm. For example, the first protective layer may have a thickness of 5 μm to 20 μm. If the thickness of the first protective layer exceeds 20 μm, the overall thickness of the semiconductor package may increase. Also, if the thickness of the first protective layer is less than 1 μm, the first circuit pattern 120 of the outermost layer included in the semiconductor package may not be stably protected.

[0082] An embodiment may include a second substrate 200 disposed on the first substrate 100, a first element 340, and a second element 355.

[0083] Here, the first element 340 and the second element 355 have already been described above, and therefore detailed description thereof will be omitted. Specifically, the first element 340 and the second element 355 may include one of an inductor and a capacitor, and the second substrate 200 may include the other of an inductor and a capacitor. However, the embodiment is not limited thereto.

[0084] For example, the semiconductor package of the embodiment may include multiple inductors, at least one of which may be implemented on the first substrate 100 in the form of a die, and the other may be implemented on the second substrate 200.

[0085] In addition, the semiconductor package of the embodiment may include a plurality of capacitors, at least one of which may be implemented on the first substrate 100 in the form of a die, and the other may be implemented on the second substrate 200.

[0086] The second substrate 200 will be described in detail below. The second substrate 200 may be a substrate that functions as a capacitor, or may be a substrate that functions as an inductor. For convenience of explanation, the second substrate 200 will be described below as a substrate that functions as an inductor. However, the embodiment is not limited thereto.

[0087] Referring to FIG. 1, the second substrate 200 may have a structure including a second insulating layer 210 , a second circuit pattern 220 , a second through electrode 230 , and a second protective layer 240 .

[0088] The second insulating layer 210 may be composed of at least one layer. Preferably, the second insulating layer 210 may have a layer structure of two or more layers. Thus, the embodiment allows the second substrate 200 to realize various inductances.

[0089] The second insulating layer 210 may include the same insulating material as the first insulating layer 110. Alternatively, the second insulating layer 210 may include a different insulating material than the first insulating layer 110.

[0090] The second substrate 200 includes a second circuit pattern 220. The second circuit pattern 220 may be disposed on a surface of the second insulating layer 210. The second circuit pattern 220 may be a pattern having a coil shape.

[0091] The second substrate 200 includes a second through electrode 230. The second through electrode 230 penetrates the second insulating layer 210.

[0092] 1 includes a second protective layer 240. The second protective layer 240 may be disposed on an upper surface and a lower surface of the second insulating layer 210, respectively.

[0093] 2. In contrast, the second substrate 200a of the second embodiment of FIG. 2 may have a structure in which the second protective layer 240 is omitted.

[0094] The basic features of the second substrate 200 have already been described with reference to the first substrate 100, and therefore a detailed description thereof will be omitted.

[0095] The semiconductor package also includes a molding layer 360 .

[0096] The molding layer 360 may be disposed on the first substrate 100 .

[0097] 1 may mold the first element 340 and the second element 350 disposed on the first substrate 100. In this case, the molding layer 360 of the first embodiment may not cover the second substrate 200. That is, the second substrate 200 includes a second protective layer 240, and therefore the molding layer 360 may mold only the first element 340 and the second element 350.

[0098] However, the embodiment is not limited thereto. For example, the molding layer 360 may mold the second substrate 200 together with the first element 340 and the second element 350.

[0099] 2 may mold the second substrate 200. In this case, the second protective layer 240 may be omitted from the second substrate 200. Thus, the molding layer 360 may mold the second circuit pattern 220 and the second insulating layer 210 of the second substrate 200.

[0100] The molding layer 360 may be, but is not limited to, EMC (Epoxy Mold Compound).

[0101] The molding layer 360 may have a low dielectric constant to improve heat dissipation characteristics. For example, the dielectric constant (Dk) of the molding layer 360 may be 0.2 to 10. For example, the dielectric constant (Dk) of the molding layer 360 may be 0.5 to 8. For example, the dielectric constant (Dk) of the molding layer 360 may be 0.8 to 5. Thus, in an embodiment, the molding layer 360 has a low dielectric constant to improve the heat dissipation characteristics of the first element 340 and the second element 350.

[0102] The semiconductor package also includes a plurality of connecting parts, for example, a first connecting part 330 disposed on the first pad 123 of the first circuit pattern 120.

[0103] The semiconductor package may also include a second connection portion 310 disposed on the second pad 121 of the first circuit pattern 120 .

[0104] The semiconductor package may also include a third connection portion 320 disposed on the third pad 122 of the first circuit pattern 120 .

[0105] The first to third connection parts 310, 320, 330 may include a spherical shape. For example, the cross sections of the first to third connection parts 310, 320, 330 may include a circular or semicircular shape. For example, the cross sections of the first to third connection parts 310, 320, 330 may include a partially or entirely rounded shape. The cross sections of the first to third connection parts 310, 320, 330 may have a flat surface on one side and a curved surface on the other side. The first to third connection parts 310, 320, 330 may be solder balls, but are not limited thereto.

[0106] Alternatively, the first to third connection parts 310, 320, and 330 may have a hexahedral shape. For example, the cross sections of the first to third connection parts 310, 320, and 330 may include a quadrangular shape. The cross sections of the first to third connection parts 310, 320, and 330 may include a rectangular shape or a square shape.

[0107] Meanwhile, referring to FIGS. 3a to 3c, the second circuit pattern 220 may refer to coil pattern layers disposed on the surfaces of a plurality of insulating layers, respectively.

[0108] FIG. 3a(a) is a plan view showing a first embodiment of the first pattern layer 221, and FIG. 3a(b) is a plan view showing a second embodiment of the first pattern layer 221. As shown in FIG.

[0109] The first pattern layer 221 of the first embodiment may include a plurality of square patterns spaced apart from each other as shown in FIG. 3(a).

[0110] Differently, the first pattern layer 221 of the second embodiment may have a coil shape.

[0111] Meanwhile, the first pattern layer 221 may be connected to a second pattern layer 222 below via a second through electrode 230. The first pattern layer 221 may include a pad 221P. A chip 400 may be mounted on the pad 221P of the first pattern layer 221. The chip 400 may be, but is not limited to, a multilayer ceramic capacitor (MLCC).

[0112] Meanwhile, (a) of FIG. 3b shows the second pattern layer 222 of the first embodiment connected to the first pattern layer 221 of the first embodiment, and (b) of FIG. 3b shows the second pattern layer 222 of the second embodiment connected to the first pattern layer 221 of the second embodiment.

[0113] The second pattern layer 222 is disposed on a lower surface of the 2-1 insulating layer 211 or an upper surface of the 2-2 insulating layer 212. The second pattern layer 222 has a coil shape. For example, the second pattern layer 222 may include a pattern folded multiple times in one direction on the lower surface of the 2-1 insulating layer 211 or the upper surface of the 2-2 insulating layer 212. The second pattern layer 222 may be connected to the first pattern layer 221 and the third pattern layer 223 via the through electrodes 230.

[0114] Meanwhile, (a) of Figure 3c shows the third pattern layer 223 of the first embodiment connected to the first pattern layer 221 and the second pattern layer 222 of the first embodiment, and (b) of Figure 3c shows the third pattern layer 223 of the second embodiment connected to the first pattern layer 221 and the second pattern layer 222 of the second embodiment.

[0115] The third pattern layer 223 is disposed on the lower surface of the 2-2 insulating layer 212. The third pattern layer 223 may include a pad portion connected to the first connection portion 330. The third pattern layer 223 has a coil shape. For example, the third pattern layer may include a pattern folded multiple times in one direction on the lower surface of the 2-2 insulating layer 212. The third pattern layer 223 may be connected to the first pattern layer 221 and the second pattern layer 222 through the through electrode 230.

[0116] The second substrate 200 will be described in detail below.

[0117] FIG. 4 is a diagram showing a specific layer structure of the second substrate in the first embodiment, FIG. 5 is a diagram showing a specific layer structure of the second substrate in the second embodiment, FIG. 6 is a diagram showing a specific layer structure of the second substrate in the third embodiment, and FIG. 7 is a diagram showing a specific layer structure of the second substrate in the fourth embodiment.

[0118] Referring to FIG. 4, the second insulating layer 210 of the second substrate 200 includes a 2-1 insulating layer 211 and a 2-2 insulating layer 212 .

[0119] The second circuit pattern 220 of the second substrate 200 includes a first pattern layer 221 disposed on the upper surface of the 2-1 insulating layer 211. The second circuit pattern 220 also includes a second pattern layer 222 disposed between the lower surface of the 2-1 insulating layer 211 and the upper surface of the 2-2 insulating layer 212. The second circuit pattern 220 also includes a third pattern layer 223 disposed on the lower surface of the 2-2 insulating layer 212.

[0120] The first pattern layer 221, the second pattern layer 222, and the third pattern layer 223 may each be a coil pattern that forms a specific inductance.

[0121] The first pattern layer 221, the second pattern layer 222, and the third pattern layer 223 are disposed on a second insulating layer 210 and are connected to each other via second through electrodes 230 to form a specific inductance.

[0122] The inductance formed by the first pattern layer 221, the second pattern layer 222, and the third pattern layer 223 can be determined by the dielectric constant (Dk) of the second insulating layer 210, the distance (δ) between the circuit patterns arranged on different layers, and the cross-sectional area and length of each pattern layer.

[0123] The first pattern layer 221, the second pattern layer 222, and the third pattern layer 223 may have the same thicknesses t1, t2, and t3 as each other. And the distance δ1 between the first pattern layer 221 and the second pattern layer 222 and the distance δ2 between the second pattern layer 222 and the third pattern layer 223 may also be the same.

[0124] As a result, the second substrate shown in FIG. 4 can be an inductor substrate that performs the function of an inductor having a single inductance.

[0125] 5, the second substrate of the second embodiment includes a 2-1 insulating layer 211a and a 2-2 insulating layer 212a. The second substrate of the second embodiment also includes a first pattern layer 221a disposed on the upper surface of the 2-1 insulating layer 211a. The second substrate of the second embodiment also includes a second pattern layer 222a disposed between the lower surface of the 2-1 insulating layer 211a and the upper surface of the 2-2 insulating layer 212a. The second substrate of the second embodiment also includes a third pattern layer 223a disposed on the lower surface of the 2-2 insulating layer 212a.

[0126] At this time, the first pattern layer 221 and the third pattern layer 223 in the first embodiment had a structure protruding from the upper surface of the 2-1 insulating layer 211 and the lower surface of the 2-2 insulating layer 212, respectively.

[0127] Alternatively, the first pattern layer 221a and the third pattern layer 223a of the second embodiment may have a structure embedded in the upper surface of the 2-1 insulating layer 211a and the lower surface of the 2-2 insulating layer 212a.

[0128] For this purpose, the 2-1 insulating layer 211a and the 2-2 insulating layer 212a of the second embodiment may include a photocurable resin or a photosensitive resin. For example, the 2-1 insulating layer 211a and the 2-2 insulating layer 212a may be formed of a PID (Photoimageable Dielectrics) material.

[0129] For this purpose, the 2-1 insulating layer 211a and the 2-2 insulating layer 212a may include epoxy resin, photoinitiator, silicon-based filler, and hardener. For example, the 2-1 insulating layer 211a and the 2-2 insulating layer 212a may be formed by laminating a photocurable resin film or applying a photocurable resin paste or liquid phase. In this case, for example, the photocurable resin material may include at least one selected from photocurable polyhydroxystyrene (PHS), photocurable polybenzoxazole (PBO), photocurable polyimide (PI), photocurable benzocyclobutene (BCB), photocurable polysiloxane, photocurable epoxy, and novolac resin.

[0130] Through this, in the embodiment, pattern grooves (not shown) are formed on the upper and lower surfaces of the 2-1 insulating layer 211a and the 2-2 insulating layer 212a, respectively, and the first pattern layer 221 and the third pattern layer 223 are embedded in the formed pattern grooves.

[0131] Referring to FIG. 6, the second substrate of the third embodiment can be an inductor substrate having multiple inductances.

[0132] The second substrate of the third embodiment includes a 2-1 insulating layer 211b and a 2-2 insulating layer 212b. The second substrate of the third embodiment also includes a first pattern layer 221b arranged on the upper surface of the 2-1 insulating layer 211b. The second substrate of the third embodiment also includes a second pattern layer 222b arranged between the lower surface of the 2-1 insulating layer 211b and the upper surface of the 2-2 insulating layer 212b. The second substrate of the third embodiment also includes a third pattern layer 223b arranged on the lower surface of the 2-2 insulating layer 212b.

[0133] In this case, the first pattern layer 221b may include a plurality of coil patterns.

[0134] The first pattern layer 221b includes a first coil pattern 221b1 and a second coil pattern 221b2.

[0135] The first coil pattern 221b1 and the second coil pattern 221b2 may have different arrangement structures.

[0136] For example, the first coil pattern 221b1 may have a structure embedded in the upper surface of the 2-1 insulating layer 211b, and the second coil pattern 221b2 may have a structure protruding above the upper surface of the 2-1 insulating layer 211b.

[0137] Therefore, in the second substrate of the third embodiment, the first separation distance δ1 between the first coil pattern 221b1 and the second pattern layer 222b may be different from the second separation distance δ2 between the second coil pattern 221b2 and the second pattern layer 222b.

[0138] The second separation distance δ2 may be greater than the first separation distance δ1. For example, the second separation distance δ2 may be greater than the first separation distance δ1 by the thickness of the first coil pattern 221b1.

[0139] As a result, in the second substrate of the third embodiment, the first coil pattern 221b1 and the second pattern layer 222b can form a first inductance, and the second coil pattern 221b2 and the second pattern layer 222b can form a second inductance different from the first inductance.

[0140] Referring to FIG. 7, the second substrate of the fourth embodiment may be an inductor substrate having multiple inductances.

[0141] The second substrate of the fourth embodiment includes a 2-1 insulating layer 211c and a 2-2 insulating layer 212c. The second substrate of the fourth embodiment also includes a first pattern layer 221c arranged on the upper surface of the 2-1 insulating layer 211c. The second substrate of the fourth embodiment also includes a second pattern layer 222c arranged between the lower surface of the 2-1 insulating layer 211c and the upper surface of the 2-2 insulating layer 212c. The second substrate of the fourth embodiment also includes a third pattern layer 223c arranged on the lower surface of the 2-2 insulating layer 212c.

[0142] In this case, the first pattern layer 221c may include a plurality of coil patterns.

[0143] The first pattern layer 221c may include a first coil pattern 221c1, a second coil pattern 221c2, a third coil pattern 221c3, and a fourth coil pattern 221c4.

[0144] In the fourth embodiment, the first coil pattern 221c1, the second coil pattern 221c2, the third coil pattern 221c3, and the fourth coil pattern 221c4 are configured to form inductances different from one another.

[0145] A first separation distance δ1 may be provided between the first coil pattern 221c1 and the second pattern layer 222c. A second separation distance δ2 may be provided between the second coil pattern 221c2 and the second pattern layer 222c. A third separation distance δ3 may be provided between the third coil pattern 221c3 and the second pattern layer 222c. A fourth separation distance δ4 may be provided between the fourth coil pattern 221c4 and the second pattern layer 222c.

[0146] The first coil pattern 221c1, the second coil pattern 221c2, and the third coil pattern 221c3 may have a structure embedded in the upper surface of the 2-1 insulating layer 211c, and the fourth coil pattern 221c4 may have a structure protruding above the upper surface of the 2-1 insulating layer 211c.

[0147] In this case, a plurality of grooves having different depths may be formed on the upper surface of the 2-1 insulating layer 211c, and the first coil pattern 221c1, the second coil pattern 221c2, and the third coil pattern 221c3 may be disposed in the respective grooves having different depths.

[0148] Thereby, in the embodiment, the first to fourth separation distances δ1, δ2, δ3, and δ4 can be realized to be different from one another.

[0149] The semiconductor package of the embodiment includes a first substrate and a second substrate, and the semiconductor package includes at least one element mounted on the first substrate, and the second substrate is mounted on the first substrate and can function as an inductor or a capacitor.

[0150] Specifically, in the embodiment, one of the inductor and the capacitor is configured as an element having a die shape, and the other is configured as an element having a substrate shape. As a result, the embodiment can secure design space for the semiconductor package, thereby ensuring design freedom. Furthermore, the embodiment can realize the inductor and the capacitor as different types from each other, thereby solving a reliability problem that may occur between them. For example, when the inductor and the capacitor are arranged adjacent to each other, a problem may occur in that the characteristics of each function are deteriorated due to interference between them. Thus, the embodiment can realize the inductor and the capacitor as different types from each other, thereby solving the problem of deterioration of the characteristics of each function. Furthermore, the embodiment can maximize the characteristics of the inductor function and the capacitor function, thereby further improving the reliability of the product.

[0151] Also, the embodiment includes a plurality of inductors or a plurality of capacitors. Any one of the plurality of inductors is configured as a die-shaped element, and another inductor is configured as a substrate. Also, in the embodiment, another capacitor of the plurality of capacitors is configured as a die-shaped element, and another capacitor is configured as a substrate.

[0152] Through this, the embodiment can further maximize the inductor function or capacitor function, thereby further improving product performance.

[0153] Also, the second substrate of the embodiment includes a second insulating layer including a photosensitive material. And, the pattern layer of the second substrate is inserted into the groove of the second insulating layer or has a protruding structure. Also, the groove of the second insulating layer may include a plurality of grooves having different depths, and the pattern layer may be disposed in each of the plurality of grooves. Through this, the embodiment can realize a plurality of inductances with one second substrate. Through this, the embodiment can further improve product performance.

[0154] The features, structures, effects, etc. described in the above embodiments are included in at least one embodiment and are not necessarily limited to only one embodiment. Furthermore, the features, structures, effects, etc. exemplified in each embodiment can be combined or modified in other embodiments by a person having ordinary skill in the art to which the embodiment belongs. Therefore, the contents related to such combinations and modifications should be interpreted as being included in the scope of the embodiment.

[0155] The above description focuses on the embodiments, but these are merely illustrative and do not limit the embodiments. Those skilled in the art will understand that various modifications and applications not exemplified above are possible within the scope of the essential characteristics of the embodiments. For example, each component specifically illustrated in the embodiments can be modified and implemented. Differences related to such modifications and applications should be interpreted as being included in the scope of the embodiments defined in the appended claims.

Claims

1. a first substrate including first and second pads; a first connection portion disposed on the first pad of the first substrate; a second substrate coupled to the first connection portion; a second connection portion disposed on the second pad of the first substrate; An element mounted on the second connection portion; a molding layer disposed on the first substrate and molding the device; the element includes one of a capacitor and an inductor; the second substrate includes a patterned layer that serves a different function than the element; Semiconductor package.

2. The second substrate is A second insulating layer; a second circuit pattern disposed on the second insulating layer and corresponding to the pattern layer; The semiconductor package according to claim 1 , further comprising: a second through electrode penetrating the second insulating layer.

3. The second substrate is further comprising a second protective layer disposed on an upper surface and a lower surface of the second insulating layer; The semiconductor package of claim 2 , wherein the molding layer molds the device at a location spaced apart from the second substrate.

4. The semiconductor package of claim 1 , wherein the molding layer molds the second insulating layer and the second circuit pattern of the second substrate.

5. the second substrate is an inductor substrate including a coil pattern forming an inductance; The element comprises: A first element corresponding to a capacitor; 2. The semiconductor package of claim 1, further comprising: a second element spaced apart from the first element and corresponding to an inductor.

6. the second substrate is a capacitor substrate including a capacitor pattern for forming a capacitance; The element comprises: A first element corresponding to a capacitor; 2. The semiconductor package of claim 1, further comprising: a second element spaced apart from the first element and corresponding to an inductor.

7. The second circuit pattern is a first pattern layer disposed on an upper surface of the second insulating layer; a second pattern layer disposed on a lower surface of the second insulating layer; the first pattern layer includes a plurality of coil patterns; The plurality of coil patterns include a first coil pattern having a first separation distance from the second pattern layer; The semiconductor package of claim 2 , further comprising: a second coil pattern having a second separation distance different from the second pattern layer and the first separation distance.

8. The first coil pattern is disposed in a pattern groove formed on the upper surface of the second insulating layer; The second coil pattern is The semiconductor package of claim 7 , protruding above a top surface of the second insulating layer.

9. The first coil pattern is a first trench having a first depth formed in an upper surface of the second insulating layer; The second coil pattern is 8. The semiconductor package of claim 7, wherein the semiconductor package is disposed in a second groove formed in an upper surface of the second insulating layer and having a second depth different from the first depth.

10. 10. The semiconductor package according to claim 7, wherein the second insulating layer includes a photo imageable dielectric resin (PID).

Images