Semiconductor memory device and method for manufacturing the same

Abstract

The present invention provides a semiconductor memory device and a method for manufacturing the same that can improve data retention characteristics and achieve high write saturation and low erase saturation. [Solution] The semiconductor memory device according to this embodiment comprises a laminate in which a plurality of electrode films and a plurality of first insulating films are alternately stacked in a first direction. The columnar body is provided penetrating the laminate in the first direction. The aluminum oxide film is provided between the columnar body and the electrode films. The first tetravalent metal oxide is present at the interface between the columnar body and the aluminum oxide film.

Description

Technical Field

[0001] This embodiment relates to a semiconductor memory device and a method for manufacturing the same.

Background Art

[0002] A semiconductor memory device such as a NAND-type flash memory may have a three-dimensional memory cell array in which a plurality of memory cells are three-dimensionally arranged. In such a three-dimensional memory cell array, a block film is provided between the word line and the charge storage layer in order to suppress charge back tunneling from the word line to the charge storage layer. In such a semiconductor memory device, it is desired to improve the data retention characteristics in the charge storage layer and to increase the write saturation and decrease the erase saturation.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] To provide a semiconductor memory device and a method for manufacturing the same that can improve data retention characteristics and increase write saturation and decrease erase saturation.

Means for Solving the Problems

[0005] The semiconductor memory device according to this embodiment includes a stack in which a plurality of electrode films and a plurality of first insulating films are alternately stacked in a first direction. The columnar body is provided penetrating the stack in the first direction. The aluminum oxide film is provided between the columnar body and the electrode film. The first tetravalent metal oxide exists at the interface between the columnar body and the aluminum oxide film.

Brief Description of the Drawings

[0006] [Figure 1] A cross-sectional view showing an example configuration of a semiconductor memory device according to this embodiment. [Figure 2] A plan view showing the laminated structure. [Figure 3] A cross-sectional view illustrating a three-dimensional memory cell structure. [Figure 4] A cross-sectional view illustrating a three-dimensional memory cell structure. [Figure 5] A cross-sectional view that provides a more detailed explanation of the memory cell portion shown in Figure 3. [Figure 6] A cross-sectional view showing an example configuration between the charge trap film and the electrode film. [Figure 7] A cross-sectional view showing an example configuration between the charge trap film and the electrode film. [Figure 8] A cross-sectional view showing an example configuration between the charge trap film and the electrode film. [Figure 9] A cross-sectional view showing an example configuration between the charge trap film and the electrode film. [Figure 10] A cross-sectional view showing an example configuration when the electrode film is made of tungsten. [Figure 11] A graph showing the amount of shift in IRDR (Infrared Data Retention). [Figure 12] A graph showing the write saturation voltage. [Figure 13] This is a cross-sectional view showing an example of a configuration in which metal oxide 221a_3 is added to the configuration in Figure 6. [Figure 14] This is a cross-sectional view showing an example of a configuration in which metal oxide 221a_3 is added to the configuration in Figure 9. [Figure 15] A graph showing the elimination saturation voltage. [Figure 16] A cross-sectional view showing an example of the manufacturing process for a semiconductor memory device according to this embodiment. [Figure 17] A cross-sectional view showing an example of the manufacturing process, following Figure 16. [Figure 18] A cross-sectional view showing an example of the manufacturing process, following Figure 17. [Figure 19] A cross-sectional view showing an example of the manufacturing process, following Figure 18. [Figure 20]A cross-sectional view showing an example of a manufacturing process, following FIG. 19. [Figure 21] A cross-sectional view showing an example of a manufacturing process, following FIG. 20.

Embodiments for Carrying Out the Invention

[0007] Hereinafter, embodiments of the present invention will be described with reference to the drawings. These embodiments do not limit the present invention. The drawings are schematic or conceptual. In the specification and the drawings, the same reference numerals are assigned to the same elements.

[0008] FIG. 1 is a cross-sectional view showing a configuration example of a semiconductor memory device 1 according to this embodiment. Hereinafter, the stacking direction of the stacked body 20 is defined as the Z direction. One direction intersecting, for example, orthogonally to the Z direction is defined as the Y direction. One direction intersecting, for example, orthogonally to each of the Z direction and the Y direction is defined as the X direction. In FIG. 1, the semiconductor memory device 1 is shown with the +Z direction being upward. In the cross-sectional views after FIG. 5, the array chip may be shown with the -Z direction or the Y direction being upward. Note that in this specification, the ±Z directions are examples of the first direction.

[0009] The semiconductor memory device 1 includes an array chip 2 having a memory cell array and a CMOS chip 3 having a CMOS circuit. The array chip 2 and the CMOS chip 3 are bonded at the bonding surface B1 and are electrically connected to each other via the wiring bonded at the bonding surface B1. In FIG. 1, a state where the array chip 2 is provided on the CMOS chip 3 is shown.

[0010] The CMOS chip 3 includes a substrate 30, transistors 31, vias 32, wirings 33 and 34, and an interlayer insulating film 35.

[0011] The substrate 30 is, for example, a semiconductor substrate such as a silicon substrate. The transistor 31 is an N-type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) or a P-type MOSFET provided on the substrate 30. The transistor 31 constitutes, for example, a CMOS (Complementary MOS) circuit that controls the memory cell array 2m of the array chip 2. Multiple transistors 31 constitute logic circuits such as a sense amplifier, a row decoder, and a column decoder. Semiconductor elements other than transistors 31, such as resistors and capacitive elements, may be formed on the substrate 30.

[0012] Via 32 electrically connects transistor 31 to wiring 33, or wiring 33 to wiring 34. Wires 33 and 34 constitute a multilayer wiring structure within the interlayer insulating film 35. Wire 34 is embedded within the interlayer insulating film 35 and is exposed almost flush with the surface of the interlayer insulating film 35. Wires 33 and 34 are electrically connected to transistor 31, etc. Metals such as copper and tungsten are used for vias 32, wiring 33 and 34. The interlayer insulating film 35 covers and protects transistor 31, vias 32, wiring 33 and 34. An insulating film such as a silicon oxide film is used for the interlayer insulating film 35.

[0013] The array chip 2 comprises a laminate 20, a columnar body CL, a source layer BSL, a metal layer 40, a contact plug CCw, a contact plug 29, a bonding pad 50, wiring 23 and 24, a via 28, and an interlayer insulating film 25.

[0014] The laminate 20 is located above the transistor 31 and is positioned in the +Z direction relative to the substrate 30. The laminate 20 is constructed by alternately stacking multiple electrode films 21 and multiple insulating films 22 along the Z direction. The laminate 20, together with the columnar body CL, constitutes a memory cell array. For example, a conductive metal such as tungsten is used for the electrode film 21. For example, a silicon oxide film is used for the insulating film 22. The insulating film 22 insulates the electrode films 21 from each other. That is, multiple electrode films 21 are stacked in an insulated state from each other. The number of stacks of each electrode film 21 and insulating film 22 is arbitrary. The insulating film 22 may be, for example, a porous insulating film or an air gap.

[0015] One or more electrode films 21 at the upper and lower ends of the stacked body 20 in the Z direction function as a source-side selection gate SGS and a drain-side selection gate SGD, respectively. The electrode film 21 between the source-side selection gate SGS and the drain-side selection gate SGD functions as a word line WL. The word line WL is the gate electrode of the memory cell MC. The source-side selection gate SGS is the gate electrode of the source-side selection transistor. The drain-side selection gate SGD is the gate electrode of the drain-side selection transistor. The source-side selection gate SGS is located in the upper region of the stacked body 20. The drain-side selection gate SGD is located in the lower region of the stacked body 20. The upper region refers to the region of the stacked body 20 that is farther from the CMOS chip 3 (closer to the metal layer 40), and the lower region refers to the region of the stacked body 20 that is closer to the CMOS chip 3.

[0016] The semiconductor memory device 1 has multiple memory cells MC connected in series between a source-side selection transistor and a drain-side selection transistor. The structure in which the source-side selection transistor, memory cells MC, and drain-side selection transistor are connected in series is called a “memory string” or “NAND string”. The memory string is connected to a bit line BL via, for example, a via 28. The bit line BL is a wiring 23 located below the stack 20 and extending in the X direction. Therefore, hereafter, the bit line BL will also be referred to as the bit line 23.

[0017] Multiple columnar bodies CL are provided within the laminate 20. The columnar bodies CL extend through the laminate 20 in the stacking direction (Z direction) and are provided from vias 28 connected to bit lines 23 to the source layer BSL. The internal structure of the columnar bodies CL will be described later. In Figure 1, the columnar bodies CL are shown to be formed in two stages in the Z direction. However, the columnar bodies CL may be formed in three or more stages, as shown in Figure 5A.

[0018] Although not shown in Figure 1, multiple slits ST (see Figure 2) are provided within the laminate 20. The slits ST extend in the Y direction and penetrate the laminate 20 in the stacking direction (Z direction). The slits ST are filled with an insulating film such as a silicon oxide film, and the insulating film is configured in a plate shape. The slits ST electrically divide the electrode film 21 of the laminate 20. Alternatively, the inner walls of the slits ST may be coated with an insulating film such as a silicon oxide film, and a conductive material may be embedded inside the insulating film. In this case, the conductive material can also function as source wiring that reaches the source layer BSL.

[0019] A source layer BSL is provided on the laminate 20. The source layer BSL is provided in correspondence with the laminate 20. The laminate 20 (memory cell array 2m) is provided on the side F1 of the source layer BSL, and a metal layer 40 is provided on the opposite side F2. The source layer BSL is commonly connected to one end of multiple columnar bodies CL, and provides a common source voltage to multiple columnar bodies CL in the same memory cell array 2m. In other words, the source layer BSL functions as a common source electrode for the memory cell array 2m. Conductive materials such as doped polysilicon are used for the source layer BSL. A metal material with lower resistance than the source layer BSL is used for the metal layer 40, such as copper, aluminum, or tungsten.

[0020] On the other hand, a bonding pad 50 is provided in the region above the surface F2 of the source layer BSL where the source layer BSL is not provided. The bonding pad 50 is connected to a metal wire or the like (not shown) and receives power or signals from outside the semiconductor memory device 1. The bonding pad 50 is provided to be connected to one end of the contact plug 29 in the Z direction. The bonding pad 50 is connected to the transistor 31 of the CMOS chip 3 via the contact plug 29, wiring 24 and wiring 34. External power supplied from the bonding pad 50 is supplied to the transistor 31. Alternatively, a signal is supplied to the transistor 31 via the bonding pad 50.

[0021] The contact plug CCw is provided in the peripheral part of the laminate 20 and extends in the Z direction within the interlayer insulating film 25. The contact plug CCw is electrically connected between the electrode film 21 (word line WL) and the wiring 24. The contact plug CCw is provided in the stepped portion 2s where the electrode film 21 is formed in a stepped shape at the end of the laminate 20, and is electrically connected to each electrode film 21. The contact plug CCw is provided to transmit the word line voltage from the CMOS chip 3 to each electrode film 21. For example, metals such as copper and tungsten can be used for the contact plug CCw.

[0022] The contact plug 29 is provided on the periphery of the laminate 20 and extends in the Z direction within the interlayer insulating film 25. The contact plug 29 is provided from at least below the laminate 20 to above the laminate 20.

[0023] The contact plug 29 is electrically connected between the bonding pad 50 and the wiring 24. The contact plug 29 is used to supply power or signals from the bonding pad 50 to the array chip 2 or CMOS chip 3. The contact plug 29 is made of a metal such as copper or tungsten. The power supply is, for example, the power supply voltage VDD, or a reference voltage (e.g., ground voltage) VSS that is lower than the power supply voltage VDD. The signal may be an external control signal, or it may be write data or read data.

[0024] In this embodiment, the array chip 2 and the CMOS chip 3 are formed individually and bonded together at the bonding surface B1. Therefore, no transistors 31 are provided within the array chip 2. Furthermore, no stacked structure 20 (memory cell array 2m) is provided within the CMOS chip 3.

[0025] Below the laminate 20, vias 28, wiring 23, and wiring 24 are provided. Wirings 23 and 24 are embedded in the interlayer insulating film 25. Wiring 24 is exposed almost flush with the surface of the interlayer insulating film 25. Wirings 23 and 24 are electrically connected to the semiconductor body of the columnar body CL (210 in Figures 3 and 4), etc. Metals such as copper and tungsten are used for vias 28, wiring 23, and wiring 24. The interlayer insulating film 25 covers and protects the laminate 20, vias 28, wiring 23, and wiring 24. An insulating film such as a silicon oxide film is used for the interlayer insulating film 25.

[0026] The interlayer insulating film 25 and the interlayer insulating film 35 are bonded together at the bonding surface B1, and consequently, the wiring 24 and the wiring 34 are joined almost flush at the bonding surface B1. As a result, the array chip 2 and the CMOS chip 3 are electrically connected via the wiring 24 and the wiring 34.

[0027] Figure 2 is a plan view showing the stacked structure 20. The stacked structure 20 includes a stepped portion 2s and a memory cell array 2m. The stepped portion 2s is provided, for example, at the end of the stacked structure 20. The memory cell array 2m is sandwiched or surrounded by the stepped portion 2s. The slit ST is provided from the stepped portion 2s at one end of the stacked structure 20, through the memory cell array 2m, to the stepped portion 2s at the other end of the stacked structure 20. The slit SHE is provided at least in the memory cell array 2m. The slit SHE is shallower in the Z direction than the slit ST and extends substantially parallel to the slit ST. The slit SHE electrically separates the electrode film 21 on the lower region side of the stacked structure 20 for each drain-side selection gate SGD. For example, an insulating film such as a silicon oxide film is used for the slit SHE. The slit ST may also include source wiring that is electrically isolated from the electrode film 21 of the stacked structure 20 while being electrically connected to the source layer BSL.

[0028] The portion of the stacked material 20 sandwiched between the two slits ST shown in Figure 2 is called a block BLK. The block BLK constitutes, for example, the smallest unit for data erasure. Slit SHE is provided within the block BLK. The stacked material 20 between slit ST and slit SHE is called a finger. The drain-side selection gate SGD is separated for each finger. Therefore, during data writing and reading, the drain-side selection gate SGD can select one finger within the block BLK.

[0029] Figures 3 and 4 are cross-sectional views illustrating a three-dimensional memory cell structure. Multiple columnar bodies CL are each located within memory holes MH provided in the stack 20. Each columnar body CL extends from one end of the stack 20 along the Z-direction, penetrating the stack 20 and extending within the stack 20 and into the source layer BSL. Each of the multiple columnar bodies CL includes a semiconductor body 210, a memory film 220, and a core layer 230. Each columnar body CL includes a core layer 230 located in its center, a semiconductor body (semiconductor layer) 210 surrounding the core layer 230, and a memory film 220 surrounding the semiconductor body 210. Within the stack 20, the semiconductor body 210 extends along the memory holes MH in the Z-direction and penetrates the stack 20. The semiconductor body 210 is electrically connected to the source layer BSL. The memory film 220 is provided between the semiconductor body 210 and the electrode film 21 and has a cover insulating film 221, a charge trap film 222, and a tunnel insulating film 223. Multiple columnar bodies CL, one selected from each finger, are commonly connected to a single bit line 23 via vias 28 in Figure 1. Each of the columnar bodies CL is provided, for example, in the region of the memory cell array 2m.

[0030] Furthermore, a metal oxide 221a_1 and a block insulating film 221a_2 are provided between the columnar body CL and the electrode film 21. The metal oxide 221a_1 and the block insulating film 221a_2 cover the electrode film 21 (word line WL). Therefore, the metal oxide 221a_1 and the block insulating film 221a_2 are also provided between the electrode film 21 and the insulating film 22. The metal oxide 221a_1 is present at the interface between the block insulating film 221a_2 and the cover insulating film 221. The metal oxide 221a_1 is composed of a tetravalent metal oxide, for example, one of TiO2, ZrO2, HfO2, and RfO2. The metal oxide 221a_1 can be said to be a metal oxide with a higher dielectric constant than the silicon oxide film. The block insulating film 221a_2 is, for example, aluminum oxide. The block insulating film 221a_2 suppresses back tunneling of charge from the electrode film 21 to the memory film 220 side. The metal oxide 221a_1 can improve data retention characteristics (e.g., IRDR) and erase saturation voltage, and suppress degradation of the write saturation voltage. The metal oxide 221a_1 will be described in more detail later. The metal oxide 221a_1 and the block insulating film 221a_2 can be said to constitute a part of the memory film 220.

[0031] As shown in Figure 4, the shape of the memory hole MH in the XY plane is, for example, a circle or an ellipse. Consequently, the shape of the columnar body CL in the XY plane is also, for example, a circle or an ellipse.

[0032] The semiconductor body 210 has a cylindrical shape, for example, with a bottom. For example, polysilicon is used for the semiconductor body 210. For example, the semiconductor body 210 is undoped silicon. Alternatively, the semiconductor body 210 may be p-type silicon. The semiconductor body 210 serves as the channel for the drain-side selection transistor, the memory cell MC, and the source-side selection transistor. That is, multiple memory cell MCs have a storage area between the semiconductor body 210 and the electrode film 21 which becomes the word line WL, and are stacked in the Z direction. One end of multiple semiconductor bodies 210 within the same memory cell array 2m is electrically connected in common to the source layer BSL.

[0033] As shown in Figure 3, the memory film 220 includes, for example, a cover insulating film 221, a charge trap film 222, a tunnel insulating film 223, a metal oxide 221a_1, and a block insulating film 221a_2. The portion of the memory film 220 other than the metal oxide 221a_1 and the block insulating film 221a_2 is provided between the inner wall of the memory hole MH (laminated structure 20) and the semiconductor body 210 as part of a columnar body CL. The shape of the cover insulating film 221, the charge trap film 222, and the tunnel insulating film 223 is, for example, cylindrical. Each of the cover insulating film 221, the charge trap film 222, and the tunnel insulating film 223 is stretched in the Z direction.

[0034] The cover insulating film 221 is located between the semiconductor body 210 and the laminate 20. The cover insulating film 221 is provided between the insulating film 22 and the charge trap film 222, and between the block insulating film 221a_2 (or metal oxide 221a_1) and the charge trap film 222. The cover insulating film 221 includes, for example, silicon oxide. The cover insulating film 221 protects the charge trap film 222 from etching when the sacrificial film (21a in Figure 6A) is replaced with the electrode film 21 (replacement process).

[0035] The charge trap film 222 is located between the cover insulating film 221 and the semiconductor body 210. The charge trap film 222 is provided between the cover insulating film 221 and the tunnel insulating film 223. The charge trap film 222 contains, for example, silicon nitride and has trap sites that trap charge within the film. The portion of the charge trap film 222 sandwiched between the electrode film 21, which becomes the word line WL, and the semiconductor body 210 constitutes the memory area of ​​the memory cell MC as a charge trap section. The threshold voltage of the memory cell MC changes depending on the presence or absence of charge in the charge trap section, or the amount of charge trapped in the charge trap section. As a result, the memory cell MC retains information.

[0036] The tunnel insulating film 223 is provided between the semiconductor body 210 and the charge trap film 222. The tunnel insulating film 223 includes, for example, silicon oxide, or silicon oxide and silicon nitride. The tunnel insulating film 223 is a potential barrier between the semiconductor body 210 and the charge trap film 222. For example, when electrons are injected from the semiconductor body 210 to the charge trap film 222 (writing operation), and when holes are injected from the semiconductor body 210 to the charge trap film 222 (erasing operation), the electrons and holes pass through the potential barrier of the tunnel insulating film 223 (tunneling).

[0037] The core layer 230 fills the internal space of the cylindrical semiconductor body 210. The shape of the core layer 230 is, for example, columnar. The core layer 230 contains, for example, silicon oxide and is insulating.

[0038] Figure 5 is a cross-sectional view illustrating the memory cell portion of Figure 3 in more detail. The charge trap film 222 and cover insulating film 221 of the columnar body CL within the memory hole MH are shown. Block insulating film (aluminum oxide film) 221a_2 is provided between the cover insulating film 221 and the electrode film 21 of the columnar body CL, and between the insulating film 22 and the electrode film 21. Metal oxide 221a_1 is present at the interface between the cover insulating film 221 and the block insulating film 221a_2 of the columnar body CL, and at the interface between the insulating film 22 and the block insulating film 221a_2.

[0039] The concentration of metal oxide 221a_1 is highest at the interface between the cover insulating film 221 and the block insulating film 221a_2, and at the interface between the insulating film 22 and the block insulating film 221a_2. Furthermore, the concentration of metal oxide 221a_1 decreases from the interface between the cover insulating film 221 or insulating film 22 and the block insulating film 221a_2 toward the electrode film 21 or the block insulating film 221a_2. In addition, the concentration of metal oxide 221a_1 decreases from the interface between the cover insulating film 221 or insulating film 22 and the block insulating film 221a_2 toward the cover insulating film 221 or insulating film 22 of the columnar body CL. That is, the concentration of metal oxide 221a_1 gradually decreases from the interface between the cover insulating film 221 or insulating film 22 and the block insulating film 221a_2 toward both sides. The metal oxide 221a_1 is present in a range of 0.1 nm to 0.3 nm in a direction intersecting (e.g., orthogonal) to the interface between the block insulating film 221a_2 and the cover insulating film 221. The metal oxide 221a_1 may exist as a film or may be detected as a component without being recognized as a film.

[0040] Here, we will describe the configuration of the cover insulating film 221, metal oxide 221a_1, and block insulating film 221a_2 located between the charge trap film 222 and the electrode film 21.

[0041] Figures 6 to 10 are cross-sectional views showing examples of configurations between the charge trap film 222 and the electrode film 21.

[0042] In the example shown in Figure 6, a laminated film of cover insulating film 221 and block insulating film 221a_2 is provided between the charge trap film 222 and the electrode film 21. The thickness of the aluminum oxide film of block insulating film 221a_2 is, for example, about 2.7 nm. In the examples shown in Figures 6 to 9, the electrode film 21 is made of molybdenum. In this case, a titanium nitride film (not shown) as a barrier film is not provided between the block insulating film 221a_2 and the electrode film 21.

[0043] In the example shown in Figure 7, a laminated film of cover insulating film 221 and metal oxide 221a_1 is provided between the charge trap film 222 and the electrode film 21. In the example shown in Figure 7, metal oxide 221a_1 is provided between the cover insulating film 221 and the electrode film 21 instead of block insulating film 221a_2. The metal oxide 221a_1 is, for example, hafnium oxide (HfO2). The film thickness of the metal oxide 221a_1 is, for example, 5 nm and can be recognized as a film.

[0044] In the example shown in Figure 8, a multilayer film of cover insulating film 221, metal oxide 221a_1, and block insulating film 221a_2 is provided between the charge trap film 222 and the electrode film 21. In the example shown in Figure 8, the block insulating film 221a_2 and the metal oxide 221a_1 are provided. The metal oxide 221a_1 is provided between the cover insulating film 221 and the aluminum oxide film of the block insulating film 221a_2. The metal oxide 221a_1 is, for example, hafnium oxide (HfO). The thickness of the aluminum oxide film of the block insulating film 221a_2 is, for example, about 2.7 nm. The thickness of the metal oxide 221a_1 is, for example, 1 nm and can be recognized as a film.

[0045] In the example shown in Figure 9, similar to the configuration in Figure 8, a laminated film of cover insulating film 221, metal oxide 221a_1, and block insulating film 221a_2 is provided between the charge trap film 222 and the electrode film 21. The thickness of the aluminum oxide film of block insulating film 221a_2 may be, for example, about 2.7 nm. However, the thickness of the metal oxide 221a_1 is, for example, 0.1 nm or less, and is hardly recognizable as a film. The metal oxide 221a_1 can be detected as a component of hafnium oxide (HfO2) detected at the interface between the cover insulating film 221 and the block insulating film 221a_2.

[0046] Figure 10 is a cross-sectional view showing an example configuration when the electrode film 21 is made of tungsten. In the example in Figure 10, a laminated film of cover insulating film 221, block insulating film 221a_2, and barrier film 21b is provided between the charge trap film 222 and the electrode film 21. In this case, the barrier film 21b is provided between the aluminum oxide film of the block insulating film 221a_2 and the tungsten of the electrode film 21. The barrier film 21b is made of, for example, a titanium nitride film. The barrier film 21b is provided to improve the adhesion between the aluminum oxide film of the block insulating film 221a_2 and the tungsten of the electrode film 21. The other configurations in Figure 10 are the same as those in Figure 6. Therefore, in this example, the metal oxide 221a_1 is not provided.

[0047] Figure 11 is a graph showing the IRDR shift amount. The vertical axis of this graph shows the IRDR shift amount (voltage) relative to the configuration in Figure 10. That is, it is the IRDR shift amount of each configuration minus the IRDR shift amount of the configuration in Figure 10. The horizontal axis shows the respective configurations in Figures 6 to 9. The IRDR shift amount indicates the change in the data retention state (threshold voltage shift) of the memory cell MC that holds the data, after heating it to, for example, 240°C to 250°C. Therefore, a small IRDR shift amount is preferable because it indicates good data retention characteristics.

[0048] In the configuration shown in Figure 6, the aluminum oxide film of the block insulating film 221a_2 easily allows oxygen atoms to pass from Mo(MoOx), which readily forms an oxide film due to exposure to the source gas and atmosphere, to the cover insulating film 221. These oxygen atoms then combine with hydrogen atoms generated in the subsequent hydrogen annealing process and OH + Generates OH + This reacts with the silicon oxide film of the cover insulating film 221 to generate defects. Defects in the cover insulating film 221 make it easier for electrons in the charge trap film 222 to pass through to the electrode film 21. As a result, the amount of threshold voltage shift of the memory cell MC is relatively large.

[0049] In the configuration shown in Figure 7, the hafnium oxide of metal oxide 221a_1 does not allow oxygen atoms to pass through easily even when heated. Therefore, the cover insulating film 221 does not allow oxygen atoms to pass through easily, + This suppresses the generation of defects in the cover insulating film 221. As a result, the threshold voltage shift of the memory cell MC having the configuration of Figure 7 is smaller than the threshold voltage shift of the memory cell MC having the configuration of Figure 6.

[0050] In the configuration shown in Figure 8, both the hafnium oxide metal oxide 221a_1 and the aluminum oxide film of the block insulating film 221a_2 are provided. The hafnium oxide metal oxide 221a_1 makes it difficult for oxygen atoms to pass through. For this reason, the threshold voltage shift amount of the memory cell MC with the configuration of Figure 8 is smaller than the threshold voltage shift amount of the memory cell MC with the configuration of Figure 6.

[0051] In the configuration of Figure 9, both the hafnium oxide of metal oxide 221a_1 and the aluminum oxide film of the block insulating film 221a_2 are provided, but the hafnium oxide of metal oxide 221a_1 is very thin and is hardly recognized as a film. Therefore, the threshold voltage of the memory cell MC with the configuration of Figure 9 is shifted more significantly than the threshold voltage of the memory cell MC with the configuration of Figure 7 or Figure 8. However, because the hafnium oxide of metal oxide 221a_1 is present between the aluminum oxide film of the block insulating film 221a_2 and the cover insulating film 221, the threshold voltage of the memory cell MC with the configuration of Figure 9 is shifted less in magnitude than the threshold voltage of the memory cell MC with the configuration of Figure 6.

[0052] In the configuration shown in Figure 10, a laminated film consisting of a cover insulating film 221, a block insulating film 221a_2, and a barrier film 21b is provided between the charge trap film 222 and the electrode film 21. A metal oxide 221a_1 is not provided. However, the electrode film 21 is made of tungsten, which is less susceptible to oxidation than molybdenum. Therefore, the threshold voltage of the memory cell MC in Figure 10 is smaller in terms of shift amount than the threshold voltage of any of the memory cell MCs in Figures 6 to 9. Note that in Figure 11, the IRDR shift amount of the configuration in Figure 10 is set to zero (reference value).

[0053] Thus, when the electrode film 21 is molybdenum, by providing a metal oxide 221a_1 between the charge trap film 222 and the electrode film 21, either in place of or together with the aluminum oxide film of the block insulating film 221a_2, the IRDR shift amount can be reduced and the data retention characteristics can be improved. Note that the same effect can be obtained with any of the tetravalent metal oxides TiO2, ZrO2, HfO2, and RfO2 as the metal oxide 221a_1.

[0054] Figure 12 is a graph showing the write saturation voltage. The vertical axis of this graph represents the write saturation voltage. The horizontal axis represents the respective configurations of Figures 6 to 10. The write saturation voltage is the maximum value of the threshold voltage when data is written to the memory cell MC. When the write voltage applied to the word line WL (electrode film 21) is increased, the threshold voltage of the memory cell MC to which the data has been written also increases accordingly. However, when the amount of charge held in the charge trap film 222 saturates, the threshold voltage of the memory cell MC will not rise any further, even if the write voltage of the word line WL is increased. Therefore, the threshold voltage of the memory cell MC to which the data has been written has a maximum value (peak). This maximum value of the threshold voltage of the memory cell MC is called the "write saturation voltage". A higher write saturation voltage is preferable to facilitate data detection.

[0055] In the configuration shown in Figure 6, the aluminum oxide film of the block insulating film 221a_2 allows oxygen to pass through during the annealing process described later, oxidizing the interface between the charge trap film 222 and the cover insulating film 221 and creating defects. As a result, a large amount of charge can be retained at the interface between the charge trap film 222 and the cover insulating film 221. Consequently, the write saturation voltage becomes relatively high.

[0056] In the configuration shown in Figure 7, the hafnium oxide of metal oxide 221a_1 does not allow much oxygen to pass through during the annealing process, and does not generate many defects at the interface between the charge trap film 222 and the cover insulating film 221. For this reason, the write saturation voltage of the memory cell MC with the configuration shown in Figure 7 is lower than that of the memory cell MC with the configuration shown in Figure 6.

[0057] In the configuration of Figure 8, both the hafnium oxide of the metal oxide 221a_1 and the aluminum oxide film of the block insulating film 221a_2 are provided. Therefore, similar to the configuration of Figure 7, it does not allow much oxygen to pass through and does not generate many defects at the interface between the charge trap film 222 and the cover insulating film 221. For this reason, the write saturation voltage of the memory cell MC with the configuration of Figure 8 is lower than that of the memory cell MC with the configuration of Figure 6. The write saturation voltage of the memory cell MC with the configuration of Figure 8 is approximately equal to that of the memory cell MC with the configuration of Figure 7.

[0058] In the configuration of Figure 9, both the hafnium oxide metal oxide 221a_1 and the aluminum oxide film of the block insulating film 221a_2 are provided. Therefore, the write saturation voltage of the memory cell MC with the configuration of Figure 9 is lower than that of the memory cell MC with the configuration of Figure 6. However, the hafnium oxide metal oxide 221a_1 is very thin and is hardly perceived as a film. Therefore, the write saturation voltage of the memory cell MC with the configuration of Figure 9 is higher than that of the memory cell MC with the configuration of Figure 7 or Figure 8.

[0059] In the configuration of Figure 10, the metal oxide 221a_1 is not provided, but the electrode film 21 is made of tungsten. The write saturation voltage of the memory cell MC in Figure 10 is at the same level as in Figure 6 and is greater than that of any of the memory cell MCs in Figures 7 to 9. This is because annealing is performed after forming the aluminum oxide film of the metal oxide 221a_2, and before forming the barrier film 21b and the electrode film 21. In this annealing stage, the configuration of Figure 10 has the same configuration as the configuration of Figure 6, and this annealing process modifies the charge trap film 222, determining the write saturation voltage. Therefore, the write saturation voltage of the memory cell MC in Figure 10 is at the same level as in Figure 6.

[0060] Thus, when the metal oxide 221a_1 is thick, oxygen does not pass through it very well, and the modification of the charge trap film 222 by the annealing process does not progress. Therefore, when the metal oxide 221a_1 is thick, the write saturation voltage of the memory cell MC decreases. On the other hand, when the thickness or concentration of the metal oxide 221a_1 is reduced, oxygen can pass through it to some extent, and the modification of the charge trap film 222 by the annealing process progresses. Therefore, by reducing the thickness or concentration of the metal oxide 221a_1, the write saturation voltage of the memory cell MC increases and improves. Note that in addition to hafnium oxide (HfO2), the same effect can be obtained with any of the tetravalent metal oxides TiO2, ZrO2, and RfO2 for the metal oxide 221a_1.

[0061] As shown in Figures 11 and 12, the IRDR characteristics of the memory cell MC can be improved by providing a metal oxide 221a_1 between the aluminum oxide film of the cover insulating film 221 and the block insulating film 221a_2. On the other hand, if the metal oxide 221a_1 is too thick, the write saturation voltage of the memory cell MC will decrease, so it is preferable to have a thin film thickness or density of metal oxide 221a_1, as shown in the configuration of Figure 9. With the configuration of Figure 9, improvements can be made to both the IRDR characteristics and the write saturation voltage.

[0062] Figure 13 is a cross-sectional view showing an example of a configuration in which a metal oxide 221a_3 is added to the configuration of Figure 6. In the example of Figure 13, a laminated film of cover insulating film 221, block insulating film 221a_2, and metal oxide 221a_3 is provided between the charge trap film 222 and the electrode film 21. This example differs from the configuration of Figure 6 in that the metal oxide 221a_3 is provided between the block insulating film 221a_2 and the electrode film 21. The metal oxide 221a_3 may be any tetravalent metal oxide such as TiO2, ZrO2, HfO2, and RfO2, similar to the metal oxide 221a_1. The metal oxide 221a_3 may have a film thickness of, for example, 1 nm and be recognizable as a film. The other components of Figure 13 may be the same as those of the configuration of Figure 6.

[0063] Figure 14 is a cross-sectional view showing an example of a configuration in which metal oxide 221a_3 is added to the configuration of Figure 9. In the example of Figure 14, a laminated film of cover insulating film 221, metal oxide 221a_1, block insulating film 221a_2, and metal oxide 221a_3 is provided between the charge trap film 222 and the electrode film 21. This example differs from the configuration of Figure 9 in that metal oxide 221a_3 is provided at the interface between the block insulating film 221a_2 and the electrode film 21. Metal oxide 221a_3 may be, for example, hafnium oxide (HfO2), similar to metal oxide 221a_1, but may be any other tetravalent metal oxide such as TiO2, ZrO2, HfO2, and RfO2. Metal oxide 221a_3 may have a film thickness of, for example, 1 nm and be recognizable as a film. That is, metal oxide 221a_1 is lower in concentration or thinner in film thickness than metal oxide 221a_3. The other components of Figure 14 can be the same as those in Figure 9.

[0064] Figure 15 is a graph showing the erase saturation voltage. The vertical axis of this graph represents the threshold voltage (erasure voltage) of the memory cell MC after erasure. The horizontal axis represents the voltage Vera applied to the word line WL (electrode film 21) during the erase operation. The erase saturation voltage is the minimum value of the threshold voltage of the memory cell MC when data is erased. If the absolute value of the voltage Vera applied to the word line WL (electrode film 21) is increased (increased towards the negative voltage side), the threshold voltage of the memory cell MC after data erasure will decrease accordingly. However, once all the charge in the charge trap film 222 is removed, even if the absolute value of the voltage Vera on the word line WL is further increased, the threshold voltage of the memory cell MC will not decrease any further. Therefore, the threshold voltage of the memory cell MC after data erasure has a minimum value (bottom). This minimum value of the threshold voltage of the memory cell MC is called the "erasure saturation voltage". A low erase saturation voltage is preferable to facilitate data detection.

[0065] The erase voltage for the configuration shown in Figure 10 is represented by the graph shown by line L10. Defects with fixed charges are likely to occur at the interface between the silicon oxide film of the cover insulating film 221 and the aluminum oxide film of the block insulating film 221a_2. Therefore, during the erase operation, electrons injected from the electrode film 21 to the charge trap film 222 are trapped in these defects, worsening the erase saturation voltage. As a result, the erase saturation voltage B10 for the configuration shown in Figure 10 is relatively high.

[0066] The erase voltage for the configuration in Figure 13 is shown in the graph by line L13. In this case, the erase saturation voltage B13 is lower than that of the configuration in Figure 10. However, the configuration in Figure 13 also has an interface between the silicon oxide film of the cover insulating film 221 and the aluminum oxide film of the block insulating film 221a_2. Therefore, during the erase operation, electrons injected from the electrode film 21 to the charge trap film 222 are trapped in this defect, so the erase saturation voltage is inferior compared to the configuration in Figure 14.

[0067] In contrast, the erase voltage for the configuration in Figure 14 is shown in the graph by line L14. In this case, the erase saturation voltage B14 is more than 2V lower than that of the configuration in Figure 10, and about 0.8V lower than that of the configuration in Figure 13. This is because the metal oxide 221a_1 provided at the interface between the silicon oxide film of the cover insulating film 221 and the aluminum oxide film of the block insulating film 221a_2 suppresses the occurrence of defects at this interface.

[0068] As described above, by providing metal oxides 221a_1 and 221a_3, the erase saturation voltage can be significantly improved. However, as explained with reference to Figure 12, if the metal oxide 221a_1 is thick, the write saturation voltage deteriorates. Therefore, it is preferable for the thickness of the metal oxide 221a_1 to be thin, as explained with reference to Figure 9. This makes it possible to increase the write saturation voltage and decrease the erase saturation voltage.

[0069] The annealing process for modifying the charge trap film 222 is performed after the formation of the aluminum oxide film of the block insulating film 221a_2 and before the formation of the metal oxide 221a_3. Therefore, the write saturation voltage of the configuration in Figure 14 is approximately the same as that of Figure 9. Thus, the configuration in Figure 14 is more advantageous than those in Figures 7 and 8 in terms of write saturation voltage.

[0070] Furthermore, the IRDR characteristics of the configuration in Figure 14 are clearly improved compared to the configuration in Figure 9 because the metal oxide 221a_3 is added. Therefore, the configuration in Figure 14 is equally or even more preferable than the configuration in Figure 9 when considering IRDR characteristics and write saturation voltage. As a result, it can be said that the configuration in Figure 14 is the most preferable in terms of IRDR characteristics, write saturation voltage, and erase saturation voltage. Note that although the electrode film 21 is made of molybdenum, similar effects can be obtained with tungsten.

[0071] Based on the above description, by providing the metal oxide 221a_1 at the interface between the cover insulating film 221 and the aluminum oxide film of the block insulating film 221a_2, as shown in the configuration of Figure 9, the IRDR characteristics, write saturation voltage, and erase saturation voltage can be improved.

[0072] Furthermore, as shown in the configuration of Figure 14, by providing the metal oxide 221a_3 between the aluminum oxide film of the block insulating film 221a_2 and the electrode film 21, the IRDR characteristics and erasure saturation voltage can be further improved.

[0073] By lowering the erasure saturation voltage, the operating voltage of the word line WL can be reduced. Consequently, the breakdown voltage between adjacent electrode films 21 in the Z direction can be reduced, allowing the thickness of the insulating film 22 in the Z direction to be reduced. For example, the thickness of the insulating film 22 in the Z direction can be reduced to less than approximately 40 nm.

[0074] Next, a method for manufacturing a semiconductor memory device according to this embodiment will be described.

[0075] Figures 16 to 21 are cross-sectional views showing an example of the manufacturing process of the semiconductor memory device 1 according to this embodiment.

[0076] The laminated structure 20 of the array chip 2 is first formed by alternately stacking material films 21a and insulating films 22 in the -Z direction, as shown in Figure 16. For example, a silicon nitride film is used for the material film 21a. For example, a silicon oxide film is used for the insulating film 22.

[0077] Next, multiple memory holes MH penetrating the laminate 20 in the Z direction are formed using lithography and etching techniques. Then, as shown in Figure 17, columnar bodies CL are formed within the multiple memory holes MH. The columnar bodies CL are formed by depositing a cover insulating film 221, a charge trap film 222, a tunnel insulating film 223, and a semiconductor body 210 on the side walls of the laminate 20 within the memory holes MH.

[0078] Next, slits ST, as shown in Figure 2 or Figure 5, are formed in the laminate 20 using lithography and etching techniques. The slits ST are provided so as to penetrate the laminate 20 in the Z direction.

[0079] Next, the material film 21a is removed through the slit ST using a wet etching method. As a result, as shown in Figure 18, a space C is formed between adjacent insulating films 22 in the Z direction (where the material film 21a was located).

[0080] Figures 19 to 21 show enlarged cross-sections of space C.

[0081] Using the Atomic Layer Deposition (ALD) method, metal oxide 221a_1 is deposited through the slit ST into space C and the inner wall of slit ST. The metal oxide 221a_1 is introduced into the exposed side surfaces of the columnar body CL and the surface of the insulating film 22 within space C and slit ST. The metal oxide 221a_1 may be any tetravalent metal oxide such as TiO2, ZrO2, HfO2, and RfO2. The metal oxide 221a_1 has a concentration or thickness (e.g., 0.1 nm) such that it is not recognized as a film.

[0082] Next, using the ALD method, an aluminum oxide film of the block insulating film 221a_2 is deposited through the slit ST into space C and the inner wall of the slit ST. The thickness of the aluminum oxide film of the block insulating film 221a_2 is, for example, about 2.7 nm.

[0083] Next, the laminate 20 and columnar body CL are annealed to modify the charge trap film 222. The annealing temperature is, for example, 240°C to 250°C. During the annealing process, oxygen passes through the aluminum oxide film of the block insulating film 221a_2 and the hafnium oxide of the metal oxide 221a_1. Although the hafnium oxide is less permeable to oxygen than the aluminum oxide film, it is so thin that it is not recognized as a film, so oxygen can pass through the metal oxide 221a_1. This allows oxygen to oxidize the interface between the charge trap film 222 and the cover insulating film 221, causing defects. As a result, the write saturation voltage can be increased.

[0084] Furthermore, the concentration of metal oxide 221a_1 is highest at the interface between the cover insulating film 221 and the block insulating film 221a_2. During the annealing process, metal oxide 221a_1 diffuses from the interface between the block insulating film 221a_2 and the cover insulating film 221, and from the interface between the block insulating film 221a_2 and the insulating film 22. Metal oxide 221a_1 diffuses from the interface between the block insulating film 221a_2 and the cover insulating film 221 or insulating film 22 to a range of, for example, 0.1 nm to 0.3 nm. Metal oxide 221a_1 may exist as a film, or it may be detected as a component without being recognized as a film.

[0085] Next, as shown in Figure 21, a metallic material such as molybdenum or tungsten is deposited on the inner wall of space C as the material for the electrode film 21.

[0086] Next, an insulating film 101, such as a silicon oxide film, is formed on the inner wall of the slit ST.

[0087] Next, a metal film such as molybdenum or tungsten is embedded inside the insulating film 101 in the slit ST. This forms the source wiring LI inside the slit ST shown in Figure 5, resulting in the structure shown in Figure 3.

[0088] Subsequently, contacts and multilayer wiring layers are formed, completing the semiconductor memory device 1 according to this embodiment. In this case, the structure shown in Figure 9 is obtained.

[0089] Furthermore, in order to form the structure shown in Figure 14, an aluminum oxide film of the block insulating film 221a_2 is formed, and after an annealing process, the metal oxide 221a_3 is deposited through the slit ST using the ALD method or the like, on the space C and the inner wall of the slit ST. The metal oxide 221a_3 is formed on the aluminum oxide film of the block insulating film 221a_2 within the space C and the slit ST. The metal oxide 221a_3 can be any tetravalent metal oxide such as TiO2, ZrO2, HfO2, and RfO2, similar to the metal oxide 221a_1. Subsequently, the structure shown in Figure 14 is obtained by forming the electrode film 21.

[0090] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of symbols]

[0091] 1. Semiconductor memory 20 Laminate ST Slit 2m memory cell array 21 Electrode membrane 22 Insulating film CL columnar body 210 Semiconductor Body 220 memory film 221a_1 Metal oxides 221a_2 Block insulating film 221 Cover insulating film 222 Charge trap membrane 223 Tunnel insulating film 230 core layers

Claims

1. A laminate in which multiple electrode films and multiple first insulating films are alternately stacked in a first direction, A columnar body provided penetrating the laminate in the first direction, An aluminum oxide film is provided between the columnar body and the electrode film, A first tetravalent metal oxide present at the interface between the columnar body and the aluminum oxide film, A semiconductor memory device equipped with the following features.

2. The columnar body is A semiconductor layer provided penetrating the laminate in the first direction, A second insulating film is provided between the semiconductor layer and the laminate, A third insulating film is provided between the second insulating film and the semiconductor layer, The third insulating film and the semiconductor layer are provided together, including a fourth insulating film. The semiconductor memory device according to claim 1, wherein the first tetravalent metal oxide is present at the interface between the aluminum oxide film and the second insulating film.

3. The semiconductor memory device according to claim 2, wherein the concentration of the first tetravalent metal oxide is maximized at the interface between the aluminum oxide film and the second insulating film.

4. The semiconductor memory device according to claim 3, wherein the concentration of the first tetravalent metal oxide decreases from the interface between the aluminum oxide film and the second insulating film toward the electrode film.

5. The semiconductor memory device according to claim 2, wherein the first tetravalent metal oxide is present in a range of 0.1 nm to 0.3 nm in a second direction intersecting the interface between the aluminum oxide film and the second insulating film.

6. The semiconductor memory device according to any one of claims 1 to 5, further comprising a second tetravalent metal oxide present at the interface between the aluminum oxide film and the electrode film.

7. The first tetravalent metal oxide is TiO ２ , ZrO ２ , HfO ２ and RfO ２ A semiconductor memory device according to claim 1, which is any of the following.

8. A laminate is formed by alternately stacking multiple material films and multiple first insulating films in a first direction. A columnar body is formed that penetrates the laminate in the first direction, Remove the aforementioned multiple material films, The plurality of material films are removed and the first tetravalent metal oxide is introduced to the exposed side surface of the columnar body. An aluminum oxide film is formed on the side surface of the columnar body. The laminate is heat-treated, A method for manufacturing a semiconductor memory device, comprising forming an electrode film in the space obtained by removing the aforementioned plurality of material films.

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