Oscillator Circuit

Abstract

To provide an oscillation circuit capable of suppressing power supply voltage dependency of an oscillation frequency.SOLUTION: An oscillation circuit includes a first voltage comparison unit that receives supply of a power supply voltage via a constant current source and outputs a first signal indicating the comparison result between the input potential and a threshold, a second voltage comparison unit that receives supply of a power supply voltage via a constant current source and outputs a second signal indicating the result of comparison between the input potential and the threshold, an RS flip-flop circuit that receives inputs of a first signal at a reset terminal and a second signal at a set terminal and outputs first and second oscillation signals, a first charging / discharging unit that charges / discharges a first capacitor on the basis of the first oscillation signal, a second charging / discharging unit that charges / discharges a second capacitor on the basis of the second oscillation signal, a first dummy switch that is ON / OFF-controlled according to the second oscillation signal and adds a predetermined capacitance to a first node, and a second dummy switch that is ON / OFF-controlled according to the signal level of the first oscillation signal and adds a predetermined capacitance to a second node.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to an oscillator circuit, and more particularly to a relaxation oscillator circuit using a comparator. [Background technology]

[0002] A relaxation oscillator circuit that performs oscillation by charging and discharging a capacitor is used as a clock generating circuit mounted on an LSI. A relaxation oscillator circuit has a problem in that the frequency of the output clock fluctuates due to variations in the manufacturing process of the comparator that compares the voltage across the capacitor with a reference voltage, and variations in the power supply voltage and temperature during operation. Therefore, a relaxation oscillator circuit that aims to generate a clock with a constant frequency has been proposed (for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2013-46378 A Summary of the Invention [Problem to be solved by the invention]

[0004] In the relaxation oscillator circuit of the above-mentioned prior art, the threshold fluctuation of the comparator is suppressed by limiting the current using a constant current source. However, in this configuration, the current limit is activated when the output of the comparator is set to H (high level), so it takes time for the output of the comparator to become H. The higher the power supply voltage, the longer the time required. As a result, there is a problem that the response delay of the comparator and the RS latch causes the oscillation frequency to depend on the power supply voltage.

[0005] The present invention has been made in consideration of the above problems, and has an object to provide an oscillation circuit capable of suppressing the dependence of the oscillation frequency on the power supply voltage. [Means for solving the problem]

[0006] The oscillator circuit according to the present invention includes a first voltage comparator unit that receives a power supply voltage via a first constant current source, and outputs a first signal of logic level 0 when a potential input to an input terminal exceeds a threshold, and outputs a first signal of logic level 1 when the potential input to the input terminal is equal to or lower than the threshold; a second voltage comparator unit that receives a power supply voltage via a second constant current source, and outputs a second signal of logic level 0 when a potential input to the input terminal exceeds a threshold, and outputs a second signal of logic level 1 when the potential input to the input terminal is equal to or lower than the threshold; an RS flip-flop circuit that receives the first signal at a reset terminal and the second signal at a set terminal, and outputs a first oscillation signal and a second oscillation signal obtained by inverting the first oscillation signal based on the first signal and the second signal; a first capacitor having one end connected to a ground potential; and a second capacitor having one end connected to a ground potential, the drains of which are connected to each other and the other end of the first capacitor and the input of the first voltage comparator unit are connected to each other via a first node. a first charging / discharging unit including a first transistor of a first conductivity type and a second transistor of a second conductivity type connected to an input end of the second voltage comparison unit and turned on and off complementarily in response to the first oscillation signal, the first charging / discharging unit charging / discharging the first capacitor based on the first oscillation signal; a second charging / discharging unit including a third transistor of the first conductivity type and a fourth transistor of the second conductivity type, the drains of which are connected to each other and connected to the other end of the second capacitor and an input end of the second voltage comparison unit via a second node, the third transistor of the first conductivity type and a fourth transistor of the second conductivity type, the fourth transistor of the second conductivity type being turned on and off complementarily in response to the second oscillation signal, the second charging / discharging unit charging / discharging the second capacitor based on the second oscillation signal; a first dummy switch connected to the first node, controlled to be turned on and off in response to a signal level of the second oscillation signal, and adding a predetermined capacitance to the first node when in an on state; and a second dummy switch provided at the second node, controlled to be turned on and off in response to the signal level of the first oscillation signal, and adding a predetermined capacitance to the second node when in an on state. Effect of the Invention

[0007] According to the oscillator circuit of the present invention, it is possible to suppress the dependence of the oscillation frequency on the power supply voltage. [Brief description of the drawings]

[0008] [Figure 1] 1 is a circuit diagram showing a configuration of an oscillator circuit according to a first embodiment of the present invention. [Diagram 2] FIG. 2 is a diagram illustrating a truth table of an RS flip-flop circuit. [Diagram 3] 4 is a time chart showing changes in signals and potentials in the oscillation circuit of the first embodiment. [Figure 4] FIG. 11 is a circuit diagram illustrating a configuration of an oscillator circuit according to a second embodiment of the present invention. [Diagram 5] FIG. 11 is a diagram illustrating a configuration of a variable capacitance section in an oscillation circuit according to a second embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0009] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will now be described in detail. In the following description of each embodiment and in the accompanying drawings, the same reference numerals are used to designate substantially the same or equivalent parts. EXAMPLES

[0010] 1 is a circuit diagram showing a configuration of an oscillator circuit 100 according to a first embodiment of the present invention. The oscillator circuit 100 includes an RS flip-flop circuit 10, a first inverter INV1A, a second inverter INV1B, a first capacitor C1A, a second capacitor C1B, a constant current source I1A, a constant current source I2A, a constant current source I1B, a constant current source I2B, a transistor MP1A, a transistor MN1A, a transistor MP1B, a transistor MN1B, a dummy switch MN2A, and a dummy switch MN2B.

[0011] The RS flip-flop circuit 10 receives the output signal of the inverter INV1A at a reset terminal R and the output signal of the inverter INV1B at a set terminal S, and outputs signals from output terminals Q and QB. The output of the output terminal QB is output to the outside of the oscillation circuit 100 as an oscillation signal fout. The oscillation signal fout is a binary signal whose signal level changes between logic levels 0 and 1. The output signal from the output terminal Q is the oscillation signal fout, which is a signal in phase with the logic levels changing between logic levels 0 and 1 (i.e., a signal having a signal level that is the inverse of the oscillation signal fout).

[0012] 2 is a table showing a truth table of the RS flip-flop circuit 10. When the inputs to the set terminal S and the reset terminal R are both at logic level 0, the outputs of the output terminals Q and QB are maintained in their current states. When the input to the set terminal S is at logic level 0 and the input to the reset terminal R is at logic level 1, a signal of logic level 0 is output from the output terminal Q and a signal of logic level 1 is output from the output terminal QB. When the input to the set terminal S is at logic level 1 and the input to the reset terminal R is at logic level 0, a signal of logic level 1 is output from the output terminal Q and a signal of logic level 0 is output from the output terminal QB.

[0013] 1 again, the first inverter INV1A has an input terminal connected to the node n1A and an output terminal connected to the reset terminal R of the RS flip-flop circuit 10. The first inverter INV1A functions as a comparator, and when the potential level of the input signal, i.e., the potential VC1A of the node n1A, exceeds the threshold Th, it outputs an inverted signal obtained by inverting the input signal. The output signal is input to the reset terminal R of the RS flip-flop circuit 10 as a reset signal.

[0014] The first inverter INV1A operates by receiving the power supply voltage VDD through the constant current source I2A. Since the constant current source I2A is inserted in the supply line of the power supply voltage VDD, the supply of the power supply voltage VDD is current-limited. This suppresses fluctuations in the threshold Th due to fluctuations in the power supply voltage VDD.

[0015] The second inverter INV1B has an input terminal connected to the node n1B and an output terminal connected to the set terminal S of the RS flip-flop circuit 10. The second inverter INV1B functions as a comparator, and when the potential level of the input signal, i.e., the potential VC1B of the node n1B, exceeds the threshold Th, it outputs an inverted signal obtained by inverting the input signal. The output signal is input to the set terminal S of the RS flip-flop circuit 10 as a set signal.

[0016] The second inverter INV1B operates by receiving the power supply voltage VDD through the constant current source I2B. Since the constant current source I2B is inserted in the supply line of the power supply voltage VDD, the supply of the power supply voltage VDD is current-limited. This suppresses fluctuations in the threshold Th due to fluctuations in the power supply voltage VDD.

[0017] The transistor MP1A and the transistor MN1A are a transistor pair that constitute the charge / discharge unit 11 that charges and discharges the capacitor C1A. The transistor MP1A is composed of a P-channel MOSFET. The transistor MN1A is composed of an N-channel MOSFET. The transistors MP1A and MN1A have a CMOS switch configuration and are controlled to be turned on and off complementarily.

[0018] A power supply voltage VDD is supplied to the source of the transistor MP1A via a constant current source I1A. A ground potential is supplied to the source of the transistor MN1A. The drains of the transistors MP1A and MN1A are connected to each other.

[0019] The gates of the transistors MP1A and MN1A are connected to each other and receive the oscillation signal fout output from the output terminal QB of the RS flip-flop circuit 10. When the oscillation signal fout is at logic level 0 (i.e., L level), the transistor MP1A is on and the transistor MN1A is off. On the other hand, when the oscillation signal fout is at logic level 1 (i.e., H level), the transistor MP1A is off and the transistor MN1A is on.

[0020] The transistor MP1B and the transistor MN1B are a transistor pair that constitute the charge / discharge unit 12 that charges and discharges the capacitor C1B. The transistor MP1B is composed of a P-channel MOSFET. The transistor MN1B is composed of an N-channel MOSFET. The transistors MP1B and MN1B have a CMOS switch configuration and are controlled to be turned on and off complementarily.

[0021] A power supply voltage VDD is supplied to the source of the transistor MP1B via a constant current source I1B. A ground potential is supplied to the source of the transistor MN1B. The drains of the transistors MP1B and MN1B are connected to each other.

[0022] The gates of the transistors MP1B and MN1B are connected to each other and receive a signal output from the output terminal Q of the RS flip-flop circuit 10. When the output signal from the output terminal Q is at logic level 0 (i.e., L level), the transistor MP1B is on and the transistor MN1B is off. On the other hand, when the output signal from the output terminal Q is at logic level 1 (i.e., H level), the transistor MP1B is off and the transistor MN1B is on.

[0023] One end of the capacitor C1A is connected to the node n1A, and the other end is grounded. The capacitor C1A is charged and discharged by turning on and off a CMOS switch consisting of a transistor MP1A and a transistor MN1A. When the transistor MP1A is on and the transistor MN1A is off, a constant current from the constant current source I1A is supplied to the capacitor C1A via the node n1A, thereby charging the capacitor C1A. When the transistor MP1A is off and the transistor MN1A is on, the capacitor C1A is discharged via the ground line. When the capacitor C1A is charged, the potential of the node n1A rises, and when the capacitor C1A is discharged, the potential of the node n1A falls.

[0024] One end of the capacitor C1B is connected to the node n1B, and the other end is grounded. The capacitor C1B is charged and discharged by turning on and off a CMOS switch consisting of a transistor MP1B and a transistor MN1B. When the transistor MP1B is on and the transistor MN1B is off, a constant current from the constant current source I1B is supplied to the capacitor C1B via the node n1B, thereby charging the capacitor C1B. When the transistor MP1B is off and the transistor MN1B is on, the capacitor C1B is discharged via the ground line. When the capacitor C1B is charged, the potential of the node n1B rises, and when the capacitor C1B is discharged, the potential of the node n1B falls.

[0025] The dummy switch MN2A is composed of an N-channel MOSFET whose source and drain are connected to each other. The source and drain of the dummy switch MN2A are connected to the drains of the transistors MP1A and MN1A, and are also connected to a node n1A. The gate of the dummy switch MN2A is connected to the output terminal Q of the RS flip-flop circuit 10 together with the gates of the transistors MP1B and MN1B, and receives an output signal from the output terminal Q.

[0026] The dummy switch MN2A is turned on when the output signal from the output terminal Q of the RS flip-flop circuit 10 is at logic level 1, and is turned off when the output signal from the output terminal Q is at logic level 0. Since the output signal from the output terminal Q is a signal in phase opposite to that of the oscillation signal fout from the output terminal QB, the dummy switch MN2A is controlled to be turned on and off in phase opposite to that of the transistor MN1A that receives the oscillation signal fout.

[0027] When the dummy switch MN2A is turned on, the capacitance of the transistor that constitutes the dummy switch MN2A is added to the node n1A. As a result, the potential VC1A of the node n1A starts to rise in response to the charging of the capacitor C1A from the state in which the voltage of the capacitance is added.

[0028] The dummy switch MN2B is composed of an N-channel MOSFET whose source and drain are connected to each other. The source and drain of the dummy switch MN2B are connected to the drains of the transistors MP1B and MN1B, and are also connected to a node n1B. The gate of the dummy switch MN2B is connected to the output terminal QB of the RS flip-flop circuit 10 together with the gates of the transistors MP1A and MN1A, and receives the oscillation signal fout.

[0029] The dummy switch MN2B is on when the oscillation signal fout is at logic level 1, and is off when the oscillation signal fout is at logic level 0. Since the oscillation signal fout is a signal in phase opposite to that of the output signal from the output terminal Q, the dummy switch MN2B is controlled to be turned on and off in phase opposite to that of the transistor MN1B which receives the output signal from the output terminal Q.

[0030] When the dummy switch MN2B is turned on, the capacitance of the transistor that constitutes the dummy switch MN2B is added to the node n1B. As a result, the potential VC1B of the node n1B starts to rise in response to the charging of the capacitor C1B from the state in which the voltage of the capacitance is added.

[0031] Next, the operation of the oscillator circuit 100 of this embodiment will be described.

[0032] FIG. 3 is a time chart showing the relationship between the change in the signal level of the oscillation signal fout and the change in the voltage level of the potential VC1A of the node n1A.

[0033] During a period T1 when the oscillation signal fout is at logic level 1, the transistor MP1A is off and the transistor MN1A is on. Since the transistor MN1A is on, the capacitor C1A is discharged and goes into a reset state. In response to this, the potential VC1A of the node n1A goes to the ground potential level (i.e., the L level).

[0034] When the oscillation signal fout becomes a logic level 0, the transistor MP1A is turned on and the transistor MN1A is turned off, causing the current I1 from the constant current source I1A to be supplied to the capacitor C1A via the transistor MP1A and the node n1A, and charging of the capacitor C1A begins.

[0035] At that time, the output signal from output terminal Q becomes logic level 1 and is applied to dummy switch MN2A. Dummy switch MN2A turns on, and the voltage corresponding to the capacitance of dummy switch MN2A is added to potential VC1A of node n1A. Therefore, during period T2 shown in Figure 3, the potential VC1A of node n1A starts from an initial state where it is higher than the set potential by the voltage corresponding to the capacitance of dummy switch MN2A (shown as ΔV in the figure), and the voltage level rises in accordance with the charging of capacitor C1A.

[0036] When the voltage level of the potential VC1A of the node n1A exceeds the threshold Th, the inverter INV1A outputs a signal of logic level 0. A signal of logic level 0 is supplied to the reset terminal R of the RS flip-flop circuit 10.

[0037] On the other hand, the transistor MP1B, the transistor MN1B, and the dummy switch MN2B are turned on and off in an opposite phase (in other words, half-phase delay) to the operations of the transistor MP1A, the transistor MN1A, and the dummy switch MN2A. As a result, the capacitor C1B is discharged, the potential VC1B of the node n1B becomes L level, and the inverter INV1B outputs a signal of logic level 1. A signal of logic level 1n is supplied to the set terminal S of the RS flip-flop circuit 10. The RS flip-flop circuit 10 outputs an oscillation signal fout of logic level 1.

[0038] Thus, in the oscillator circuit 100 of this embodiment, the initial value ΔV of the potential VC1A of the node n1A when the voltage rises (when charging) becomes high due to the so-called charge injection effect that occurs by controlling the dummy switch MN2A to be on and off in opposite phase to the transistor MN1A.

[0039] This initial value ΔV increases in proportion to the voltage value of the power supply voltage VDD. Therefore, the larger the voltage value of the power supply voltage VDD, the shorter the time it takes for the potential VC1A of the node n1A to exceed the threshold Th of the comparator INV1A (hereinafter referred to as a reduction in the voltage rise time).

[0040] In the oscillator circuit 100 of this embodiment, the voltage rise time is shortened, thereby offsetting the response delay of the comparator and the RS flip-flop circuit, and the dependence of the oscillation frequency on the power supply voltage can be reduced.

[0041] That is, in a configuration in which constant current sources I2A and I2B are provided in the supply line of the power supply voltage VDD, the timing at which the outputs of the comparators INV1A and INV1B change from L level to H level is delayed due to current limiting, causing a response delay in the comparators INV1A, INV1B and the RS flip-flop circuit 10. The larger the voltage value of the power supply voltage VDD, the larger the amount of response delay. For this reason, in a configuration that does not have dummy switches MN2A and MN2B as in this embodiment, the oscillation frequency depends on the power supply voltage.

[0042] In contrast, in the oscillator circuit 100 of this embodiment, the response delay of the comparator and the RS flip-flop can be offset by shortening the time required for the potential VC1A to exceed the threshold Th. Also, while the response delay of the comparator and the RS flip-flop is proportional to the power supply voltage VDD, the time required for the potential VC1A to exceed the threshold Th is inversely proportional to the power supply voltage VDD, so that the power supply voltage dependency of the oscillation frequency can be reduced.

[0043] As described above, according to the oscillator circuit 100 of this embodiment, it is possible to suppress the dependence of the oscillation frequency on the power supply voltage. EXAMPLES

[0044] Next, a description will be given of a second embodiment of the present invention. The oscillation circuit of the second embodiment differs from the oscillation circuit of the first embodiment in the configuration and operation of the dummy switch.

[0045] 4 is a circuit diagram showing a configuration of an oscillator circuit 200 according to a second embodiment of the present invention. The oscillator circuit 200 includes a dummy switch MN3A, a dummy switch MN3B, a NAND gate 13, and a NAND gate 14.

[0046] The dummy switch MN3A is composed of a plurality of N-channel MOSFETs whose sources and drains are connected to each other. The plurality of N-channel MOSFETs receive an output signal from the NAND gate 13 and are controlled to be turned on and off in response to the output signal.

[0047] 5 is a circuit diagram showing the configuration of the dummy switch MN3A. The dummy switch MN3A has a configuration in which n N-channel MOSFETs, transistors MN3-1, MN3-2, ..., MN3-n (n is an integer of 2 or more), are connected in cascade. The transistors MN3-1 to MN3-n receive an output signal from a NAND gate 13 at their respective gates and are controlled to be selectively turned on and off.

[0048] 4 again, the first input terminal of the NAND gate 13 is connected to the output terminal QB of the RS flip-flop circuit 10 and receives the oscillation signal fout as input. The enable signal en is input to the second input terminal of the NAND gate 13. The NAND gate 13 outputs a signal which is the NAND of the oscillation signal fout and the enable signal en.

[0049] The dummy switch MN3B has the same configuration as the dummy switch MN3A, that is, the dummy switch MN3B is composed of a plurality of N-channel MOSFETs whose sources and drains are connected to each other, and is controlled to be turned on and off in response to the application of the output signal of the NAND gate 14.

[0050] The NAND gate 14 has a first input terminal connected to the output terminal QB of the RS flip-flop circuit 10 and receives the oscillation signal fout as input. The enable signal en is input to a second input terminal of the NAND gate 13. The NAND gate 14 outputs a signal that is the NAND of the output signal from the output terminal Q and the enable signal en.

[0051] The enable signal en functions as a selection signal for selecting a transistor to be controlled to be turned on and off by a signal supplied from the RS flip-flop circuit 10, from among the multiple transistors constituting each of the dummy switches MN3A and MN3B.

[0052] For example, when an enable signal en that selects only the transistor MN3-1 among the transistors that make up the dummy switch MN3A is supplied to the NAND gate 13, the NAND gate 13 outputs a signal that controls the transistor MN3-1 to be on and off in the opposite phase to the oscillation signal fout. This signal is supplied to the gate of the transistor MN3-1. In addition, since the same enable signal en is supplied to the NAND gate 14, the transistor corresponding to the transistor MN3-1 among the multiple transistors that make up the dummy gate MN3B is selectively controlled to be on and off by the output signal of the NAND gate 14. Note that when the enable signal en is set to the L level, the gates of the dummy switches MN3A and MN3B are fixed, and the capacitance values ​​added to the nodes n1A and n1B are fixed.

[0053] The dummy gate MN3A is controlled to be turned on and off in opposite phase to the transistor MN1A. Therefore, similar to the first embodiment, the initial value ΔV of the potential VC1A of the node n1A when the voltage rises (when charging) becomes high due to the so-called charge injection effect. Similarly, the dummy gate MN3B is controlled to be turned on and off in opposite phase to the transistor MN1B, and the initial value ΔV of the potential VC1B of the node n1B when the voltage rises (when charging) becomes high. This makes it possible to offset the response delay of the comparator and the RS flip-flop circuit and reduce the dependence of the oscillation frequency on the power supply voltage, similar to the first embodiment.

[0054] Furthermore, in the oscillator circuit 200 of this embodiment, it is possible to select a transistor to be controlled to be on or off according to the output signal from the RS flip-flop circuit 10 by supplying an enable signal en. Therefore, according to the oscillator circuit 200 of this embodiment, the initial value ΔV at the time of voltage rise of each of the nodes n1A and n1B can be adjusted according to the voltage value of the power supply voltage VDD. For example, by performing an adjustment when the oscillator circuit 200 is shipped as a product, it is possible to set the initial value ΔV to an appropriate value and accurately reduce the dependence of the oscillation frequency on the power supply voltage.

[0055] The present invention is not limited to the above embodiment. For example, in the above embodiment, the first inverter INV1A and the second inverter INV1B are used to compare the potentials of the nodes n1A and n1B with the threshold Th, and a reset signal and a set signal are output based on the comparison result. However, the part may be configured using a comparator amplifier instead of the first inverter INV1A and the second inverter INV1B. That is, it is sufficient if the voltage comparator functions as a voltage comparator that compares the potentials of each node with the threshold and outputs a signal of logic level 0 if the potentials exceed the threshold and a signal of logic level 1 if the potentials are equal to or less than the threshold.

[0056] In addition, in the above embodiment, an example was described in which the power supply voltage VDD is supplied to the charge / discharge unit 11 via the constant current source I1A, and the power supply voltage VDD is supplied to the charge / discharge unit 12 via the constant current source I1B, but this configuration is not limited to this, and the power supply voltage VDD may be supplied to the charge / discharge units 11 and 12 via a common constant current source.

[0057] In the above embodiment, the dummy switch is an N-channel MOSFET. However, the present invention is not limited to this configuration, and the dummy switch may be a P-channel MOSFET or a capacitance element.

[0058] In addition, in the above embodiment, the discharged state of the capacitors C1A and C1B is regarded as the reset state, but a configuration may be used in which the charged state is regarded as the reset state and the capacitors C1A and C1B are charged by a constant current.

[0059] In addition, in the above embodiment 2, it has been described that adjustments can be made before the product is shipped, but it is also possible to provide an adjustment unit outside the oscillator circuit 200 that outputs an enable signal en based on changes in the oscillation signal fout and the power supply voltage VDD, thereby making it possible to make dynamic adjustments. [Explanation of symbols]

[0060] 100 Oscillator Circuit 10 RS Flip-Flop Circuit 13. NAND 14 NAND INV1A 1st inverter INV1B 2nd inverter C1A First Capacitor C1B Second capacitor I1A constant current source I2A constant current source I1B constant current source I2B constant current source MP1A Transistor MP1B Transistor MN1A Transistor MN1B Transistor MN2A Dummy Switch MN2B Dummy Switch MN3A Dummy Switch MN3B Dummy Switch

Claims

1. a first voltage comparator that receives a power supply voltage via a first constant current source, and outputs a first signal of logic level 0 when a potential input to the input terminal exceeds a threshold, and outputs a first signal of logic level 1 when the potential input to the input terminal is equal to or lower than the threshold; a second voltage comparator that receives a power supply voltage via a second constant current source, and outputs a second signal of logic level 0 when a potential input to the input terminal exceeds a threshold, and outputs a second signal of logic level 1 when the potential input to the input terminal is equal to or lower than the threshold; an RS flip-flop circuit that receives the first signal at a reset terminal and the second signal at a set terminal, and outputs a first oscillation signal and a second oscillation signal obtained by inverting the first oscillation signal based on the first signal and the second signal; A first capacitor having one end connected to a ground potential; a second capacitor having one end connected to ground potential; a first charging / discharging unit including a first transistor of a first conductivity type and a second transistor of a second conductivity type, the drains of which are connected to each other and to the other end of the first capacitor and an input end of the first voltage comparing unit via a first node, the first transistor and the second transistor being complementarily turned on and off in response to the first oscillation signal, and configured to charge and discharge the first capacitor based on the first oscillation signal; a second charging / discharging unit including a third transistor of a first conductivity type and a fourth transistor of a second conductivity type, the drains of which are connected to each other and to the other end of the second capacitor and an input end of the second voltage comparing unit via a second node, the third transistor and the fourth transistor being complementarily turned on and off in response to the second oscillation signal, and charging and discharging the second capacitor based on the second oscillation signal; a first dummy switch connected to the first node, controlled to be turned on and off in response to a signal level of the second oscillation signal, and adding a predetermined capacitance to the first node when in an on state; a second dummy switch that is provided at the second node and is controlled to be turned on and off in response to a signal level of the first oscillation signal, and that adds a predetermined capacitance to the second node when in an on state; 1. An oscillator circuit comprising:

2. the first dummy switch is composed of a second conductivity type transistor having a source and a drain connected to each other and connected to the first node, and having a gate to which the second oscillation signal is applied; 2. The oscillation circuit according to claim 1, wherein the second dummy switch is composed of a transistor of a second conductivity type having a source and a drain connected to each other and connected to the second node, and having a gate to which the first oscillation signal is applied.

3. the first dummy switch includes a plurality of transistors of a second conductivity type connected in cascade; the second dummy switch includes a plurality of transistors of a second conductivity type connected in cascade; Each of the plurality of transistors constituting the first dummy switch has a source and a drain connected to each other, and selectively receives an inverted signal of the first oscillation signal at a gate thereof; 2. The oscillation circuit according to claim 1, wherein each of the plurality of transistors constituting the second dummy switch has a source and a drain connected to each other, and selectively receives an inverted signal of the second oscillation signal at its gate.

4. a first NAND gate that supplies a logical product of a selection signal that selects one of the plurality of transistors that configure the first dummy switch and the first oscillation signal to the first dummy switch; a first NAND gate that supplies a logical product of a selection signal that selects one of the plurality of transistors that configure the second dummy switch and the second oscillation signal to the second dummy switch; 4. The oscillator circuit according to claim 3, further comprising:

5. the first voltage comparison unit is composed of a first inverter having an input terminal connected to the first node and configured to invert and output a comparison result obtained by comparing a potential of the first node with a threshold value; 5. The oscillator circuit according to claim 1, wherein the second voltage comparison unit is composed of a second inverter having an input terminal connected to the second node and inverting and outputting a comparison result obtained by comparing the potential of the second node with a threshold value.

6. the first charging / discharging unit receives a power supply voltage via a constant current source to a source of the first transistor, and supplies a current from the constant current source to the first capacitor via the first node to charge the first capacitor; 6. The oscillator circuit according to claim 1, wherein the second charging / discharging unit receives a power supply voltage via a constant current source to a source of the third transistor, and charges the second capacitor by supplying a current from the constant current source to the second capacitor via the second node.

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