Gate Drive Circuit

Abstract

To correct the temperature of a gate drive circuit in which an N-channel MOSFET and a P-channel MOSFET are push-pull connected.SOLUTION: In a gate drive circuit in which an N-channel MOSFET and a P-channel MOSFET are push-pull connected to amplify an input pulse signal and drive an output element, a temperature correction circuit that lowers each gate voltage of the N-channel MOSFET and the P-channel MOSFET as the ambient temperature increases is connected between the gate terminals of the N-channel MOSFET and the P-channel MOSFET.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a gate drive circuit that drives a power semiconductor element by connecting an N-channel MOSFET and a P-channel MOSFET in a push-pull manner. [Background technology]

[0002] As one of the drive circuits for driving power semiconductor elements such as power MOSFETs and IGBTs, a circuit in which an N-channel MOSFET and a P-channel MOSFET are connected in a push-pull manner, which is capable of low-loss and high-speed switching drive, is used (Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Utility Model Application Publication No. 05-048584 Summary of the Invention [Problem to be solved by the invention]

[0004] However, in the gate drive circuit as shown in Patent Document 1, the gate voltage is constant without temperature compensation, and therefore problems associated with temperature changes arise as described below.

[0005] 1) The turn-on delay time and turn-off delay time differ at low and high temperatures. This causes the responsiveness of the gate drive circuit to be temperature dependent.

[0006] 2) The time that the N-channel MOSFET and P-channel MOSFET are on simultaneously becomes longer, resulting in increased losses. In particular, when high-frequency switching is performed and the temperature of the elements rises, simultaneous on-states become more likely to occur, resulting in increased losses.

[0007] These problems are caused by the fact that the MOSFET threshold voltage changes with temperature (ambient temperature).

[0008] The present invention takes note of the fact that the threshold voltage of a MOSFET changes depending on temperature (ambient temperature), and aims to provide a gate drive circuit that changes the gate voltage in response to temperature (ambient temperature). [Means for solving the problem]

[0009] The gate drive circuit of the present invention is a gate drive circuit in which an N-channel MOSFET and a P-channel MOSFET are push-pull connected, and an input pulse signal is amplified to drive an output element, As the ambient temperature increases, The amplitude of the input pulse signal is reduced, and the input pulse signal having the reduced amplitude is P-channel MOSFET Input to the gate terminal of A temperature compensation circuit is connected.

[0010] The temperature compensation circuit includes a transistor having the gate terminals of the N-channel MOSFET and the P-channel MOSFET connected between the collector and emitter, and a thermistor circuit including a thermistor element connected between the base and emitter of the transistor.

[0011] According to the above configuration, the temperature compensation circuit TeP Channel MOSFET Reduce the amplitude of the input pulse signal to the gate. This makes it possible to reduce the difference in turn-on and turn-off delay times, which changes with temperature. In addition, the simultaneous on time of the N-channel MOSFET and P-channel MOSFET is not lengthened, preventing an increase in loss. Effect of the Invention

[0012] In the present invention, a current flows between the gate terminals of the N-channel MOSFET and the P-channel MOSFET as the ambient temperature increases. Before The P-channel MOSFET Reduce the amplitude of the input pulse signal to the gate. A temperature compensation circuit is connected to adjust the temperature as the temperature (ambient temperature) increases. TePChannel MOSFET The amplitude of the input pulse signal input to the gate of This makes it possible to reduce the difference in turn-on and turn-off delay times, which changes with temperature. In addition, the simultaneous on time of the N-channel MOSFET and P-channel MOSFET is not lengthened, preventing an increase in loss. This makes it possible to reduce losses that tend to occur at high temperatures during high-frequency switching in particular. [Brief description of the drawings]

[0013] [Figure 1] 1 is a schematic diagram of a power module circuit according to an embodiment of the present invention; [Diagram 2] FIG. 2 is a configuration diagram of a gate drive circuit 2. [Diagram 3] FIG. 2 is a circuit diagram of a temperature correction circuit 20. [Figure 4] The relationship between the ambient temperature (thermistor temperature) and the gate voltage V(GS) when the temperature compensation circuit 20 is provided is shown. [Diagram 5] The method for calculating the calculated value V1 is shown below. [Figure 6] 1A shows the turn-on and turn-off delay times of nMOSFET Q1 when the temperature compensation circuit 20 is not provided (FIG. 1A), and when the temperature compensation circuit 20 is provided (FIG. 1B). [Figure 7] 1A shows the loss in the nMOSFET Q1 and the pMOSFET Q2 when the temperature compensation circuit 20 is not provided, and FIG. 1B shows the loss in the nMOSFET Q1 and the pMOSFET Q2 when the temperature compensation circuit 20 is provided. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0014] Fig. 1 is a schematic diagram of a power module circuit according to an embodiment of the present invention. In Fig. 1, a control board 1 outputs a pulse signal to a gate drive circuit 2, which amplifies the pulse signal and supplies it to a power MOSFET element 3. The gate drive circuit 2 is the part according to the present invention.

[0015] FIG. 2 is a configuration diagram of the gate drive circuit 2.

[0016] The gate drive circuit 2 is configured by connecting an N-channel MOSFET (nMOSFET) Q1 and a P-channel MOSFET (pMOSFET) Q2 in series (push-pull). A temperature compensation circuit 20 is connected between the gate terminals (gate G) of Q1 and Q2. An input pulse signal from the control board 1 is input to the gate G of the nMOSFET Q1, and is input to the gate G of the pMOSFET Q2 via the temperature compensation circuit 20. The temperature compensation circuit 20 is a circuit that drops the output voltage of the input voltage as the ambient temperature rises. In other words, the temperature compensation circuit 20 increases the voltage as the ambient temperature rises. 、p MOSFET Q2 The amplitude of the input pulse signal input to the gate G is reduced by the amount of the drop.

[0017] FIG. 3 is a circuit diagram of the temperature correction circuit 20.

[0018] In this temperature compensation circuit 20, a thermistor circuit 200 is connected between the base and emitter of a transistor Q3. The thermistor circuit 200 is composed of resistors R2 and R3 connected in series, and a thermistor NTC connected in parallel to R3. R2 and R3 are used to adjust the temperature-voltage characteristics (negative characteristics) of the thermistor NTC. The collector emitter of the transistor Q3 is connected between the gates G of Q1 and Q2 via output terminals a and b, thereby ri, p The gate voltage V(GS) of the MOSFET Q2 is dropped. This drop voltage changes depending on the ambient temperature. In the following, the function and effect of the temperature correction circuit 20 will be described in the case where the temperature correction circuit 20 is also provided in the nMOSFET Q1.

[0019] FIG. 4 shows the relationship between the ambient temperature (thermistor temperature) and the gate voltage V(GS) when the temperature compensation circuit 20 is provided. The gate voltage threshold T of the nMOSFET Q1 and pMOSFET Q2 decreases as the ambient temperature (thermistor temperature) increases, due to the characteristics of the FET. On the other hand, it is desirable in design that the gate voltage V(GS) be approximately twice the threshold value. Therefore, the characteristics of R2, R3 and thermistor NTC in FIG. 3 are selected so that the gate voltage V(GS) will be approximately that value. The calculated value V1 of the gate voltage V(GS) in FIG. 3 is obtained as shown in FIG. 5.

[0020] Figure 5 shows the calculation method used to determine the calculated value V1. Due to the temperature characteristics of the NTC thermistor, I(R2) increases as the temperature increases. Therefore, as the temperature increases, the drop voltage V(DROP) increases and the gate voltage V(GS) decreases. As a result of the calculation shown in Figure 5, as shown in Figure 4, the calculated value V1 decreases as the temperature increases. Note that Figure 4 also shows the measured gate voltage value V2, and it can be seen that the calculated value V1 and the measured value V2 are almost the same.

[0021] As described above, by connecting the temperature compensation circuit 20 of the circuit in FIG. 3 as shown in FIG. 2, the gate voltage V(GS) can be reduced as shown in FIG. 4 in response to an increase in the ambient temperature (thermistor temperature).

[0022] Next, the operation of the temperature correction circuit 20 will be described with reference to FIGS.

[0023] FIG. 6A shows the turn-on and turn-off delay times of the nMOSFET Q1 when the temperature compensation circuit 20 is not provided, and FIG. 6B shows the turn-on and turn-off delay times of the nMOSFET Q1 when the temperature compensation circuit 20 is provided. show.

[0024] The pulse waveform (input pulse) shown on the upper side of Fig. 6(A) is the gate voltage V(GS), and the pulse waveform shown on the lower side is the drain-source voltage V(DS). In Fig. 6(A), due to its characteristics, the threshold value (voltage) (V(ThL)) at turn-on at low temperature and the threshold value (voltage) (V(ThH)) at turn-on at high temperature are different (V(ThL)>V(ThH)).

[0025] Therefore, as shown in the pulse waveform (V(DS) waveform) shown at the bottom of Figure 6(A), the turn-on delay time of the drain-source voltage V(DS) differs between low and high temperatures. In other words, the turn-on delay time DL1(L) at low temperature is greater than the turn-on delay time DL1(H) at high temperature. Similarly, at turn-off, the turn-off delay time DL2(L) at low temperature is less than the turn-off delay time DL2(H) at high temperature. The turn-on delay time and turn-off delay time are defined as the time during which the voltage is 10%-90% during the rising or falling edge of the pulse.

[0026] In addition, although FIG. 6A shows an nMOSFET Q1, the same applies to a pMOSFET Q2. teeth, The nMOSFET Q1 turns on during the off period, and similarly, a difference occurs between the turn-on delay time and the turn-off delay time depending on the temperature.

[0027] In FIG. 6B, as in FIG. 6A, the pulse waveform (input pulse) shown on the upper side is the gate voltage V(GS), and the pulse waveform shown on the lower side is the drain-source voltage V(DS). The pulse waveform shown on the upper side of FIG. 6B shows that the gate voltage V(GS) at low temperature is different from the gate voltage V(GS) at high temperature. This is due to the drop voltage V(DROP) by the temperature correction circuit 20. In other words, the gate voltage V(GS) at low temperature - the drop voltage V(DROP) = the gate voltage (GS) at high temperature. As a result, as shown in the waveform of the drain-source voltage V(DS) shown on the lower side of FIG. 6B, the turn-on delay time DL1(L) at low temperature = the turn-on delay time DL1(H) at high temperature. Also, the turn-off delay time DL2(L) at low temperature = the turn-off delay time DL2(H) at high temperature.

[0028] 6B shows the nMOSFET Q1, but the same is true for the pMOSFET Q2. The pMOSFET Q2 turns on during the interval in which the nMOSFET Q1 is off, and the turn-on delay time and the turn-off delay time are the same even if there is a change in temperature.

[0029] In this way, by providing the temperature compensation circuit 20, the temperature dependency of the MOSFET threshold can be cancelled, and the turn-on delay time and the turn-off delay time can be made the same regardless of the temperature.

[0030] FIG. 7A shows the losses in the nMOSFET Q1 and pMOSFET Q2 when the temperature compensation circuit 20 is not provided, and FIG. 7B shows the losses in the nMOSFET Q1 and pMOSFET Q2 when the temperature compensation circuit 20 is provided.

[0031] The pulse waveform (input pulse) shown at the top of Fig. 7(A) is the gate voltage V(GS) of nMOSFETQ1, and the pulse waveform (input pulse) shown at the bottom is the gate voltage V(GS) of pMOSFETQ2. In Fig. 7(A), the nMOSFETQ1 and pMOSFETQ2 have different threshold values ​​(voltage) (V(ThL)) at turn-on at low temperature and threshold values ​​(voltage) (V(ThH)) at turn-on at high temperature due to their characteristics (V(ThL)>V(ThH)). On the other hand, when nMOSFETQ1 turns on (when pMOSFETQ2 turns off), there are sections TON(H) and TON(L) where both nMOSFETQ1 and pMOSFETQ2 are simultaneously on. Also, when nMOSFETQ1 turns off (when pMOSFETQ2 turns on), there are sections TOFF(H) and TOFF(L) where both are simultaneously on. In these sections TON(H), TON(L) and TOFF(H), TOFF(L), short-circuit current flows through the two nMOSFETs Q1 and pMOSFET Q2, causing (thermal) losses. These losses are particularly large when the switching frequency is high.

[0032] As in Fig. 7(A), the pulse waveform (input pulse) shown on the upper side of Fig. 7(B) is the gate voltage V(GS) of nMOSFET Q1, and the pulse waveform (input pulse) shown on the lower side is the gate voltage V(GS) of pMOSFET Q2. The pulse waveform shown on the upper side of Fig. 7(B) shows that the gate voltage V(GS) drops by the drop voltage V(DROP) of the temperature compensation circuit 20 when nMOSFET Q1 is on. The pulse waveform shown on the lower side of Fig. 7(B) shows that the gate voltage V(GS) drops by the drop voltage V(DROP) of the temperature compensation circuit 20 when pMOSFET Q2 is on.

[0033] From Fig. 7(B), it can be seen that the intervals TON(H) and TON(L) during which both are simultaneously on when nMOSFETQ1 is turned on (when pMOSFETQ2 is turned off) are shorter than those in Fig. 7(A). It can also be seen that the intervals TOFF(H) and TOFF(L) during which both are simultaneously on when nMOSFETQ1 is turned off (when pMOSFETQ2 is turned on) are also shorter than those in Fig. 7(A).

[0034] In this manner, by providing the temperature compensation circuit 20, it is possible to reduce losses at the time of turn-on and turn-off due to the temperature dependency of the threshold voltage of the MOSFET.

[0035] As described above, according to this embodiment, the difference in the turn-on and turn-off delay times of the N-channel MOSFET and the P-channel MOSFET can be reduced by providing the temperature compensation circuit 20. In addition, the simultaneous on time of the N-channel MOSFET and the P-channel MOSFET is not lengthened, and an increase in loss can be prevented. [Explanation of symbols]

[0036] 20-Temperature compensation circuit Q1 - N-channel MOSFET Q2 - P-channel MOSFET

Claims

1. In a gate drive circuit in which an N-channel MOSFET and a P-channel MOSFET are push-pull connected and an input pulse signal is amplified to drive an output element, A gate drive circuit in which a temperature compensation circuit is connected between the gate terminals of the N-channel MOSFET and the P-channel MOSFET, the temperature compensation circuit reducing the amplitude of the input pulse signal as the ambient temperature increases, and inputting the input pulse signal with the reduced amplitude to the gate terminal of the P-channel MOSFET.

2. 2. The gate drive circuit according to claim 1, wherein the temperature compensation circuit includes a transistor having gate terminals of the N-channel MOSFET and the P-channel MOSFET connected between a collector and an emitter, and a thermistor circuit including a thermistor element connected between a base and an emitter of the transistor.

3. 3. The gate drive circuit according to claim 2, wherein said thermistor circuit is composed of resistors R2 and R3 connected in series, and a thermistor NTC connected in parallel to said resistor R3.

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