Semiconductor integrated circuit and control method for semiconductor integrated circuit

Abstract

To reduce occurrence of noise and shift a block from a power interruption state to a power supply state.SOLUTION: A semiconductor integrated circuit includes: multiple blocks that can be shifted from a power interruption state to a power supply state, respectively; a request part for issuing a power supply request for requesting a shift from the power interruption state of the blocks to the power supply state for each block; an arbitration part for arbitrating multiple power supply requests when there are the multiple power supply requests, and issuing permission to the power supply requests; and multiple shift processing parts that can perform a process for shifting the multiple blocks from the power interruption state to the power supply state, and perform a process for shifting from the power interruption state to the power supply state to a block to which a permission to the power supply requests is issued. The request part issues the power supply requests regardless of a state of a block to which the power supply requests are not issued.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor integrated circuit and a method for controlling the semiconductor integrated circuit. [Background technology]

[0002] In recent years, the performance and functionality of mobile devices such as digital cameras and smartphones have improved, leading to an increase in the power consumption of LSIs, making power reduction measures an urgent necessity. Power consumption is classified into dynamic power and leakage power. Dynamic power is the power consumed while a circuit is operating. Leakage power is the power consumed constantly when the power is on, regardless of whether the circuit is operating or not.

[0003] A typical method for reducing dynamic power is "clock gating." Clock gating allows the clock to transition from an operating state to a blocked state, or from a blocked state to an operating state, in one to a few clock cycles, and is known as a power reduction measure that can be implemented relatively easily.

[0004] On the other hand, a typical method for reducing leakage power is "power shutdown," in which each functional block that realizes each function of a semiconductor integrated circuit system is divided into power-off blocks, and power to each functional block is shut off during periods when the function that the functional block is responsible for is not in use.

[0005] Unlike the clock shutdown that is a dynamic power reduction measure, this "power shutdown" requires control of signals such as power switch control, clock control, reset control, and isolation control when transitioning to the power shutdown state and when returning from the power shutdown state. This power shutdown transition sequence and power restoration transition sequence are necessary to suppress the impact on surrounding blocks that are not powered down, and to prevent the functional block to be powered down from resuming processing from an unstable state.

[0006] It is generally known that it takes tens to hundreds of microseconds to recover from a power-off state, depending on the circuit scale, with most of that time being spent controlling the power switch. If the power-off block needs to perform some processing after the power-off state has been reached, the disadvantage is that it cannot begin processing until it has waited for this recovery time of tens to hundreds of microseconds. Another disadvantage is that when the power switch for the power-off block is turned on, a large inrush current flows, generating noise on the power line and causing circuits on the same power line to malfunction.

[0007] In Patent Document 1, which focuses on this issue, the control method for the power switches is switched depending on the on / off state of the power cutoff block adjacent to the power cutoff block to be controlled. When the adjacent power cutoff block is in the on state, two types of power switches are switched in two time-shifted stages, thereby reducing the probability of noise generation on the power line. When the adjacent block is in the off state, these two types of power switches are switched simultaneously. This makes it possible to shorten the time it takes to transition from the power cutoff state to the recovery state and reduce the probability of noise generation at the same time. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] Japanese Patent Application Laid-Open No. 2012-48562 Summary of the Invention [Problem to be solved by the invention]

[0009] With the growing demand for power saving, especially in battery-powered products, the number of power-off blocks inside LSIs is steadily increasing, and there is a demand for finer-grained control of power-off and recovery in terms of space and time. In this regard, Patent Document 1 relates to a method of controlling two types of power switches for one power-off block, and does not mention simultaneous control of multiple power-off blocks.

[0010] An object of the present disclosure is to enable a block to transition from a powered-off state to a powered-on state while reducing noise generation. [Means for solving the problem]

[0011] The semiconductor integrated circuit includes a plurality of blocks each capable of transitioning from a power-off state to a power-supply state, a request unit that issues a power supply request for each block, requesting that the block transition from the power-off state to the power-supply state, an arbitration unit that, when there are a plurality of power supply requests, arbitrates the plurality of power supply requests and issues a permission for the power supply request, and a plurality of transition processing units that are capable of performing processing for transitioning each of the plurality of blocks from the power-off state to the power-supply state and that performs processing for transitioning a block for which a permission for the power supply request has been issued, from the power-off state to the power-supply state. have do. [Effects of the Invention]

[0012] According to the present disclosure, it is possible to transition a block from a power-off state to a power-supply state while reducing the generation of noise. [Brief explanation of the drawings]

[0013] [Figure 1] FIG. 1 illustrates an example of the configuration of an information processing device. [Figure 2] FIG. 2 illustrates an example of the configuration of a return control unit. [Figure 3] 10 is a timing chart showing the operating state within the subsystem. [Figure 4] FIG. 10 is a diagram showing a sequence of transitioning from a power-off state to a restored state. [Figure 5] FIG. 10 is a diagram showing a sequence for transitioning to a power-off state. [Figure 6] FIG. [Figure 7] FIG. 2 is a diagram showing the number of power switches in each block. [Figure 8] 10 is a flowchart illustrating arbitration. [Figure 9] 10 is a timing chart of arbitration regarding a plurality of power restoration requests. [Figure 10] FIG. 1 illustrates an example of the configuration of an information processing device. [Figure 11] 10 is a timing chart showing the operating state within the subsystem. [Figure 12] 10 is a timing chart relating to a power recovery period reservation. [Figure 13] 10 is a timing chart relating to a power recovery period reservation. DETAILED DESCRIPTION OF THE INVENTION

[0014] Hereinafter, embodiments will be described with reference to the drawings. Note that the following embodiments are merely examples and do not limit the scope of the present disclosure.

[0015] (First embodiment) 1 is a block diagram showing an example of the configuration of an information processing device 1 according to a first embodiment. The information processing device 1 is, for example, an information processing device for a digital camera system, and is a semiconductor integrated circuit known as a system-on-chip. The information processing device 1 has a main CPU 2, a clock reset control unit 3, an arbitration unit 4, a subsystem 5, and a subsystem 6.

[0016] The components inside the information processing device 1 are interconnected by a bus system (not shown). This bus system is generally called an interconnect, a fabric, an on-chip network, or a network-on-chip. A main CPU 2 that performs overall processing of the information processing device 1 is connected to the bus system. The information processing device 1 receives video data from an external sensor (not shown), writes the video data to a DRAM (not shown) via the bus system, and transfers the video data stored in the DRAM to an external video display unit (not shown). The information processing device 1 also processes the video data stored in the DRAM and writes the processed video data back to the DRAM. Subsystem 5 and subsystem 6 each transfer video data to an external video display unit and process the video data.

[0017] The information processing device 1 has a clock reset control unit 3 that supplies a clock signal and a reset signal to subsystems 5 and 6. The clock reset control unit 3 supplies a clock signal 41 and a reset signal 42 to subsystem 5. Similarly, the clock reset control unit 3 supplies a clock signal of subsystem 6 and a reset signal of subsystem 6 to subsystem 6. The arbitration unit 4 arbitrates power restoration requests notified from subsystem 5 and subsystem 6.

[0018] Next, the internal configuration of subsystems 5 and 6 will be explained. The configuration of subsystem 5 will be explained below, but subsystem 6 has a similar configuration. Subsystem 5 has a sub-CPU 11, recovery control units 12a and 12b, and blocks 13a and 13b. Sub-CPU 11 performs internal processing for subsystem 5. Blocks 13a and 13b are functional blocks that each handle some of the processing of the functions handled by subsystem 5. Furthermore, blocks 13a and 13b are also power-off blocks that are subject to power-off, and can be individually restored after power-off. Here, power supply voltage is supplied to blocks 13a and 13b of subsystem 5, and further to blocks 13a and 13b of subsystem 6, from the same power line.

[0019] The recovery control unit 12a controls the transition of block 13a to a power-off state and a power-restored state. Similarly, the recovery control unit 12b controls the transition of block 13b to a power-off state and a power-restored state. When transitioning to a power-off state or a power-restored state, the recovery control units 12a and 12b each need to control a power switch on / off request signal, a power switch on / off permission signal, an isolation control signal, a reset signal, and a clock signal. The actual control procedure will be described later.

[0020] The recovery control unit 12a outputs a power switch on / off request signal 25a to the block 13a. The recovery control unit 12a inputs a power switch on / off permission signal 26a from the block 13a. The recovery control unit 12a outputs a clock signal 27a to the block 13a. The recovery control unit 12a outputs a reset signal 28a to the block 13a. The recovery control unit 12a outputs an isolation control signal 29a to the block 13a.

[0021] The recovery control unit 12b outputs a power switch on / off request signal 25b to the block 13b. The recovery control unit 12b inputs a power switch on / off permission signal 26b from the block 13b. The recovery control unit 12b outputs a clock signal 27b to the block 13b. The recovery control unit 12b outputs a reset signal 28b to the block 13b. The recovery control unit 12b outputs an isolation control signal 29b to the block 13b.

[0022] When starting the power restoration process for block 13a, sub CPU 11 outputs power restoration request 22a to arbitration unit 4. When starting the power restoration process for block 13b, sub CPU 11 outputs power restoration request 22b to arbitration unit 4. Arbitration unit 4 arbitrates the multiple power restoration requests 22a and 22b. Arbitration unit 4 outputs power restoration permission 23a to restoration control unit 12a. Arbitration unit 4 also outputs power restoration permission 23b to restoration control unit 12b.

[0023] The arbitration unit 4 receives an operating state notification 21 from the sub-CPU 11 and a clock frequency notification 36 from the clock reset control unit 3. The arbitration unit 4 determines a threshold for the number of power switches that may simultaneously perform power restoration processing, and allows multiple power restoration requests simultaneously as long as the threshold is not exceeded. The threshold is determined using the operating state notification 21, the operating state and operating frequency information within the subsystem notified by the clock frequency notification 36, the number of power switches in each of the blocks 13a and 13b, and the voltage value being supplied. The method for determining the threshold will be described in detail later.

[0024] When power restoration permission 23a is input from the arbitration unit 4, the restoration control unit 12a executes a process of transitioning the block 13a to the power restoration state. Then, when the process of transitioning to the power restoration state is completed, the restoration control unit 12a outputs a power restoration completion notification 24a to the sub CPU 11.

[0025] The restoration control unit 12b executes a process of transitioning the block 13b to a power restoration state when the power restoration permission 23b is input from the arbitration unit 4. Then, the restoration control unit 12b outputs a power restoration completion notification 24b to the sub CPU 11 when the process of transitioning to the power restoration state is completed.

[0026] The sub CPU 11 receives the power restoration completion notification 24a, and when it is ready to start normal processing, asserts the block activation 30a to the block 13a. When the block activation 30a is asserted, the block 13a starts normal processing.

[0027] The sub CPU 11 receives the power restoration completion notification 24b, and when it is ready to start normal processing, asserts the block activation 30b to the block 13b. When the block activation 30b is asserted, the block 13b starts normal processing.

[0028] When the block 13a completes the normal processing, it outputs an end interrupt 31a to the sub CPU 11. When the end interrupt 31a is input, the sub CPU 11 executes a power cut-off process for the block 13a.

[0029] When the block 13b completes the normal processing, it outputs an end interrupt 31b to the sub CPU 11. When the end interrupt 31b is input, the sub CPU 11 executes a power cut-off process for the block 13b.

[0030] When starting the power-off process for the block 13a, the sub-CPU 11 outputs a power-off request for the block 13a (not shown) to the restoration control unit 12a. Upon receiving this power-off request, the restoration control unit 12a executes a transition process for the block 13a to a power-off state.

[0031] When starting the power-off process for the block 13b, the sub-CPU 11 outputs a power-off request for the block 13b (not shown) to the restoration control unit 12b. Upon receiving this power-off request, the restoration control unit 12b executes a transition process for the block 13b to a power-off state.

[0032] Fig. 2 is a diagram showing an example of the configuration of the recovery control unit 12a in Fig. 1. The recovery control unit 12b has the same configuration as the recovery control unit 12a. The recovery control unit 12a has a power switch control unit 32, a clock control unit 33, a reset control unit 34, an isolation control unit 35, and an overall control unit 37.

[0033] The overall control unit 37 starts the power restoration transition sequence when it receives a power restoration permission 23a from the arbitration unit 4. The overall control unit 37 also starts the power shutdown transition sequence when it receives a power shutdown request (not shown) from the sub CPU 11. The overall control unit 37 cooperates with the power switch control unit 32, clock control unit 33, reset control unit 34, and isolation control unit 35 to execute the power restoration transition sequence and the power shutdown transition sequence, which will be described later with reference to FIGS. 4 and 5.

[0034] When the power switch control unit 32 is notified by the overall control unit 37 to start power switch control, it controls the power switch on / off request signal 25a. In this embodiment, a high level of the power switch on / off request signal 25a indicates a request to turn the power switch on, and a low level of the power switch on / off request signal 25a indicates a request to turn the power switch off. When the power switch control unit 32 is notified by the power switch on / off permission signal 26a that the power switch has been turned on / off, it notifies the overall control unit 37 of completion.

[0035] The clock control unit 33 passes the clock signal 41 and outputs it to the block 13a as the clock signal 27a. While the clock cutoff signal output by the overall control unit 37 is valid, the clock control unit 33 does not pass the clock signal 41 and cuts off the supply of the clock signal 27a.

[0036] The reset control unit 34 passes the reset signal 42 and outputs it to the block 13a as the reset signal 28a. During the period in which the forced reset signal output by the overall control unit 37 is valid, the reset control unit 34 enables the reset signal 28a and outputs it to the block 13a, regardless of the valid / invalid state of the reset signal 42.

[0037] When the isolation control unit 35 is notified by the overall control unit 37 to start isolation control, it controls the isolation control signal 29a.

[0038] Fig. 3 is a timing chart showing an example of processing by the recovery control unit 12a in the subsystem 5. Below, a power recovery request in the subsystem 5 and transitions in the operating state in the subsystem 5 will be explained using the timing chart in Fig. 3. An example of processing by the recovery control unit 12a will be explained, but the processing by the recovery control unit 12b is similar.

[0039] At time T1, all blocks 13a and 13b in subsystem 5 are in a power-off state. Therefore, operation status notification 21 indicates "power off." Here, for ease of explanation, operation status notification 21 indicates only the operation status of block 13a that is the target of power restoration processing, but in reality, it indicates the operation status of all blocks 13a and 13b in subsystem 5 individually. At time T1, sub-CPU 11 asserts power restoration request 22a and outputs power restoration request 22a to arbitration unit 4.

[0040] At time T2, when the arbitration unit 4 determines that it is in a state where permission can be issued for the power restoration request 22a, it asserts the power restoration permission 23a. Here, the power restoration request 22a and the power restoration permission 23a are high-level active, which means that the assertion is at a high level.

[0041] At time T3, when power restoration permission 23a is asserted, sub CPU 11 lowers (deasserts) power restoration request 22a to low level. Also, when power restoration permission 23a is asserted, restoration control unit 12a sets power switch on / off request signal 25a to high level. Here, a high level of switch on / off request signal 25a and switch on / off permission signal 26a means power restoration, and a low level means power shutdown. Since the transition process to the power restoration state has started, operating state notification 21 indicates "power on transition."

[0042] At time T4, the arbitration unit 4 deasserts the power restoration permission 23a because the power restoration request 22a has been deasserted.

[0043] At time T5, the block 13a sets the power switch on / off request signal 25a to high level, and then sets the power switch on / off permission signal 26a to high level. This indicates that all the power switches in the block 13a are in the on state and the power has returned to the power supply state. The operation state notification 21 indicates "idle."

[0044] At time T6, the sub CPU 11 asserts the block activation signal 30a. Then, the block 13a starts to operate to execute a predetermined process. When the block 13a is in the operating period, the operating state notification 21 indicates "operating."

[0045] At time T7, the block 13a completes the predetermined processing and asserts the end interrupt 31a. The operation state notification 21 indicates "idle." After time T7, the recovery control unit 12a may execute a sequence for transitioning to a power-off state.

[0046] 4 is a flowchart showing the power restoration transition sequence of the restoration control unit 12a. The power restoration sequence of the restoration control unit 12b is similar.

[0047] In step S0, when the power restoration transition sequence of the restoration control unit 12a starts, the block 13a is in a power-off state (power is cut off) and no power supply voltage is supplied, and further, the clock signal 27a is stopped and the isolation control signal 29a is in a valid state.

[0048] In step S1, when the overall control unit 37 is notified of the power restoration permission 23a, it regards this as a request for processing to transition to the power restoration state. Then, under the control of the overall control unit 37, the power switch control unit 32 sets the power switch on / off request signal 25a to high level. Then, the block 13a turns on the power switches, and the supply of power voltage begins. When all the power switches are on, the block 13a sets the power switch on / off permission signal 26a to high level.

[0049] In step S2, the power switch control unit 32 sets the power switch on / off request signal 25a to high level, and then waits until the power switch on / off permission signal 26a becomes high level. When the power switch on / off permission signal 26a becomes high level, the process proceeds to step S3.

[0050] In step S3, the reset control unit 34 releases (deactivates) the reset signal 28a, and in step S4, the isolation control unit 35 deactivates the isolation control signal 29a.

[0051] In step S5, the overall control unit 37 disables the clock cutoff signal. Then, the clock control unit 33 outputs the clock signal 41 as the clock signal 27a and starts supplying the clock signal 27a. Note that before step S5, the clock signal 27a is in a cutoff state.

[0052] In step S6, the overall control unit 37 determines that the transition to the power restoration state has been completed and asserts the power restoration completion notification 24a.

[0053] In step S7, the overall control unit 37 completes the power restoration transition sequence for the block 13a, and the block 13a enters a state in which normal processing is possible.

[0054] 5 is a flowchart showing the power-off transition sequence of the recovery control unit 12a. The power-off transition sequence of the recovery control unit 12b is also similar.

[0055] In step S7, when the power-off transition sequence of the recovery control unit 12a starts, the block 13a is in a power-on state, the power supply voltage is being supplied, the clock signal 27a is being supplied, and the isolation control signal 29a is in an invalid state.

[0056] In step S11, when the overall control unit 37 receives a power-off request (not shown), it starts a power-off transition sequence and first enables the clock-off signal, which causes the clock control unit 33 to cut off the supply of the clock signal 27a.

[0057] In step S12, the isolation control unit 35 enables the isolation control signal 29a under the control of the overall control unit 37. In step S13, the reset control unit 34 enables the reset signal 28a under the control of the overall control unit 37. This causes the block 13a to enter a reset state.

[0058] In step S14, the power switch control unit 32, under the control of the overall control unit 37, sets the power switch on / off request signal 25a to the block 13a to low level. Then, the block 13a turns off the power switches, and the supply of power voltage is cut off. When all the power switches are turned off, the block 13a sets the power switch on / off permission signal 26a to low level.

[0059] In step S15, the power switch control unit 32 waits until the power switch on / off permission signal 26a goes to low level. When the power switch on / off permission signal 26a goes to low level, the process proceeds to step S16.

[0060] In step S16, the overall control unit 37 notifies the sub-CPU 11 of the completion of power-off by issuing a power-off completion notification (not shown).

[0061] In step S0, the overall control unit 37 completes the power-off transition sequence for the block 13a, and the block 13a enters a state in which the supply of power supply voltage is cut off.

[0062] The sequences described in Figures 4 and 5 are just examples, and the order of execution of each step may be changed or skipped as long as power restoration and power shutdown can be achieved without destabilizing the circuit operation.

[0063] FIG. 6 shows a lookup table of thresholds used by the arbitration unit 4 when arbitrating between the power restoration requests 22a and 22b. If a block 13a or 13b exists whose operating state notification 21 indicates "operating," the threshold is determined based on the power supply voltage and operating frequency supplied to the block 13a or 13b. This lookup table indicates that if the power supply voltage is 1.05V and the operating frequency is 400MHz, the threshold is set to 60. If the operating frequencies of the blocks 13a and 13b are different, the strictest threshold is set. For example, if the block 13a has a power supply voltage of 1.05V and an operating frequency of 400MHz, and the block 13b has a power supply voltage of 1.05V and an operating frequency of 100MHz, the stricter (smaller) threshold value of 60 is selected. The arbitration unit 4 stores the lookup table shown in FIG. 6. The lookup table shown in FIG. 6 can be rewritten after chip startup, like a register.

[0064] FIG. 7 is a diagram showing the number of power switches and operating frequencies of blocks 13a and 13b of subsystems 5 and 6. Block 13a of subsystem 5 has 50 power switches and an operating frequency of 200 MHz. The other blocks have the same number of power switches and operating frequencies as shown in FIG. 7. The arbitration unit 4 holds the information shown in FIG. 7. Like a register, the information in FIG. 7 can be rewritten after chip startup. The operating frequency information is notified from the clock reset control unit 3 to the arbitration unit 4 by a clock frequency notification 36.

[0065] FIG. 8 is a flowchart showing a method for determining a threshold value used when the arbitration unit 4 arbitrates the power restoration requests 22a and 22b.

[0066] In step S31, the arbitration unit 4 determines whether all of the surrounding blocks 13a and 13b connected to the same power line are "powered off." Information is notified to the arbitration unit 4 from the sub-CPUs 11 of the subsystems 5 and 6 via the operation status notification 21. Here, the surrounding blocks may be all blocks connected to the same power line, or may be only blocks located close to the block for which the power restoration request is made in terms of layout. The arbitration unit 4 changes the blocks for which the threshold is determined to suit the system.

[0067] If all of the surrounding blocks 13a and 13b connected to the same power line are "powered off," the arbitration unit 4 proceeds to step S32. If any of the surrounding blocks 13a and 13b connected to the same power line are not "powered off," the arbitration unit 4 proceeds to step S33.

[0068] In step S32, the arbitration unit 4 sets the threshold to infinity because it will not malfunction even if noise is carried on the power supply line due to an inrush current.

[0069] In step S33, the arbitration unit 4 determines whether all of the blocks that are not "powered off" are "powered on" or "idle." If all of the blocks that are not "powered off" are "powered on" or "idle," the arbitration unit 4 proceeds to step S34. If any of the blocks that are not "powered off" are "operating," the arbitration unit 4 proceeds to step S35.

[0070] In step S34, the arbitration unit 4 sets a relatively large threshold value because there is no risk of data being lost even if a voltage drop occurs due to noise on the power supply line, since data is not being exchanged within or between blocks. This threshold value is a predetermined value, and may be hardwired into the circuit as a fixed value, or may be configured in a register so that it can be rewritten after chip startup.

[0071] In step S35, the arbitration unit 4 selects the highest operating frequency among the operating frequencies of the "active" blocks, and sets a threshold based on the selected operating frequency according to the lookup table of FIG.

[0072] The arbitration unit 4 can perform arbitration using an appropriate threshold value at all times by dynamically updating the threshold value according to the flowchart of FIG.

[0073] 9 is a timing chart showing an example of a control method for the information processing device 1. Below, we will explain the operation of arbitration regarding multiple power recovery requests 22a and 22b, based on blocks 13a and 13b in subsystem 5 and blocks 13a and 13b in subsystem 6. Here, the power supply voltage is 1.05V.

[0074] Time T10 is the initial state. At time T10, blocks 13a and 13b in subsystem 5 and blocks 13a and 13b in subsystem 6 are in the "power off" state, as indicated by operation state notification 21. Therefore, the threshold is set to infinity. The power switch count addition value is the sum of the power switch counts of all blocks 13a and 13b for which power restoration requests 22a and 22b have occurred or for which power restoration processing is being performed. At time T10, the power switch count addition value is 0.

[0075] At time T11, the sub-CPU 11 of the subsystem 5 notifies the arbitration unit 4 of a power restoration request 22a for performing power restoration processing for the block 13a of the subsystem 5 and a power restoration request 22b for performing power restoration processing for the block 13b of the subsystem 5. As shown in FIG. 7, the block 13a of the subsystem 5 has 50 power switches. The block 13b of the subsystem 5 has 30 power switches. Therefore, the sum of the number of power switches is 50 + 30 = 80.

[0076] At time T12, since the power switch count addition value (=80) is less than or equal to the threshold value (=infinity), the arbitration unit 4 notifies the recovery control unit 12a of the subsystem 5 and the recovery control unit 12b of the subsystem 5 of power recovery permission 23a and 23b, respectively. Upon receiving the notification of power recovery permission 23a, the recovery control unit 12a of the subsystem 5 executes the power recovery transition sequence (Figure 4) for block 13a of the subsystem 5. Upon receiving the notification of power recovery permission 23b, the recovery control unit 12b of the subsystem 5 executes the power recovery transition sequence (Figure 4) for block 13b of the subsystem 5. The sub-CPU 11 of the subsystem 5 outputs an operating status notification 21 to the arbitration unit 4. The operating status notification 21 indicates that the block 13a of the subsystem 5 and the block 13b of the subsystem 5 are in the "power on transition" state.

[0077] The arbitration unit 4 is notified of the "power-on transition" state, and therefore updates the threshold value according to the flowchart in Fig. 8. Since block 13a of subsystem 5 and block 13b of subsystem 5 are in the "power-on transition" state, the arbitration unit 4 sets the threshold value to 100 in step S34.

[0078] At time T13, the sub-CPU 11 of the subsystem 6 notifies the arbitration unit 4 of a power restoration request 22a to perform power restoration processing for the block 13a of the subsystem 6. As shown in FIG. 7, the block 13a of the subsystem 6 has 40 power switches. Therefore, the power switch count addition value is 50+30+40=120. Because the power switch count addition value (=120) is greater than the threshold value (=100), the arbitration unit 4 does not notify the restoration control unit 12a of the subsystem 6 of power restoration permission 23a. The restoration control unit 12a of the subsystem 6 enters a waiting state for power restoration permission 23a.

[0079] At time T14, the restoration control unit 12a of subsystem 5 completes the power restoration process for block 13a of subsystem 5. Then, the power switch count addition value, which is the sum of the number of power switches in block 13b of subsystem 5 and block 13a of subsystem 6, decreases to 30 + 40 = 70. The operating status notification 21 indicates that block 13a of subsystem 5 is in the "idle" state.

[0080] At time T15, the arbitration unit 4 notifies the recovery control unit 12a of the subsystem 6 of power recovery permission 23a because the power switch count addition value (=70) is less than or equal to the threshold value (=100). Upon receiving the notification of power recovery permission 23a, the recovery control unit 12a of the subsystem 6 executes the power recovery transition sequence (Figure 4) of the block 13a of the subsystem 6. The sub-CPU 11 of the subsystem 6 outputs an operating state notification 21 to the arbitration unit 4. The operating state notification 21 indicates that the block 13a of the subsystem 6 is in the "power on transition" state.

[0081] At time T16, the restoration control unit 12b of subsystem 5 completes the power restoration process for block 13b of subsystem 5. Then, the power switch count addition value, which is the number of power switches in block 13a of subsystem 6, decreases to 40. The operating status notification 21 indicates that block 13b of subsystem 5 is in the "idle" state.

[0082] At time T17, block 13a of subsystem 5 starts normal processing. Then, operation state notification 21 indicates that block 13a of subsystem 5 is in the "operating" state. According to the flowchart of FIG. 8, since block 13a of subsystem 5 is "operating", arbitration unit 4 executes step S35. The operating frequency of block 13a of subsystem 5 is 200 MHz. According to the lookup table of FIG. 6, since the power supply voltage is 1.05 V and the operating frequency is 200 MHz, arbitration unit 4 sets the threshold to 70.

[0083] At time T18, block 13b of subsystem 5 starts normal processing. Then, operation state notification 21 indicates that block 13b of subsystem 5 is in the "operating" state. According to the flowchart of FIG. 8, since blocks 13a and 13b of subsystem 5 are "operating," arbitration unit 4 executes step S35. The operating frequency of block 13a of subsystem 5 is 200 MHz, and the operating frequency of block 13b of subsystem 5 is 400 MHz. The highest operating frequency of these two operating frequencies is 400 MHz. According to the lookup table of FIG. 6, arbitration unit 4 sets the threshold to 60 because the power supply voltage is 1.05 V and the highest operating frequency is 400 MHz.

[0084] At time T19, the restoration control unit 12a of the subsystem 6 completes the power restoration process for the block 13a of the subsystem 6. Then, the power switch count addition value becomes 0 because there are no blocks 13a, 13b for which a power restoration request 22a, 22b has occurred or for which the power restoration process is being executed. The operating status notification 21 indicates that the block 13a of the subsystem 6 is in the "idle" state.

[0085] Although the arbitration unit 4 performs arbitration within a range in which the sum of the number of power switches is equal to or less than a threshold value, the present invention is not limited to this. When the arbitration unit 4 cannot notify power restoration permission 23a, 23b in response to a power restoration request, it may instruct the clock reset control unit 3 to lower the operating frequency of "operating" blocks 13a, 13b, raise the threshold value, and notify power restoration permission 23a, 23b. In this case, after the power restoration process is completed, the arbitration unit 4 controls the clock reset control unit 3 to restore the operating frequency of blocks 13a, 13b whose operating frequency has been lowered.

[0086] In addition, if there is a possibility that the sum of the number of power switches during the power restoration process may exceed a threshold value if blocks 13a and 13b in the "idle" state become "operating," the arbitration unit 4 may wait for the blocks to become "operating."

[0087] In this embodiment, the power restoration requests 22a, 22b are arbitrated in the order in which they are generated, but this is not limiting. The arbitration unit 4 may assign a priority to each of the blocks 13a, 13b and preferentially select a power restoration request for the block 13a, 13b with the highest priority. Furthermore, if there is a dependency between multiple blocks 13a, 13b in the same subsystem 5, 6, such that power restoration is required simultaneously or consecutively, the arbitration unit 4 may arbitrate a series of power restoration requests for those blocks collectively.

[0088] According to this embodiment, the arbitration unit 4 collectively manages all power restoration requests 22a, 22b for power restoration control for multiple blocks 13a, 13b, and arbitrates within a range in which the sum of the number of power switches does not exceed a threshold. This arbitration allows the information processing device 1 to reduce the risk of noise generation on the power line due to a large inrush current when multiple power switches are turned on simultaneously. Furthermore, by dynamically adjusting the threshold, the arbitration unit 4 can simultaneously execute power restoration processing for multiple blocks 13a, 13b within a range in which the risk of noise generation on the power line can be reduced.

[0089] (Second embodiment) Fig. 10 is a diagram showing an example of the configuration of an information processing device 1 according to the second embodiment. The information processing device 1 of Fig. 10 differs from the information processing device 1 of Fig. 1 in the signals input and output between the arbitration unit 4, the sub-CPU 11, and the recovery control units 12a and 12b. The following describes the differences between the second embodiment and the first embodiment. Subsystem 5 will be used as an example for explanation, but subsystem 6 also has a similar configuration to subsystem 5.

[0090] The arbitration unit 4 does not input the power restoration requests 22a and 22b and the operating state notification 21 in Fig. 1 to the sub CPU 11, and does not output the power restoration permissions 23a and 23b in Fig. 1. In addition, the arbitration unit 4 does not output the power restoration permissions 23a and 23b in Fig. 1 to the restoration control units 12a and 12b.

[0091] Before performing power-off processing on block 13a or 13b in subsystem 5, sub-CPU 11 reserves a power-on period by sending a power-on period reservation request 60 for subsystem 5 to arbitration unit 4. Here, the power-on period refers to the period until the power-on transition sequence is executed for all desired blocks 13a and 13b that are in a power-off state and they are ready for normal processing.

[0092] The sub-CPU 11 notifies the arbitration unit 4 of the maximum number of power switches among the blocks 13a and 13b that are the targets of the power restoration process, as the number of power restoration switches 61 for the subsystem 5, along with the power restoration period reservation request 60 for the subsystem 5. The arbitration unit 4 notifies the sub-CPU 11 of whether to grant or deny the power restoration period reservation request 60 using the power restoration period reservation permission 62 for the subsystem 5.

[0093] If the power recovery period reservation request 60 is permitted, the recovery control units 12a and 12b perform power cut-off processing for the blocks 13a and 13b under the control of the sub-CPU 11. The power cut-off processing is the same as in the first embodiment. If the power recovery period reservation request 60 is rejected, the recovery control units 12a and 12b may not perform power cut-off processing for the blocks and may abandon the power cut-off processing itself, or the sub-CPU 11 may shift the power recovery period and issue the power recovery period reservation request 60 again.

[0094] The sub-CPU 11 controls the restoration control units 12a and 12b to start the power restoration process when the reserved power restoration period arrives. The sub-CPU 11 instructs the restoration control unit 12a to execute the power restoration transition sequence for the block 13a by a power restoration request 70. Similarly, the sub-CPU 11 instructs the restoration control unit 12b to execute the power restoration transition sequence for the block 13b by a power restoration request 71.

[0095] The arbitration unit 4 refers to a predetermined threshold and issues permission for the power recovery period reservation request 60 within a range in which the maximum number of power switches does not exceed the threshold. The threshold may be hardwired into the circuit as a fixed value, or may be rewritable in a register after the chip is started up.

[0096] 11 is a timing chart showing an example of a control method for the information processing device 1 according to the second embodiment. The power restoration request 70 and the transition of the operating state in the subsystem 5 will be described below, but the same applies to the subsystem 6.

[0097] At time T31, the block 13a that is the target of the power restoration process in the subsystem 5 is in a power-off state. The sub CPU 11 asserts a power restoration request 70.

[0098] At time T32, the restoration control unit 12 asserts the power restoration request 70 and asserts the power switch on / off request signal 25a, causing the block 13a to transition to the "power on" state and turn the power switch on.

[0099] At time T33, when all the power switches are turned on, the block 13a asserts the power switch on / off permission signal 26 to notify that the block 13a has entered a power recovery state. The block 13a enters an "idle" state.

[0100] At time T34, when the power restoration transition sequence is completed, the restoration control unit 12a asserts the power restoration completion notification 24a to notify the sub CPU 11 of the completion.

[0101] At time T35, the sub CPU 11 receives the power restoration completion notification 24a and deasserts the power restoration request 70. At time T36, the restoration control unit 12a deasserts the power restoration completion notification 24a.

[0102] At time T37, the sub CPU 11 asserts the block activation signal 30a. Then, the block 13a starts to execute a predetermined process. The block 13a enters the "operating" state.

[0103] At time T38, when the block 13a completes the predetermined processing, it asserts the end interrupt 31a, and the block 13a enters the "idle" state.

[0104] 12 is a timing chart showing an example of a control method for the information processing device 1 according to the second embodiment. The operation of arbitration based on the power recovery period reservation request 60 will be described below based on two subsystems 5 and 6. In this embodiment, the threshold value set in the arbitration unit 4 is a fixed value of 70. The number of power switches in blocks 13a and 13b of subsystems 5 and 6 is as shown in FIG.

[0105] Time T40 is the initial state. At time T40, blocks 13a and 13b of subsystem 5 are in the "idle" state. Blocks 13a and 13b of subsystem 6 are in the "operating" state.

[0106] At time T41, the sub-CPU 11 of the subsystem 5 notifies the arbitration unit 4 of a power restoration period reservation request 60 and a power restoration switch count 61 of the subsystem 5. The power restoration period reservation request 60 reserves a period from time T46 to time T50. The power restoration switch count 61 is the maximum number of power switches among the power switches of the blocks 13a and 13 in the subsystem 5. As shown in FIG. 7, the block 13a of the subsystem 5 has 50 power switches, and the block 13b of the subsystem 5 has 30 power switches. Therefore, since the maximum number of power switches is 50, the power restoration switch count 61 is 50.

[0107] At time T42, the arbitration unit 4 notifies the sub CPU 11 of the subsystem 5 of permission by the power recovery period reservation permission 62 because the number of power recovery switches 61 (=50) is equal to or less than the threshold value (=70).

[0108] At time T43, the recovery control units 12a and 12b of subsystem 5 each confirm the reservation for the power recovery period, and therefore execute the power-off transition sequence for blocks 13a and 13b of subsystem 5. As the power is cut off, blocks 13a and 13b of subsystem 5 each transition to the "power-off transition" state and then to the "power-off" state. When block 13a of subsystem 6 completes the specified processing, it asserts the end interrupt 31a and enters the "idle" state.

[0109] At time T44, the sub-CPU 11 of the subsystem 6 notifies the arbitration unit 4 of the power recovery period reservation request 60 and the number of power recovery switches 61 of the subsystem 6. The power recovery period reservation request 60 reserves a period from time T50 to time T54. The number of power recovery switches 61 is the maximum number of power switches among the numbers of power switches of the blocks 13a and 13 in the subsystem 6. As shown in FIG. 7, the number of power switches of the block 13a of the subsystem 6 is 40, and the number of power switches of the block 13b of the subsystem 6 is 20. Therefore, since the maximum number of power switches is 40, the number of power recovery switches 61 is 40. When the block 13b of the subsystem 6 completes the predetermined processing, it asserts the end interrupt 31b and enters the "idle" state.

[0110] At time T45, the arbitration unit 4 notifies the sub CPU 11 of the subsystem 6 of permission by the power recovery period reservation permission 62 because the number of power recovery switches 61 (=40) of the subsystem 6 is less than or equal to the threshold value (=70).

[0111] At time T46, the reservation for the power recovery period has been confirmed, and therefore the recovery control units 12a and 12b of the subsystem 6 execute the power-off transition sequence for the blocks 13a and 13b of the subsystem 6. As a result of the power being shut off, the blocks 13a and 13b of the subsystem 6 transition to the "power-off transition" state and then to the "power-off" state.

[0112] At time T46, the power restoration occupation period begins for subsystem 5. The restoration control unit 12a of subsystem 5 starts processing the power restoration transition sequence for block 13a of subsystem 5. Block 13a of subsystem 5 enters the "power on transition" state.

[0113] At time T47, the restoration control unit 12a of the subsystem 5 completes the processing of the power restoration transition sequence for the block 13a of the subsystem 5. Upon completing the power restoration processing, the block 13a of the subsystem 5 asserts the end interrupt 31a and enters the "idle" state. Thereafter, the restoration control unit 12b of the subsystem 5 starts the processing of the power restoration transition sequence for the block 13b of the subsystem 5. The block 13b of the subsystem 5 enters the "power on transition" state.

[0114] At time T48, block 13a of subsystem 5 enters the "operating" state due to block activation 30a. At time T49, block 13b of subsystem 5 completes the power restoration process, asserts end interrupt 31b, and enters the "idle" state.

[0115] At time T50, the power recovery occupancy period of subsystem 5 ends, and the power recovery occupancy period of subsystem 6 begins. The recovery control unit 12a of subsystem 6 starts processing the power recovery transition sequence of block 13a of subsystem 6. Block 13a of subsystem 6 enters the "power on transition" state. Thereafter, block 13b of subsystem 5 enters the "operating" state due to block activation 30b.

[0116] At time T51, the restoration control unit 12a of the subsystem 6 completes the processing of the power restoration transition sequence for the block 13a of the subsystem 6. Upon completing the power restoration processing, the block 13a of the subsystem 6 asserts the end interrupt 31a and enters the "idle" state. Thereafter, the restoration control unit 12b of the subsystem 6 starts the processing of the power restoration transition sequence for the block 13b of the subsystem 6. The block 13b of the subsystem 6 enters the "power on transition" state.

[0117] At time T52, block 13a of subsystem 6 enters the "operating" state due to block activation 30a. At time T53, block 13b of subsystem 6 completes the power restoration process, asserts end interrupt 31b, and enters the "idle" state.

[0118] As described above, the blocks 13a and 13b of the subsystems 5 and 6 execute the power restoration process only during the reserved power restoration occupancy period. This prevents the power restoration processes of the blocks 13a and 13b of the subsystems 5 and 6 from overlapping.

[0119] Fig. 13 is a timing chart showing an example of another control method for the information processing device 1 according to the second embodiment. Another example of the operation of arbitration based on the power recovery period reservation request 60 will be described below. As in Fig. 12, the threshold set in the arbitration unit 4 is a fixed value of 70. The number of power switches in blocks 13a and 13b of subsystems 5 and 6 is as shown in Fig. 7. Differences between Fig. 13 and Fig. 12 will be described below.

[0120] The processing from time T60 to time T63 is the same as the processing from time T40 to time T43 in Fig. 12. The power recovery period reservation request 60 of the subsystem 5 reserves the period from time T66 to time T70.

[0121] At time T64, the sub-CPU 11 of the subsystem 6 notifies the arbitration unit 4 of the power restoration period reservation request 60 of the subsystem 6 and the number of power restoration switches 61. The reservation period of the power restoration period reservation request 60 of the subsystem 6 is the period from time T68 to T73, which overlaps with the reservation period T66 to T70 of the power restoration period reservation request 60 of the subsystem 5.

[0122] As shown in Figure 7, the maximum number of power switches among the number of power switches in block 13a (=50) and the number of power switches in block 13b (=30) in subsystem 5 is 50, so the number of power restoration switches 61 in subsystem 5 is 40. Also, the maximum number of power switches among the number of power switches in block 13a (=40) and the number of power switches in block 13b (=20) in subsystem 6 is 40, so the number of power restoration switches 61 in subsystem 6 is 40. Therefore, during the period when the reservation periods of the above subsystems 5 and 6 overlap, the total number of maximum power switches to process power restoration is 50 + 40 = 90.

[0123] At time T65, the arbitration unit 4 notifies the sub CPU 11 of the subsystem 6 of denial by the power recovery period reservation permission 62 because the total number (=90) of the maximum number of power switches is greater than the threshold value (=70).

[0124] The processing of subsystem 5 from time T66 onwards is the same as the processing from time T46 onwards in Figure 12. Time T68 is the start time of the reservation period T68-T73 of subsystem 6's power recovery period reservation request 60. At time T68, subsystem 6 does not execute the process of transitioning blocks 13a and 13b of subsystem 6 to a power-off state because the power recovery period reservation request 60 was rejected. Blocks 13a and 13b of subsystem 6 remain in the "idle" state.

[0125] Note that the above time T65 was described as a case where the total number of maximum power switches during the overlapping period of the reservation periods of subsystem 5 and subsystem 6 is greater than the threshold. If the total number of maximum power switches is equal to or less than the threshold, arbitration unit 4 can reserve the reservation period T66 to T70 of subsystem 5 and the reservation period T68 to T73 of subsystem 6 so that they overlap. In this case, subsystem 5 and subsystem 6 will execute power restoration transition sequences in parallel.

[0126] In this embodiment, the restoration control units 12a and 12b exclusively execute the power restoration process for the multiple blocks 13a and 13b in the same subsystem, respectively. However, this is not limited to this. The restoration control units 12a and 12b may simultaneously execute the power restoration process for the blocks 13a and 13b in parallel as long as the number of power restoration switches 61 is equal to or less than a threshold value. In this case, the sub-CPU 11 must notify the arbitration unit 4 of the number of power restoration switches 61 in the case of parallel processing, along with the power restoration period reservation request 60.

[0127] The arbitration unit 4 collectively manages the power restoration occupation period for each of the subsystems 5 and 6 for power restoration control for multiple blocks, and grants the right of occupation when the number of power restoration switches 61 is below a threshold, thereby reducing the risk of noise generation on the power line. By being able to execute power restoration processing without delay during the power restoration occupation period, the subsystems 5 and 6 prevent long delays in power restoration due to arbitration, and can execute power restoration processing for multiple blocks simultaneously without degrading performance.

[0128] As described above, according to the first and second embodiments, the blocks 13a and 13b of the subsystems 5 and 6 can each transition from a power-off state to a power-supply state, and are supplied with power voltage from the same power line. The blocks 13a and 13b and the recovery control units 12a and 12b are present in one of the subsystems 5 and 6.

[0129] The sub-CPU 11 is a request unit that issues a power supply request for each block, requesting that blocks 13a and 13b transition from a power-off state to a power-supply state. The power supply request is the power restoration request 22a or 22b in Fig. 1 or the power restoration period reservation request 60 in Fig. 10. The sub-CPU 11 issues a power supply request regardless of the state of the block to which the power supply request is not issued.

[0130] When there are multiple power supply requests, the arbitration unit 4 arbitrates the multiple power supply requests and issues a permission for the power supply request. The permission is the power recovery permission 23a or 23b in FIG. 1 or the power recovery period reservation permission 62 in FIG. 10.

[0131] The restoration control units 12a and 12b are transition processing units that can respectively perform processing for transitioning the blocks 13a and 13b from a power-off state to a power-supply state. The restoration control units 12a and 12b also perform processing for transitioning the blocks for which permission has been issued in response to a power supply request from a power-off state to a power-supply state.

[0132] The arbitration unit 4 issues a permission for a power supply request according to the total number of power switches in the block to which the power supply request is issued. The arbitration unit 4 arbitrates so that the total number of power switches in the block to which the power supply request is issued does not exceed a threshold value.

[0133] The arbitration unit 4 issues a permission to the power supply request if the total number of power switches in the block to which the power supply request is issued is within a threshold value, and issues a denial to the power supply request if the total number of power switches in the block to which the power supply request is issued is greater than the threshold value.

[0134] The threshold changes depending on the states of multiple blocks, as shown in FIG. 8. The block states include the operation state of the block, the power supply voltage, and the operating frequency. The block states may be the operation state of the block, the power supply voltage, or the operating frequency. The operation states of the block include a power-off state (power-off state), an idle state, and a normal operation state (operating state).

[0135] The threshold value in step S32 in Fig. 8 is the threshold value when all of the multiple blocks are in a power-off state. The threshold value in step S34 in Fig. 8 is the threshold value when all of the multiple blocks are in an idle state or a power-on transition state. The threshold value in step S35 in Fig. 8 is the threshold value when any of the multiple blocks is in a normal operating state. The threshold value in step S32 is larger than the threshold value in step S34. The threshold value in step S34 is larger than the threshold value in step S35. The threshold value in step S35 is smaller as the power supply voltage is lower and as the operating frequency is higher, as in Fig. 6.

[0136] If the total number of power switches of blocks for which power supply requests have been issued is greater than a threshold value, the arbitration unit 4 can control the operation of blocks for which power supply requests have not been issued to be changed so that the threshold value is increased.

[0137] The arbitration unit 4 can control the block to remain in the idle state if there is a possibility that the total number of power switches of the block to which a power supply request has been issued will exceed a threshold value when the block transitions from the idle state to the normal operation state.

[0138] In the second embodiment, the sub-CPU 11 reserves a period for transitioning the block from a power-off state to a power-supply state. The recovery control units 12a and 12b each perform processing for transitioning the block from a power-off state to a power-supply state during the reserved period. If permission is granted for the power supply request, the recovery control units 12a and 12b each perform processing for transitioning the block from a power-off state to a power-supply state during the reserved period. Furthermore, if permission is not granted for the power supply request, the recovery control units 12a and 12b each do not perform processing for transitioning the block from a power-off state to a power-supply state during the reserved period.

[0139] In Fig. 12, when permission is issued for multiple power supply requests, the restoration control units 12a and 12b perform migration processing for multiple blocks exclusively and sequentially. When permission is issued for multiple power supply requests, as in Fig. 9, the restoration control units 12a and 12b may perform migration processing for multiple blocks in parallel so that all or part of the processing overlaps.

[0140] As described above, according to the first and second embodiments, the subsystems 5 and 6 are capable of restoring a plurality of blocks from a power-off state to the extent that the generation of noise on the power supply line can be reduced.

[0141] (Other embodiments) The present disclosure can also be realized by a process in which a program that realizes one or more functions of the above-described embodiments is supplied to a system or device via a network or a storage medium, and one or more processors in the computer of the system or device read and execute the program. The present disclosure can also be realized by a circuit (e.g., ASIC) that realizes one or more functions.

[0142] The above embodiments are described to briefly explain the principles and practical applications of the present disclosure, and to enable others skilled in the art to understand the present disclosure. Other embodiments with various modifications may be suitable for specific applications, and are within the scope of the present disclosure. [Explanation of symbols]

[0143] 1 Information processing device, 2 Main CPU, 3 Clock reset control unit, 4 Arbitration unit, 5 Subsystem, 6 Subsystem, 11 Sub-CPU, 12a Recovery control unit, 12b Recovery control unit, 13a Block, 13b Block

Claims

1. a plurality of blocks each capable of transitioning from a power-off state to a power-supply state; a request unit that issues a power supply request for each of the blocks to transition from the power-off state to the power-supply state; an arbitration unit that arbitrates a plurality of power supply requests when there are multiple power supply requests and issues a permission for each of the power supply requests; a plurality of transition processing units capable of performing processing to transition each of the plurality of blocks from the power-off state to the power-supply state, and performing processing to transition a block for which permission for a power supply request has been issued from the power-off state to the power-supply state.

2. 2. The semiconductor integrated circuit according to claim 1, wherein the arbitration unit issues a permission for the power supply request in accordance with the total number of power switches in the block to which the power supply request is issued.

3. 3. The semiconductor integrated circuit according to claim 1, wherein the arbitration unit performs arbitration so that the total number of power switches in the blocks to which the power supply requests are issued does not exceed a threshold value.

4. The semiconductor integrated circuit according to any one of claims 1 to 3, characterized in that the arbitration unit issues a permission for the power supply request if the total number of power switches of the block to which the power supply request is issued is within a threshold value, and issues a refusal for the power supply request if the total number of power switches of the block to which the power supply request is issued is greater than a threshold value.

5. 5. The semiconductor integrated circuit according to claim 3, wherein the threshold value changes depending on the states of the plurality of blocks.

6. 6. The semiconductor integrated circuit according to claim 5, wherein the state of the block is an operating state of the block.

7. 7. The semiconductor integrated circuit according to claim 5, wherein the state of the block is a power supply voltage or an operating frequency of the block.

8. 8. The semiconductor integrated circuit according to claim 5, wherein the state of the block is an operating state of the block, a power supply voltage, and an operating frequency.

9. 9. The semiconductor integrated circuit according to claim 1, wherein the plurality of blocks are supplied with a power supply voltage from a same power supply line.

10. The operating states of the block include a power-off state, an idle state, and a normal operating state; the threshold value when all of the plurality of blocks are in a power-off state is greater than the threshold value when all of the plurality of blocks are in an idle state; 9. The semiconductor integrated circuit according to claim 6, wherein the threshold value when all of the plurality of blocks are in an idle state is greater than the threshold value when any of the plurality of blocks is in a normal operating state.

11. The operation state of the block includes a power-off state and a normal operation state, 9. The semiconductor integrated circuit according to claim 6, wherein the threshold value when all of the plurality of blocks are in a power-off state is greater than the threshold value when any of the plurality of blocks is in a normal operating state.

12. 9. The semiconductor integrated circuit according to claim 7, wherein the threshold value decreases as the power supply voltage decreases and as the operating frequency increases.

13. 6. The semiconductor integrated circuit according to claim 5, wherein, when a total number of power switches of the blocks to which the power supply requests have been issued is greater than a threshold value, the arbitration unit controls to change the operation of the blocks to which the power supply requests have not been issued so that the threshold value becomes larger.

14. 11. The semiconductor integrated circuit according to claim 10, wherein the arbitration unit controls the block to remain in the idle state if there is a possibility that the total number of power switches of the block to which the power supply request is issued will become greater than a threshold value when the block transitions from the idle state to a normal operation state.

15. the semiconductor integrated circuit has a plurality of subsystems, 15. The semiconductor integrated circuit according to claim 1, wherein the plurality of blocks and the plurality of transition processing units are present in any one of the plurality of subsystems.

16. the request unit reserves a period for transitioning the block from the power-off state to the power-supply state; The semiconductor integrated circuit according to any one of claims 1 to 15, characterized in that the transition processing unit performs processing to transition the block from the power-off state to the power-supply state during the reserved period.

17. 17. The semiconductor integrated circuit according to claim 16, wherein the transition processing unit performs processing to transition the block from the power-off state to the power-supply state during the reserved period if permission for the power supply request is issued, and does not perform processing to transition the block from the power-off state to the power-supply state during the reserved period if permission for the power supply request is not issued.

18. The semiconductor integrated circuit according to any one of claims 1 to 17, characterized in that when permission is issued for a plurality of power supply requests, the plurality of transition processing units perform the transition processing of the plurality of blocks exclusively and sequentially.

19. The semiconductor integrated circuit according to any one of claims 1 to 17, characterized in that when permission is issued for a plurality of power supply requests, the plurality of transition processing units perform the transition processing of a plurality of blocks in parallel so that all or part of the transition processing overlaps.

20. A method for controlling a semiconductor integrated circuit having a plurality of blocks, each of which can transition from a power-off state to a power-supply state, comprising: a request step of issuing a power supply request for each of the blocks to request a transition from the power cut-off state to the power supply state; an arbitration step of arbitrating the plurality of power supply requests and issuing a permission for the power supply requests when there are a plurality of power supply requests; a transition processing step for performing processing for transitioning from the power cut-off state to the power supplied state for a block for which permission for the power supply request has been issued.

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