Ceramic electronic component and manufacturing method thereof

Abstract

To provide a ceramic electronic component that compatibly has continuity of an internal electrode layer and insulation reliability on a dielectric layer, and a method of manufacturing the same.SOLUTION: A ceramic electronic component comprises a laminate chip where a dielectric layer formed principally of ceramic and an internal electrode layer formed principally of first metal are laminated, wherein one of a first surface and a second surface of the internal electrode layer which are opposed to each other in the lamination direction is covered with a metal oxide film of second metal which is easier to oxidize than the first metal, and the other surface of the first surface and second surface is not coated with the metal oxide film, or the one surface is coated with the metal oxide film, and the metal oxide film with which the other surface is coated is smaller in area than the metal oxide film with which the one surface is coated.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to a ceramic electronic component and a method for manufacturing the same. [Background technology]

[0002] In recent years, there has been an increasing demand for high-end multilayer ceramic capacitors with high capacity and high reliability in in-vehicle terminals, mobile terminals, etc. High-end multilayer ceramic capacitors are used for applications such as DC decoupling, noise bypass, and voltage stabilization in high-frequency circuits and power circuits.

[0003] In order to achieve a small size and high capacitance, the internal electrode layers and dielectric layers of multilayer ceramic capacitors are becoming thinner (for example, Patent Document 1). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] International Publication No. 2008 / 072448 [Non-patent literature]

[0005] [Non-Patent Document 1] Polotai, Anton V., et al. "Effect of Cr additions on the microstructural stability of Ni electrodes in ultra-thin BaTiO 3 multilayer capacitors." Journal of electroceramics 18.3-4 (2007): 261-268 Summary of the Invention [Problem to be solved by the invention]

[0006] However, thinning the layers may cause the internal electrode layers to fracture or the reliability of the dielectric layers to decrease. For example, Patent Document 1 proposes that adding chromium (Cr) to the internal electrode layers, which are mainly composed of nickel (Ni), can prevent the internal electrode layers from becoming spheroidized and improve the continuity of the internal electrode layers. However, as reported in Non-Patent Document 1, for example, it is known that Cr added to the internal electrode layers promotes the generation of oxygen defects at the interface with the dielectric layer, thereby reducing the insulation reliability of the dielectric layer.

[0007] The present invention has been made in view of the above-mentioned problems, and has as its object to provide a ceramic electronic component that achieves both continuity of internal electrode layers and insulation reliability of dielectric layers, and a method for manufacturing the same. [Means for solving the problem]

[0008] The ceramic electronic component according to the present invention comprises a dielectric layer mainly made of ceramic and a first metal. Made of internal electrode material and internal electrode layers are alternately stacked on a laminated chip, The internal electrode layer has a first surface and a second surface facing the first surface in the same stacking direction of the internal electrode layer, and the entire area of ​​the first surface of the internal electrode layer made of the internal electrode material is A second metal that is more easily oxidized than the first metal Consists of coated with a metal oxide film, and The second electrode layer made of the internal electrode material the surface is not covered by said metal oxide film, or The first surface and the second surface of the internal electrode layer The face of A second metal that is more easily oxidized than the first metal The metal oxide film is coated on the substrate. No. 2 The area of ​​the metal oxide film covering the surface of No. 1 The surface area of ​​the metal oxide film is smaller than the surface area of ​​the metal oxide film that covers the surface of the metal oxide film.

[0009] In the ceramic electronic component, the first metal may be nickel.

[0010] In the ceramic electronic component, the metal oxide film may be a chromium oxide film.

[0011] In the ceramic electronic component, the ratio of the metal oxide film to the internal electrode layers may be 0.1 at % to 5 at %.

[0012] In the ceramic electronic component, the ratio of the metal oxide film to the internal electrode layers may be 3 at % or less.

[0013] In the ceramic electronic component, the ratio of the metal oxide film to the internal electrode layers may be 1.5 at % or less.

[0014] The method for manufacturing a ceramic electronic component according to the present invention comprises the steps of: forming a dielectric green sheet on which a first metal is deposited as a main component; Made of internal electrode material A step of forming a laminate unit by sputtering an internal electrode layer pattern and a coating pattern mainly composed of a second metal that is more easily oxidized than the first metal on one of the first and second surfaces of the internal electrode layer pattern; a step of laminating a plurality of the laminate units to form a laminate; and a step of firing the laminate. and obtain a laminated chip in which dielectric layers mainly composed of ceramic and internal electrode layers made of the internal electrode material mainly composed of the first metal are alternately laminated. and fruit , the first surface and the second surface are opposed to each other in a stacking direction of the plurality of the laminate units, and the entire first surface of the internal electrode layer is covered with a metal oxide film made of the second metal, and the second surface is not covered with the metal oxide film, or the first surface and the second surface of the internal electrode layer are covered with the metal oxide film made of the second metal, and an area of ​​the metal oxide film covering the second surface is smaller than an area of ​​the metal oxide film covering the first surface. It is characterized by:

[0015] In the method for manufacturing a ceramic electronic component, the ratio of the coating pattern to the internal electrode layer pattern may be 0.1 at % to 5 at %.

[0016] The method for manufacturing a ceramic electronic component according to the present invention includes the steps of: A composite film containing a first metal and a second metal that is more easily oxidized than the first metal is formed by sputtering, with the proportion of the second metal being 1 at % to 5 at %, On dielectric green sheet to Internal electrode layer pattern was formed forming a laminated body by laminating a plurality of the laminated units; and firing the laminated body. and obtain a laminated chip in which dielectric layers mainly composed of ceramic and internal electrode layers made of an internal electrode material mainly composed of the first metal are alternately laminated. and the internal electrode layer has a first surface and a second surface opposite to the first surface in the same stacking direction of the internal electrode layer, the entire area of ​​the first surface of the internal electrode layer made of the internal electrode material is covered with a metal oxide film made of the second metal which is more easily oxidized than the first metal, and the second surface of the internal electrode layer made of the internal electrode material is not covered with the metal oxide film, or the first surface and the second surface of the internal electrode layer are covered with the metal oxide film made of the second metal which is more easily oxidized than the first metal, and the area of ​​the metal oxide film covering the second surface is smaller than the area of ​​the metal oxide film covering the first surface; It is characterized by:

[0017] In the method for manufacturing a ceramic electronic component, the first metal may be nickel, and the second metal may be chromium. [Effects of the Invention]

[0018] According to the present invention, it is possible to provide a ceramic electronic component that achieves both continuity of internal electrode layers and reliability of dielectric layers, and a method for manufacturing the same. [Brief explanation of the drawings]

[0019] [Figure 1] FIG. 1(a) is a partial cross-sectional perspective view of the multilayer ceramic capacitor, and FIG. 1(b) is a top view of the multilayer ceramic capacitor. [Figure 2] 2(a) is a cross-sectional view taken along line AA in FIG. 1(b), and FIG. 2(b) is a cross-sectional view taken along line BB in FIG. 1(b). [Figure 3] FIG. 3 is a schematic cross-sectional view of a multilayer ceramic capacitor in which the internal electrode layers are thinned. [Figure 4] 4(a) and 4(b) are diagrams for explaining details of the vicinity of the boundary between the internal electrode layer and the dielectric layer. [Figure 5] 5(a) and 5(b) are diagrams for explaining estimation of the magnitude relationship between the area of ​​the coating covering the upper surface of the internal electrode layer and the area of ​​the coating covering the lower surface of the internal electrode layer. [Figure 6] 6(a) to 6(c) are diagrams illustrating the analysis results when the concentration of each element is analyzed line-wise at each sample point along the lamination direction of the dielectric layers and internal electrode layers in a TEM image. [Figure 7] FIG. 7 is a diagram for explaining the distance in FIG. 6(a). [Figure 8] FIG. 8 is a flowchart illustrating a method for manufacturing a multilayer ceramic capacitor. [Figure 9] 9(a) to 9(c) are diagrams illustrating the lamination step. [Figure 10] 10(a) to 10(c) are diagrams illustrating another example of the lamination step. [Figure 11] 11(a) and 11(b) are diagrams illustrating another example of the lamination step. [Figure 12] FIG. 12 is a diagram illustrating the continuity rate. [Figure 13] 13(a) is a cross-sectional SEM image of Comparative Example 1. FIG. 13(b) is a cross-sectional SEM image of Example 1. DETAILED DESCRIPTION OF THE INVENTION

[0020] Hereinafter, embodiments will be described with reference to the drawings.

[0021] (Embodiment) Fig. 1(a) is a partial cross-sectional perspective view of a multilayer ceramic capacitor 100 according to an embodiment, and Fig. 1(b) is a top view of the multilayer ceramic capacitor 100. Fig. 2(a) is a cross-sectional view taken along line AA in Fig. 1(b), and Fig. 2(b) is a cross-sectional view taken along line BB in Fig. 1(b).

[0022] As illustrated in Figures 1(a) to 2(b), the multilayer ceramic capacitor 100 includes a laminated chip 10 having a substantially rectangular parallelepiped shape and external electrodes 20a, 20b provided on two opposing end faces of the laminated chip 10. Of the four faces of the laminated chip 10 other than the two end faces, the two faces other than the top and bottom faces in the stacking direction are referred to as side faces. The external electrodes 20a, 20b extend on the top, bottom and two side faces in the stacking direction of the laminated chip 10. However, the external electrodes 20a, 20b are spaced apart from each other.

[0023] The multilayer chip 10 has a configuration in which dielectric layers 11 containing a ceramic material that functions as a dielectric and internal electrode layers 12 containing a base metal material are alternately stacked. The edges of each internal electrode layer 12 are alternately exposed at the end face of the multilayer chip 10 where the external electrode 20a is provided and the end face where the external electrode 20b is provided. As a result, each internal electrode layer 12 is alternately electrically connected to the external electrode 20a and the external electrode 20b. As a result, the multilayer ceramic capacitor 100 has a configuration in which multiple dielectric layers 11 are stacked with the internal electrode layers 12 interposed therebetween. In addition, in a laminate of the dielectric layers 11 and the internal electrode layers 12, the internal electrode layer 12 is arranged as the outermost layer in the stacking direction, and the upper and lower surfaces of the laminate are covered by cover layers 13. The cover layers 13 are primarily composed of a ceramic material. For example, the material of the cover layers 13 may be primarily composed of the same ceramic material as the dielectric layers 11.

[0024] The size of the multilayer ceramic capacitor 100 is, for example, 0.25 mm in length, 0.125 mm in width, and 0.125 mm in height, or 0.4 mm in length, 0.2 mm in width, and 0.2 mm in height, or 0.6 mm in length, 0.3 mm in width, and 0.3 mm in height, or 0.6 mm in length, 0.3 mm in width, and 0.110 mm in height, or 1.0 mm in length, 0.5 mm in width, and 0.5 mm in height, or 1.0 mm in length, 0.5 mm in width, and 0.1 mm in height, or 3.2 mm in length, 1.6 mm in width, and 1.6 mm in height, or 4.5 mm in length, 3.2 mm in width, and 2.5 mm in height, but is not limited to these sizes.

[0025] The dielectric layer 11 has a main phase made of a ceramic material having a perovskite structure represented by the general formula ABO3. 3-α For example, the ceramic material includes BaTiO3 (barium titanate), CaZrO3 (calcium zirconate), CaTiO3 (calcium titanate), SrTiO3 (strontium titanate), MgTiO3 (magnesium titanate), BaTiO3 (barium titanate) which forms a perovskite structure, 1-x-y Ca x Sry Ti 1-z Zr z At least one of the following can be selected and used: O3 (0≦x≦1, 0≦y≦1, 0≦z≦1). 1-x-y Ca x Sr y Ti 1-z Zr z O3 includes barium strontium titanate, barium calcium titanate, barium zirconate, barium titanate zirconate, calcium titanate zirconate and barium calcium titanate zirconate.

[0026] 2(a), the region where the internal electrode layer 12 connected to the external electrode 20a and the internal electrode layer 12 connected to the external electrode 20b face each other is a region where capacitance is generated in the multilayer ceramic capacitor 100. Therefore, this region where capacitance is generated is referred to as a capacitance region 14. In other words, the capacitance region 14 is a region where adjacent internal electrode layers 12 connected to different external electrodes face each other.

[0027] The region where the internal electrode layers 12 connected to the external electrode 20a face each other without an internal electrode layer 12 connected to the external electrode 20b interposed therebetween is called the end margin 15. The region where the internal electrode layers 12 connected to the external electrode 20b face each other without an internal electrode layer 12 connected to the external electrode 20a interposed therebetween is also the end margin 15. In other words, the end margin 15 is the region where the internal electrode layers 12 connected to the same external electrode face each other without an internal electrode layer 12 connected to a different external electrode interposed therebetween. The end margin 15 is a region where no capacitance is generated.

[0028] 2(b), in the laminated chip 10, the regions extending from the two side surfaces of the laminated chip 10 to the internal electrode layers 12 are referred to as side margins 16. In other words, the side margins 16 are regions provided so as to cover the ends of the multiple internal electrode layers 12 stacked in the above-mentioned laminated structure that extend to the two side surfaces. The side margins 16 are also regions that do not generate electrical capacitance.

[0029] In order to make multilayer ceramic capacitors smaller and with greater capacitance, it is necessary to reduce the thickness of the dielectric layers 11 and the internal electrode layers 12. Fig. 3 is a schematic cross-sectional view of a multilayer ceramic capacitor 1000 in which the internal electrode layers have been thinned. The cross section of Fig. 3 corresponds to the cross section taken along line AA in Fig. 1(b).

[0030] When attempting to thin the internal electrode layers 12, it becomes difficult to maintain a high continuity ratio for the following reasons.

[0031] When the internal electrode layers 12 are obtained by sintering metal powder, the metal powder components of the internal electrode layers 12 become spherical as the sintering process progresses in an attempt to minimize surface energy. Since the metal components of the internal electrode layers 12 sinter more easily than the ceramic components that are the main component of the dielectric layers 11, if the temperature is raised until the ceramic components that are the main component of the dielectric layers 11 sinters, the metal components of the internal electrode layers 12 become over-sintered and try to become spherical. In this case, if there is a break (defect), the internal electrode layers 12 will break from the defect as a starting point, and the continuity rate will decrease as shown in Figure 3.

[0032] Therefore, in the multilayer ceramic capacitor 100 according to this embodiment, one of the upper surface (first surface) and the lower surface (second surface) of each internal electrode layer 12 is covered with a coating 17 of an oxide of a metal (second metal) that is more easily oxidized than the main component metal (first metal) of the internal electrode layer 12. FIGS. 4(a) and 4(b) are views for explaining details of the vicinity of the boundary between the internal electrode layer 12 and the dielectric layer 11. Note that the number of layers of the internal electrode layers 12 in the cross-sectional views of FIG. 4(a) and subsequent figures is different from the number of layers of the internal electrode layers 12 in the cross-sectional views of FIG. 2(a) and FIG. 2(b). Specifically, in the cross-sectional views of FIG. 4(a) and subsequent figures, the number of layers of the internal electrode layers 12 is set to four for clarity of illustration.

[0033] 4(a) and 4(b), one of the upper and lower surfaces of the internal electrode layer 12 is covered with a coating 17. The thickness of the coating 17 in the lamination direction is, for example, 1 to 50 nm.

[0034] The thickness of the coating 17 in the stacking direction can be determined as follows. First, in a TEM image of the multilayer ceramic capacitor 100, the concentration of each component element is analyzed line-by-line at each sample point along the stacking direction of the dielectric layers 11 and the internal electrode layers 12 to obtain the Ni concentration and Ti concentration at each sample point in the stacking direction. Next, the Ni concentration and Ti concentration are differentiated, and the thickness of the coating 17 is determined as the distance in the stacking direction between the point where the differential value of the Ni concentration is greatest and the point where the differential value of the Ti concentration is smallest.

[0035] The ratio of the coating 17 to the internal electrode layer 12 is 0.1 at % to 5 at %. The ratio of the coating 17 to the internal electrode layer 12 is expressed as N2 / (N1+N2)×100, where N1 is the number of atoms of the main component metal of the internal electrode layer 12 between two adjacent dielectric layers 11, and N2 is the number of metal atoms in the metal oxide that constitutes the coating 17. The ratio of the coating 17 to the internal electrode layer 12 is preferably 3 at % or less, and more preferably 1.5 at % or less.

[0036] The main component metal of the internal electrode layers 12 is, for example, nickel (Ni). When the main component metal of the internal electrode layers 12 is Ni, the coating 17 is a coating of an oxide of chromium (Cr), aluminum (Al), or iron (Fe), which is more easily oxidized than Ni. The coating 17 does not have to be composed only of the oxide, and may contain other diffused elements. The main component metal of the internal electrode layers 12 is not limited to Ni, and may be a metal having a melting point close to Ni.

[0037] The other of the upper and lower surfaces of the internal electrode layer 12 is not covered by the coating 17, or the area of ​​the other surface covered by the coating 17 is smaller than the area of ​​the one surface covered by the coating 17. The area covered by the coating 17 on one side is 1 / 2 or less, preferably 1 / 5 or less, and more preferably 1 / 10 or less.

[0038] The relationship in size between the area of ​​the coating 17 covering the upper surface of the internal electrode layer 12 and the area of ​​the coating 17 covering the lower surface of the internal electrode layer 12 can be estimated as follows. Figures 5(a) and 5(b) are diagrams for explaining the estimation of the relationship in size between the area of ​​the coating 17 covering the upper surface of the internal electrode layer 12 and the area of ​​the coating 17 covering the lower surface of the internal electrode layer 12.

[0039] Fig. 5(a) is a top view of the multilayer ceramic capacitor 100. Scanning electron microscope (SEM) images of cross sections are obtained in the width direction of the multilayer ceramic capacitor 100 at multiple positions indicated by dashed lines in Fig. 5(a).

[0040] 5(b) is a schematic diagram of a cut surface of the multilayer ceramic capacitor 100. In the SEM photograph of each cut surface, the lengths of the coatings 17 on the upper and lower surfaces of the same internal electrode layer 12 are measured. For example, in the SEM image of the cut surface at the position indicated by the dashed dotted line LN1 in FIG. 5(a), the total length of the coatings 17 on the upper surfaces of the internal electrode layers 12 is LU1, and the total length of the coatings 17 on the lower surfaces is LL1. In the SEM image of the cut surface at the position indicated by the dashed dotted line LN2, the total length of the coatings 17 on the upper surfaces of the internal electrode layers 12 is LU2, and the total length of the coatings 17 on the lower surfaces is LL2. In the SEM image of the cut surface at the position indicated by the dashed dotted line LN3, the total length of the coating 17 on the upper surface of the internal electrode layer 12 is LU3, and the total length of the coating 17 on the lower surface is LL3, and in the SEM image of the cut surface at the position indicated by the dashed dotted line LN4, the total length of the coating 17 on the upper surface of the internal electrode layer 12 is LU4, and the total length of the coating 17 on the lower surface is LL4. In this case, for example, if the total length of the coating 17 on the upper surface of the internal electrode layer 12 at each cut surface (LU1+LU2+LU3+LU4) is greater than the total length of the coating 17 on the lower surface of the internal electrode layer 12 at each cut surface (LL1+LL2+LL3+LL4), it can be estimated that the area of ​​the coating 17 covering the upper surface of the internal electrode layer 12 is greater than the area covering the lower surface. The reason why the area of ​​the coating 17 on the lower surface can be made relatively small is that there is a possibility that the metal of the metal oxide constituting the coating 17 on the upper surface will diffuse from within the internal electrode layer 12 or from discontinuous portions of the internal electrode layer 12, forming the coating 17 on the lower surface as well. In this case, the area covered by the coating 17 on the lower surface will be smaller than that on the upper surface. Although the area of ​​the coating 17 has been described, when the coating 17 is formed by this mechanism, the coating 17 may be formed on the lower surface so that the metal concentration of the metal oxide is lower than that of the upper surface coating 17. According to this analysis, the concentration difference between the upper and lower surfaces is 0.1 to 5 at %.

[0041] 6(a) to 6(c) are diagrams illustrating analysis results when the concentration of each component element is analyzed line-by-line at each sample point along the lamination direction of the dielectric layers 11 and the internal electrode layers 12 in a TEM image of the multilayer ceramic capacitor 100. In the example of Fig. 6(a) to 6(c), as an example, Ni is used as the main component metal of the internal electrode layers 12, the coating film 17 is a chromium oxide film, and barium titanate is used as the main component ceramic of the dielectric layers 11.

[0042] In Figure 6(a), the horizontal axis represents the distance in the stacking direction, and the vertical axis represents the concentration (at%) of each component. As shown in Figure 7, "0 nm" on the horizontal axis indicates the predicted interface between the internal electrode layer 12 and the dielectric layer 11 in a multilayer ceramic capacitor in which a coating 17 is formed on the top surface of the internal electrode layer 12. As the distance on the horizontal axis increases, the distance approaches the internal electrode layer 12 in the stacking direction. As shown in Figure 6(a), at a distance of "0 nm," the titanium (Ti) and oxygen (O) concentrations, which constitute barium titanate, the main ceramic component of the dielectric layer 11, are highest. As the distance approaches the internal electrode layer 12, the Ti and O concentrations decrease, a peak appears in the chromium (Cr) concentration, and the nickel (Ni) concentration, the main metal component of the internal electrode layer 12, increases. Note that the example in Figure 6(a) was smoothed by averaging over nine points to reduce noise.

[0043] FIG. 6(b) shows the results of differentiating the Ni concentration, Cr concentration, and Ti concentration in FIG. 6(a). By identifying the point of the steepest change, the interface of the internal electrode layer 12 and the interface of the dielectric layer 11 can be identified. In the example of FIG. 6(b), the position where the differential value of the Ni concentration is the largest is the interface of the internal electrode layer 12. Also, the position where the differential value of the Ti concentration is the largest is the interface of the dielectric layer 11. This means that a large amount of Cr is present between the interface of the dielectric layer 11 and the interface of the internal electrode layer 12.

[0044] Fig. 6(c) is a graph showing the results of Fig. 6(a) with the vertical axis plotted on a logarithmic scale. As shown in Fig. 6(c), a peak in the Cr concentration appears between the interface of the dielectric layer 11 and the interface of the internal electrode layer 12.

[0045] According to this configuration, the coating 17 made of an oxide of a metal that is more easily oxidized than the main component metal of the internal electrode layer 12 suppresses the spheroidization of the metal component of the internal electrode layer 12, thereby improving the continuity rate of the internal electrode layer 12. In addition, since the coating 17 covers one of the upper and lower surfaces of the internal electrode layer 12, the induction of oxygen defects due to the main component metal of the coating 17 can be suppressed more than when both surfaces of the internal electrode layer 12 are covered with the coating 17. This makes it possible to obtain a multilayer ceramic capacitor 100 that achieves both the continuity of the internal electrode layer 12 and the insulation reliability of the dielectric layer 11.

[0046] Next, a description will be given of a method for manufacturing the multilayer ceramic capacitor 100. FIG.

[0047] (Raw powder production process: S1) First, a dielectric material for forming the dielectric layer 11 is prepared. The A-site elements and B-site elements contained in the dielectric layer 11 are typically contained in the dielectric layer 11 in the form of a sintered body of ABO3 particles. For example, BaTiO3 is a tetragonal compound with a perovskite structure and exhibits a high dielectric constant. This BaTiO3 can generally be obtained by synthesizing barium titanate by reacting a titanium raw material such as titanium dioxide with a barium raw material such as barium carbonate. Various methods have been known for synthesizing the ceramic that constitutes the dielectric layer 11, including the solid-phase method, the sol-gel method, and the hydrothermal method. Any of these methods can be used in this embodiment.

[0048] The resulting ceramic powder is then mixed with a specific additive compound depending on the purpose, such as oxides of Mn (manganese), V (vanadium), Cr (chromium), rare earth elements (Y (yttrium), Dy (dysprosium), Tm (thulium), Ho (holmium), Tb (terbium), Yb (ytterbium), Sm (samarium), Eu (eurobium), Gd (gadolinium), and Er (erbium)), as well as oxides or glasses of Co (cobalt), Ni (nickel), Li (lithium), B (boron), Na (sodium), K (potassium), and Si (silicon).

[0049] For example, a ceramic material is prepared by wet-mixing a ceramic raw material powder with a compound containing an additive compound, followed by drying and pulverization. For example, the ceramic material obtained as described above may be pulverized as necessary to adjust the particle size, or may be combined with a classification process to adjust the particle size. A dielectric material is obtained by the above process.

[0050] (Lamination process: S2) Next, a binder such as polyvinyl butyral (PVB) resin, an organic solvent such as ethanol or toluene, and a plasticizer are added to the obtained dielectric material and wet mixed. The obtained slurry is used to coat a dielectric green sheet 52 on a substrate 51 by, for example, a die coater method or a doctor blade method, and then dried. The substrate 51 is, for example, a PET (polyethylene terephthalate) film.

[0051] Next, as illustrated in Fig. 9(a), an internal electrode layer pattern 53 is formed on the dielectric green sheet 52. In Fig. 9(a), as an example, four layers of internal electrode layer patterns 53 are formed at predetermined intervals on the dielectric green sheet 52. In this embodiment, the internal electrode layer patterns 53 are formed by sputtering using a target of the main component metal (for example, Ni) of the internal electrode layer 12.

[0052] Next, as illustrated in FIG. 9(b), the coating pattern 54 is formed on the internal electrode layer pattern 53. In this embodiment, the coating pattern 54 is formed by sputtering using a target of a metal (e.g., Cr) of the metal oxide that constitutes the coating 17. If the amount of the coating pattern 54 formed is too large, oxygen defects are induced, and the insulation reliability of the dielectric layer 11 decreases, as in the case where both sides of the internal electrode layer 12 are covered with the coating 17. On the other hand, if the amount of the coating pattern 54 formed is too small, the spheroidization of the main component metal of the internal electrode layer pattern 53 cannot be suppressed, and a decrease in the continuity rate cannot be suppressed. Therefore, the amount of the coating pattern 54 formed relative to the amount of the internal electrode layer pattern 53 is set to 0.1 at % to 5 at %. The amount of film formation of the coating pattern 54 relative to the amount of film formation of the internal electrode layer pattern 53 is expressed as N4 / (N3+N4)×100, where N3 is the number of atoms of the main component metal of the internal electrode layer 12 contained in the internal electrode layer pattern 53, and N4 is the number of atoms of the metal oxide constituting the coating 17 contained in the coating pattern 54. The amount of film formation of the coating pattern 54 relative to the amount of film formation of the internal electrode layer pattern 53 is preferably 3 at % or less, and more preferably 1.5 at % or less.

[0053] The dielectric green sheet 52 on which the internal electrode layer pattern 53 and the coating pattern 54 are formed is defined as a lamination unit.

[0054] Next, while peeling the dielectric green sheet 52 from the substrate 51, the lamination units are stacked as shown in FIG. 9(c). Next, a predetermined number of cover sheets 55 (e.g., 2 to 10 layers) are stacked on top and bottom of the laminate obtained by stacking the lamination units, and are thermocompression bonded, and then cut to predetermined chip dimensions (e.g., 1.0 mm x 0.5 mm). In the example of FIG. 9(c), cutting is performed along the dotted lines. The cover sheet 55 may have the same components as the dielectric green sheet 52, or may contain a different additive compound.

[0055] (Firing process: S3) The ceramic laminate thus obtained was subjected to binder removal treatment in an N2 atmosphere, and then a metal paste that would become the base layer of the external electrodes 20a, 20b was applied by dipping. -5 ~10 -8 The resultant product is fired at 1100 to 1300°C for 10 minutes to 2 hours in a reducing atmosphere of atm. At this time, the main component metal of the coating pattern 54 is oxidized by oxygen in the reducing atmosphere or oxygen in the dielectric material. The main component metal of the coating pattern 54 is more easily oxidized than the main component metal of the internal electrode layer pattern 53. Therefore, the coating 17 is formed before the main component metal of the internal electrode layer pattern 53 is sintered, and firing of the main component metal of the internal electrode layer pattern 53 progresses along the coating 17. This suppresses spheroidization due to over-sintering of the main component metal of the internal electrode layer pattern 53, and can improve the continuity rate of the internal electrode layer 12 obtained after the firing process.

[0056] (Reoxidation treatment step: S4) Thereafter, a re-oxidation treatment may be performed at 600°C to 1000°C in an N2 gas atmosphere.

[0057] (Plating process: S5) Thereafter, the underlying layers of the external electrodes 20a, 20b are plated with a metal coating of Cu, Ni, Sn, etc. Through the above steps, the multilayer ceramic capacitor 100 is completed.

[0058] According to the manufacturing method of the multilayer ceramic capacitor 100 of this embodiment, a coating pattern 54 containing a metal that is more easily oxidized than the main component metal of the internal electrode layer pattern 53 as a main component metal is formed by sputtering on one surface of the internal electrode layer pattern 53, and then fired. As a result, firing of the main component metal of the internal electrode layer pattern 53 progresses along the coating 17 formed by oxidation of the main component metal of the coating pattern 54. This makes it possible to suppress spheroidization due to over-sintering of the main component metal of the internal electrode layer pattern 53, thereby suppressing a decrease in the continuity rate of the internal electrode layer 12. Furthermore, since the coating pattern 54 is formed on one surface of the internal electrode layer pattern 53, the generation of oxygen defects is suppressed compared to when the coating pattern 54 is formed on both surfaces of the internal electrode layer pattern 53, and a dielectric layer 11 with high insulation reliability can be obtained.

[0059] In the above embodiment, the internal electrode layer pattern 53 is formed on the dielectric green sheet 52, and the coating pattern 54 is formed on the internal electrode layer pattern 53, but this is not limited to this. As shown in Figures 10(a) and 10(b), the coating pattern 54 may be formed on the dielectric green sheet 52, and the internal electrode layer pattern 53 may be formed on the coating pattern 54. In this case, the dielectric green sheet 52 on which the coating pattern 54 and the internal electrode layer pattern 53 are formed is used as a lamination unit. Then, while peeling the dielectric green sheet 52 from the base material 51, the lamination units may be laminated as exemplified in Figure 10(c).

[0060] Alternatively, a composite pattern 56 containing the main component metal of the internal electrode layer 12 and the main component metal of the coating 17 may be formed on a dielectric green sheet 52 by sputtering, as shown in Fig. 11(a), using a target of the main component metal of the internal electrode layer 12 and a target of the main component metal of the coating 17. In this case, the dielectric green sheet 52 on which the composite pattern 56 is formed is used as a lamination unit. Then, while peeling the dielectric green sheet 52 from the substrate 51, lamination units may be laminated as shown in Fig. 11(b).

[0061] When a target of the main component metal of the internal electrode layer 12 and a target of the metal of the metal oxide constituting the coating 17 are sputtered simultaneously, the ratio of the metal of the metal oxide constituting the coating 17 to the main component metal of the internal electrode layer 12 is set to 1 at%-5 at%. The ratio of the metal of the metal oxide constituting the coating 17 to the main component metal of the internal electrode layer 12 is expressed as N6 / (N5+N6), where N5 is the number of atoms of the main component metal of the internal electrode layer 12 and N6 is the number of atoms of the metal of the metal oxide constituting the coating 17.

[0062] When the composite pattern 56 is fired in the firing step, a coating 17 is formed mainly on the surface of both sides of the composite pattern 56 that was exposed to the chamber. As a result, firing of the main component metal of the internal electrode layer 12 progresses along the coating 17, so that spheroidization due to over-sintering of the main component metal of the internal electrode layer 12 can be suppressed, and the continuity rate of the internal electrode layer 12 can be improved.

[0063] If the proportion of the main component metal of the coating 17 is less than 1 at % during sputtering, a sufficient amount of the coating 17 will not be formed on the upper surface of the internal electrode layer 12. In this case, the main component metal of the internal electrode layer 12 cannot be prevented from becoming spheroidized, which will not contribute to improving the continuity ratio of the internal electrode layer 12. The proportion of the main component metal of the coating 17 is preferably 1 to 3 at %. In this case, the continuity ratio of the internal electrode layer 12 will be further improved, and deterioration of reliability due to the main component metal of the coating 17 will be suppressed.

[0064] In the above embodiments, a multilayer ceramic capacitor has been described as an example of a ceramic electronic component, but the present invention is not limited to this. For example, other electronic components such as a varistor or a thermistor may also be used. [Example]

[0065] The multilayer ceramic capacitor according to the embodiment was fabricated and its characteristics were examined.

[0066] Example 1 Additives were added to barium titanate powder, which was then thoroughly wet-mixed and pulverized in a ball mill to obtain a dielectric material. A butyral-based organic binder and toluene and ethyl alcohol solvents were added to the dielectric material, and a dielectric green sheet was then applied to a PET substrate using the doctor blade method. A 200 nm-thick composite pattern was formed on the surface of the dielectric green sheet by sputtering. More specifically, a composite layer of Ni and Cr was formed. The ratio of the Cr target to the Ni target was 3.1 at%. A metal mask method was used for patterning. Ten dielectric green sheets with composite patterns were stacked so that the composite patterns were alternately offset, and then cut to the specified size. A metal conductive paste for external electrodes was applied to the two end faces where the composite patterns were exposed, and the resulting multilayer ceramic capacitor was obtained by firing.

[0067] (Comparative Example 1) In Comparative Example 1, when forming the internal electrode layer pattern, a film of 200 nm was formed using only Ni. The other conditions were the same as in Example 1.

[0068] The continuity ratio of the internal electrode layers was measured for Example 1 and Comparative Example 1. Fig. 12 is a diagram showing the continuity ratio. As illustrated in Fig. 12, in an observation area of ​​length L0 in a certain internal electrode layer 12, the lengths L1, L2, . . . , Ln of the metal parts are measured and summed, and ΣLn / L0, which is the proportion of the metal parts, can be defined as the continuity ratio of the layer.

[0069] FIG. 13(a) is a cross-sectional SEM image of Comparative Example 1. FIG. 13(b) is a cross-sectional SEM image of Example 1. From the comparison results between FIG. 13(a) and FIG. 13(b), a clear difference in the continuity ratio of the internal electrode layers can be confirmed, and it can be understood that the continuity ratio was improved by disposing a Cr oxide film between the dielectric layer and the internal electrode layer. In Example 1, the continuity ratio was measured to be 98%. In Comparative Example 1, the continuity ratio was measured to be 70%.

[0070] Although the embodiments of the present invention have been described in detail above, the present invention is not limited to such specific embodiments, and various modifications and variations are possible within the scope of the gist of the present invention as defined in the claims. [Explanation of symbols]

[0071] 10 stacked chips 11 Dielectric layer 12 Internal electrode layer 13 Cover Layer 17 Coating 20a,20b external electrode 51 Base material 52 Dielectric green sheet 53 Internal electrode layer pattern 54 Coating Pattern 56 Composite Pattern 100 Multilayer ceramic capacitors

Claims

1. a laminated chip in which dielectric layers mainly made of ceramic and internal electrode layers made of an internal electrode material mainly made of a first metal are alternately laminated; the internal electrode layer has a first surface and a second surface facing the first surface in the same stacking direction of the internal electrode layer, the entire area of ​​the first surface of the internal electrode layer made of the internal electrode material is covered with a metal oxide film made of a second metal that is more easily oxidized than the first metal, and the second surface of the internal electrode layer made of the internal electrode material is not covered with the metal oxide film, or the first surface and the second surface of the internal electrode layer are covered with the metal oxide film made of a second metal that is more easily oxidized than the first metal, and the area of ​​the metal oxide film covering the second surface is smaller than the area of ​​the metal oxide film covering the first surface; A ceramic electronic component characterized by:

2. 2. The ceramic electronic component according to claim 1, wherein the first metal is nickel.

3. 3. The ceramic electronic component according to claim 1, wherein the metal oxide film is a chromium oxide film.

4. 4. The ceramic electronic component according to claim 1, wherein the ratio of the metal oxide film to the internal electrode layers is 0.1 at % to 5 at %.

5. 5. The ceramic electronic component according to claim 4, wherein the ratio of the metal oxide film to the internal electrode layers is 3 at % or less.

6. 5. The ceramic electronic component according to claim 4, wherein the ratio of the metal oxide film to the internal electrode layers is 1.5 at % or less.

7. a step of forming a laminate unit by sputtering an internal electrode layer pattern made of an internal electrode material mainly composed of a first metal on a dielectric green sheet, and a coating pattern mainly composed of a second metal that is more easily oxidized than the first metal on one of a first surface and a second surface of the internal electrode layer pattern; forming a laminate by stacking a plurality of the lamination units; and firing the laminate to obtain a laminated chip in which dielectric layers mainly composed of ceramic and internal electrode layers made of the internal electrode material mainly composed of the first metal are alternately laminated, the first surface and the second surface face each other in a stacking direction of the plurality of stacking units, the entire area of ​​the first surface of the internal electrode layer made of the internal electrode material is covered with a metal oxide film made of the second metal, and the second surface of the internal electrode layer made of the internal electrode material is not covered with the metal oxide film, or the first surface and the second surface of the internal electrode layer made of the internal electrode material are covered with the metal oxide film made of the second metal, and an area of ​​the metal oxide film covering the second surface is smaller than an area of ​​the metal oxide film covering the first surface; A method for manufacturing a ceramic electronic component, comprising:

8. 8. The method for manufacturing a ceramic electronic component according to claim 7, wherein the ratio of the coating pattern to the internal electrode layer pattern is 0.1 at % to 5 at %.

9. A process for forming a laminated unit in which an internal electrode layer pattern is formed on a dielectric green sheet by sputtering a composite film containing a first metal and a second metal that is more easily oxidized than the first metal, with the proportion of the second metal being 1 at% to 5 at%; forming a laminate by stacking a plurality of the lamination units; and firing the laminate to obtain a laminated chip in which dielectric layers mainly composed of ceramic and internal electrode layers made of an internal electrode material mainly composed of the first metal are alternately laminated, the internal electrode layer has a first surface and a second surface facing the first surface in the same stacking direction of the internal electrode layer, the entire area of ​​the first surface of the internal electrode layer made of the internal electrode material is covered with a metal oxide film made of the second metal which is more easily oxidized than the first metal, and the second surface of the internal electrode layer made of the internal electrode material is not covered with the metal oxide film, or the first surface and the second surface of the internal electrode layer are covered with the metal oxide film made of the second metal which is more easily oxidized than the first metal, and the area of ​​the metal oxide film covering the second surface is smaller than the area of ​​the metal oxide film covering the first surface; A method for manufacturing a ceramic electronic component, comprising:

10. The first metal is nickel and the second metal is chromium. The method for manufacturing a ceramic electronic component according to any one of claims 7 to 9.

Images