Method for manufacturing semiconductor devices and semiconductor manufacturing apparatus

Abstract

To provide a manufacturing method of a semiconductor device, capable of forming a flat amorphous silicon film while using a higher order silane as an original gas, and to provide a semiconductor manufacturing apparatus used for the same.SOLUTION: A manufacturing method of a semiconductor device includes a film formation step of forming an amorphous silicon film by a thermal CVD onto a wafer front surface arranged in a cylinder processing container whose volume in a heating region is 100 cm3 or less and whose inner diameter is 1.5 cm or more and 4 cm or less under the condition that a total pressure is 1.0 Pa or more and 150 Pa or less, a partial pressure of a higher order silane of trisilane or larger is 1.0 Pa or more and 100 Pa or less, and a temperature is 550°C or more and 650°C or less. Also, the device also contains: an excitation mechanism that is provided to an upper direction of the processing part and excites a cleaning gas; an original gas supply mechanism that supplies an original gas into the processing container; a mechanism that supplies a cleaning gas into the processing container; and an exhaust mechanism that exhausts it into the processing container. The inner diameter from a plasma excitation region to a heating region in the processing container is 1.5 cm or more and 4 cm or less.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a method for manufacturing a semiconductor device having a film deposition step for amorphous silicon films, and a semiconductor manufacturing apparatus used for manufacturing the same. [Background technology]

[0002] Thermal CVD (Chemical Vapor Deposition) is one method used to deposit amorphous silicon and polysilicon films. In these films, silane (SiH4) or disilane (Si2H6) is generally used as the raw material gas. However, silane and disilane are extremely flammable and dangerous gases. Since both gases have boiling points lower than room temperature at room temperature and pressure (boiling points: silane -111.8°C, disilane -14.5°C), they are usually filled into cylinders under high pressure and then extracted for use. For this reason, silane and disilane are designated as specified high-pressure gases in Japan, and using these gases requires advanced safety measures and proper treatment of exhaust gases. As a result, the entire system, including the supply and exhaust systems, is large-scale and costly, and if these gases leak, the environmental impact is also significant.

[0003] Thermal CVD methods using higher-order silanes such as trisilane (Si3H8, boiling point 52.9°C), which are liquids at room temperature and pressure, are also being investigated. Trisilane is easier to handle than silanes and disilanes because it is not as flammable and combustible as silanes and disilanes, and because it is a liquid, it does not need to be filled into high-pressure cylinders. However, thermal CVD methods using higher-order silanes as raw material gases have difficulty achieving the level of smoothness and cleanliness required in the semiconductor field, and have not yet been put into practical use. For example, Non-Patent Literature 1 discloses that in thermal CVD using a CVD apparatus for 8-inch wafers, disilane (Si2H6) could be deposited at a pressure of 10.6 Pa (without carrier gas), but islands were formed with trisilane, and that although trisilane could be deposited at a pressure of 0.01 Pa or less, the deposition rate decreased significantly. Non-patent document 2 describes that in thermal CVD using a CVD apparatus for 8-inch wafers, when trisilane was used as the raw material gas and film deposition was performed under various conditions, islands were formed. It states that trisilane (Si3H8) decomposes into silane gas (SiH4) and Si atoms in the gas phase, and the Si atoms collide in the gas phase to form clusters, which adhere to the film and cause islands. Thus, when using higher-order silanes, there is a problem in that particles and islands are generated due to collisions between Si atoms.

[0004] Furthermore, Patent Document 1 describes that in a hot-wall type reactor that heats the processing vessel, although the deposition rate is high, impurities are easily incorporated into the silicon film, making it difficult to improve the film quality, and silicon particles accumulate on the surface (forming islands), resulting in a rough surface. To solve these problems, a method for manufacturing a silicon film using a cold-wall type reactor with a higher-order silane of trisilane or higher as the raw material gas is disclosed. However, although islands and particles do occur in the manufacturing method using the cold-wall type reactor described in Patent Document 1, they were only of a size that was not problematic at the level required for semiconductors at the time of filing Patent Document 1 (1986), and do not satisfy the current semiconductor quality requirements.

[0005] Furthermore, it is known that particle generation can be suppressed by using chlorosilane compounds such as dichlorosilane (SiH2Cl2) and trichlorosilane (SiHCl3) as raw material gases. This is because the chlorine (Cl) halogen atom contained in these gases is highly reactive, forming highly volatile silicon chlorides such as SiCl4. However, dichlorosilane and trichlorosilane are highly hazardous gases designated as special material gases in Japan. Moreover, chlorosilane compounds generate corrosive hydrogen chloride gas when they come into contact with water, which can easily corrode pipes and cause rust. This necessitates frequent pipe replacement to prevent contamination from corroded areas, resulting in high costs. [Prior art documents] [Patent Documents]

[0006] [Patent Document 1] Japanese Patent Application Publication No. 63-3414 [Non-patent literature]

[0007] [Non-Patent Document 1] Dae-Seop Byeon, et al, "Epitaxial Growth of Si and SiGe Using High-Order Silanes without a Carrier Gas at Low Temperatures via UHVCVDand LPCVD", Coatings, 2021, 11(5), 568 [Non-Patent Document 2] B.Vincent, et al, "Low temperature Si homo-epitaxy by reduced pressure chemical vapor deposition using dichlorosilane, silane and trisilane", J Crystal Growth 312 (2010) 2671-2676 [Overview of the project] [Problems that the invention aims to solve]

[0008] The objective is to provide a semiconductor device manufacturing method that can deposit a flat amorphous silicon film using a higher-order silane as a raw material gas, and a semiconductor manufacturing apparatus used for this manufacturing. [Means for solving the problem]

[0009] The means for solving the problems of the present invention are as follows. 1. The volume of the heating area is 100 cm³. 3 The wafer surface, placed inside a cylindrical processing container having the following characteristics and an inner diameter of 1.5 cm to 4 cm, A method for manufacturing a semiconductor device, characterized by comprising a film formation step of forming an amorphous silicon film by thermal CVD under conditions of a total pressure of 150 Pa or less, a partial pressure of trisilane or higher-order silanes of 1.0 Pa or more and 100 Pa or less, and a temperature of 550°C or more and 650°C or less. 2. The method for manufacturing a semiconductor device according to 1, characterized by comprising an annealing step of annealing the amorphous silicon film at 580°C or higher under an inert gas atmosphere to form a polysilicon film. 3. The method for manufacturing a semiconductor device according to 1. or 2., characterized in that the higher-order silane is trisilane. 4. The method for manufacturing a semiconductor device according to 1. or 2., characterized in that the wafer has a diameter of 1 inch or less. 5. A cylindrical processing container, A stage is placed inside the processing container and holds the wafer, A heating unit for heating a wafer held in a predetermined position within the processing container, An excitation mechanism is provided above the heating section to excite the cleaning gas, A raw material gas supply mechanism that supplies raw material gas into the processing container, A cleaning gas supply mechanism that supplies cleaning gas into the processing container, An exhaust mechanism for exhausting the contents of the processing container, having at least A semiconductor manufacturing apparatus, wherein an inner diameter from a plasma excitation region to a heating region of the processing vessel is 1.5 cm or more and 4 cm or less.

Advantages of the Invention

[0010] The method for manufacturing a semiconductor device of the present invention can form an amorphous silicon film with a flat and clean surface while using higher-order silane as a raw material, because the processing vessel has a small capacity and a relatively short gas-phase reaction region compared with the conventional method using a large processing vessel. Further, by annealing the obtained amorphous silicon film, a polysilicon film with a flat and clean surface can be obtained. The method for manufacturing a semiconductor device of the present invention has a small processing vessel, so that the time required for heating and cooling is short and the throughput is high, and the running costs such as electricity charges can be reduced. The method for manufacturing a semiconductor device of the present invention uses higher-order silane which is liquid at room temperature. Compared with the conventionally used silane and disilane, it has excellent handleability and can greatly reduce the risk that workers and the like are exposed to the source gas. Since higher-order silane is liquid at room temperature, the space required for storage can be greatly reduced compared with gas cylinders when using silane and disilane which are gases at room temperature, and miniaturization and cost reduction of the apparatus can be realized. Since higher-order silane has no corrosiveness, the piping is not easily rusted and the exhaust treatment is also easy.

[0011] The semiconductor manufacturing apparatus of the present invention has a heating unit below a cylindrical processing vessel and a plasma excitation mechanism for exciting cleaning plasma above. With this configuration, in the semiconductor manufacturing apparatus of the present invention, since the diameter of the plasma excitation unit and the diameter of the processing vessel are substantially the same, the inner surface of the processing vessel can be efficiently cleaned by the cleaning plasma.

Brief Description of the Drawings

[0012] [Figure 1] Schematic diagram of the semiconductor manufacturing apparatus of the present invention. [Figure 2]Optical microscope image and atomic force microscope image of the amorphous silicon film obtained in Experiment 1. [Figure 3] Image showing the appearance of the reaction vessel before and after cleaning in Experiment 1. [Figure 4] Graph showing the relationship between the annealing temperature and the crystallization rate in Experiment 2.

Embodiment for Carrying Out the Invention

[0013] The method for manufacturing a semiconductor of the present invention (hereinafter also referred to as the manufacturing method) is as follows. On the surface of a wafer disposed in a cylindrical processing vessel having a volume of 100 cm 3 or less and an inner diameter of 1.5 cm or more and 4 cm or less, a film formation step of forming an amorphous silicon film by thermal CVD under the conditions of a total pressure of 150 Pa or less, a partial pressure of a higher-order silane such as trisilane of 1.0 Pa or more and 100 Pa or less, and a temperature of 550°C or more and 650°C or less is provided.

[0014] Hereinafter, the method for manufacturing a semiconductor device of the present invention will be described using a minimal fab device, which is an embodiment of the semiconductor manufacturing apparatus of the present invention. The minimal fab device is a device that constitutes a locally cleaned ultra-small device production system (minimal fab: see Japanese Patent No. 5361002, Japanese Patent No. 5780531, etc.) that uses a wafer with a diameter of 0.5 inches (12.5 mm).

[0015] The minimal fab device is for handling wafers with a diameter of 0.5 inches (12.5 mm), but the diameter of the wafer used in the manufacturing method of the present invention is not limited to 0.5 inches, and a wafer that can be accommodated in the processing vessel used in the present invention can be used. However, it is preferable that the diameter of the wafer is 1 inch or less. When the diameter of the wafer is reduced, the volume of the processing vessel for accommodating the wafer can be reduced, so that the temperature increase and decrease of the CVD apparatus heated to a high temperature, particularly the time required for temperature decrease, can be shortened, and the cycle time can be shortened. The semiconductor device manufacturing method of the present invention can be preferably carried out using the semiconductor manufacturing apparatus of the present invention, but it can also be carried out using other semiconductor manufacturing apparatuses. Furthermore, the semiconductor manufacturing apparatus of the present invention can be preferably used for the semiconductor device manufacturing method of the present invention, but it can also be used for other semiconductor device manufacturing methods.

[0016] Figure 1 shows a schematic diagram of a semiconductor manufacturing apparatus 100, which is a minimal fab apparatus and is one embodiment of the semiconductor manufacturing apparatus of the present invention. The semiconductor manufacturing apparatus 100 includes a cylindrical processing container 1, a stage 2 in which a 0.5-inch wafer W is held at a predetermined position inside the processing container 1, a heating section 3 provided around the processing container 1, a plasma excitation mechanism 4 provided above the heating section 3, a raw material gas supply mechanism 5, a cleaning gas supply mechanism 6, and an inert gas supply mechanism 7 that supply raw material gas, cleaning gas, and inert gas, respectively, into the processing container 1, and an exhaust mechanism P for exhausting the inside of the processing container 1. The heating region 13 is the area between the upper and lower ends of the heating element of the heating section 3 within the processing container 1, and the plasma excitation region 14 is the area between the upper and lower ends of the coil 41 of the plasma excitation mechanism 4. In other words, the processing container 1 has a plasma excitation region 14 at the top and a heating region 13 below it.

[0017] The shape of the processing container 1 can be cylindrical, and can be a cylinder, elliptical cylinder, polygonal cylinder, etc. However, since wafers W used in semiconductor manufacturing are usually circular, it is preferable that the container be cylindrical or a regular polygonal cylinder with 6 or more vertices, and most preferably cylindrical. The inner diameter of the processing container 1 refers to the diameter of a circle with the same area as the radial cross-sectional area of ​​the inner surface of the processing container 1. That is, if the radial cross-sectional area is represented by S, the inner diameter d is d = 2 × (S / π). 1 / 2 It is represented as follows.

[0018] The processing vessel 1 has an inner diameter of 1.5 cm or more and 4 cm or less from the plasma excitation region 14 to the heating region 13 (hereinafter, the portion from the plasma excitation region 14 to the heating region 13 is also referred to as the processing region). The processing vessel 1 only needs to have an inner diameter of 1.5 cm or more and 4 cm or less in the processing region, and the inner diameter of the other parts, i.e., above the plasma excitation region 14 and below the heating region 13, is not particularly limited. The inner diameter of the processing region of the processing vessel 1 may be within the range of 1.5 to 4 cm, may be a constant value, or may vary within the range of 1.5 to 4 cm.

[0019] Stage 2 is placed inside the processing container 1 and holds the wafer W on its upper surface. Stage 2 extends from below and moves up and down within the processing container 1 to hold the wafer W at a predetermined heating position. A temperature sensor (not shown) is connected inside Stage 2, and by controlling the heating unit 3 in response to the signal from this temperature sensor, the wafer can be heated to a predetermined temperature. The materials forming the processing container 1 and stage 2 can be any materials that have sufficient heat resistance to withstand the manufacturing method of the present invention and do not contaminate the wafer W, etc. For example, insulators such as quartz, glass, and alumina, or metals such as stainless steel can be used. The processing container 1 and stage 2 can be made of the same or different materials.

[0020] The heating unit 3 is arranged to surround the processing container 1. The heating unit 3 only needs to be capable of heating to a predetermined temperature for thermal CVD processing, and known methods such as resistance heating or infrared heating can be used. The wafer W is held within the heating region 13 by the stage 2, but it is preferable from the viewpoint of temperature control that it be held near the axial center of the heating region 13. Specifically, if the axial upper end position of the heating region 13 is represented as 0% and the total length as 100%, it is preferable to hold the wafer W in the 30-70% portion, more preferably in the 35-65% portion, and even more preferably in the 40-60% portion.

[0021] As described above, the manufacturing method of the present invention is such that the volume of the heating region 13 is 100 cm³. 3 A cylindrical processing container 1 is used, having the following dimensions and an inner diameter of 1.5 cm to 4 cm. In the manufacturing method of the present invention, the volume of the heating region 13 is small and atomic movement is restricted, so the distance atomic movement within the heating region 13 is short. In the manufacturing method of the present invention, the ratio of the distance atomic movement to the mean free path (movement distance / mean free path) in the heating region 13 is small, so the frequency of atomic collisions is low, and the generation of particles and islands due to atomic collisions originating from the raw material gas can be suppressed, which is particularly useful when using trisilane or higher-order silanes as the raw material gas. For this reason, the volume of the heating region 13 is 80 cm³. 3 Preferably, it is 60cm 3 More preferably, the following: 40cm 3 More preferably, the following: 35 cm 3 The following is even more preferable. The inner diameter of the heating region 13 is preferably 3.5 cm or less, more preferably 3.0 cm or less, and even more preferably 2.5 cm or less. Since the wafer is held in the heating region 13, the inner diameter of the heating region 13 is preferably 1.2 times or more the diameter of the wafer W, more preferably 1.4 times or more, and even more preferably 1.6 times or more.

[0022] The temperature of the heating region can be appropriately selected depending on the type of raw material gas. For example, when using trisilane, the temperature is between 550°C and 650°C. While higher temperatures result in a faster deposition rate, the surface of the resulting film tends to be rougher. Therefore, the temperature of the heating region can be adjusted according to the deposition speed and the smoothness of the resulting film. Below 550°C, the deposition rate is slow, which has the disadvantage of a longer process time in practical applications.

[0023] The plasma excitation mechanism 4 is positioned above the heating region 13, with a coil 41 surrounding the outer circumference of the processing container 1, forming a plasma excitation region 14 where the cleaning gas is excited. The plasma excitation mechanism 4 can be any known device capable of exciting the cleaning gas. In this embodiment, the excitation mechanism has a coil 41 for exciting an inductively coupled plasma. In thermal CVD, atoms originating from the raw material gas accumulate not only on the wafer W surface but also on the inner surface of the heating region 13, forming a thin film. By exciting the cleaning gas with the plasma excitation mechanism 4 to generate a cleaning plasma, and irradiating the lower heating region 13 with the cleaning plasma generated in the plasma excitation region 14, the thin film accumulated on the inner surface of the heating region 13 can be removed. This prevents the thin film from peeling off from the inner surface of the heating region 13 during thermal CVD, which would generate fine fragments and contaminate the wafer W surface.

[0024] The processing vessel 1 has an inner diameter of 1.5 cm to 4 cm from the plasma excitation region 14 to the heating region 13. In the semiconductor manufacturing apparatus 100 of the present invention, because the inner diameter of the processing vessel 1 from the plasma excitation region 14 to the heating region 13 is small, the distance between the cleaning plasma excited in the plasma excitation region 14 and the inner surface of the processing vessel 1 in the heating region 13 is short. Therefore, the cleaning plasma can be efficiently irradiated onto the inner surface of the processing vessel 1, and the film deposited on the inner surface of the heating region 13 can be removed in a short time. In this case, in order to efficiently irradiate the entire inner surface of the heating region 13 with the cleaning plasma, it is preferable that the inner diameter of the functional region be the same diameter or decreases towards the bottom, and more preferably the same diameter. It is also possible to make the diameter larger towards the bottom, but in that case, it is preferable that the axial cross-sectional shape of the inner surface of the heating region 13 be flat (constant slope). With this configuration, there are no shadowed areas when viewed from above, so there are no areas that are difficult to irradiate with the cleaning plasma flowing downwards, and cleaning can be performed efficiently.

[0025] The raw material gas supply mechanism 5, the cleaning gas supply mechanism 6, and the inert gas supply mechanism 7 supply respective gases. A flow meter (not shown) is provided upstream thereof, and each gas can be supplied in an arbitrary amount. Further, a plurality of gases can be supplied while adjusting the ratio thereof according to the ratio. In FIG. 1, each gas merges upstream and is supplied from one air supply port, but it can also be supplied from separate air supply ports. A pressure measurement sensor (not shown) is connected to the processing vessel 1, and the pressure inside the processing vessel 1 can be controlled by controlling the exhaust mechanism P according to the signal from this pressure measurement sensor.

[0026] As the raw material gas, those that can form a film by thermal CVD can be used without particular limitation. For example, silane, disilane, trisilane, tetrasilane (Si4H 10 ), cyclohexasilane (Si6H 12 ), TEOS (tetraethoxysilicate), and WF6 can be used. Among these, it is preferable to use higher-order silanes such as trisilane or higher, which are likely to generate particles and islands, and it is more preferable to use trisilane, which has the lowest boiling point among the higher-order silanes and is thus easy to control the supply. The cleaning gas can be used without particular limitation as long as it can remove the film deposited on the inner surface of the heating region 13 by plasma. For example, when an amorphous silicon film or a polysilicon film is formed on the inner surface of the heating region 13, H2, SF6, CF4, NF3, etc. can be used, and these gases can also be used when a silicon nitride film or a tungsten film is deposited. As the inert gas, nitrogen, argon, helium, neon, etc. can be used.

[0027] When using a higher-order silane as the raw material gas, the partial pressure of the higher-order silane is 1.0 Pa or more and 100 Pa or less. Here, the mean free path (λ) of the raw material gas is represented by the following formula. λ = kT / (2 1 / 2 pρ) k: Boltzmann coefficient T: Temperature (K) p: Pressure (Pa) ρ: Collision cross section (m 2 ) As shown in the above formula, the mean free path decreases as the pressure increases. When the partial pressure of the higher-order silane exceeds 100 Pa, the mean free path becomes shorter, so the ratio of the distance traveled by the source gas atoms to the mean free path (travel distance / mean free path) becomes larger, making it easier for particles and islands to occur. On the other hand, when the partial pressure of the higher-order silane is less than 1.0 Pa, the deposition rate becomes too slow, and the time required for film formation becomes too long. The partial pressure of the higher-order silane is not particularly limited as long as the flatness required for the amorphous silicon film is ensured, but it is preferably 5 Pa or more, more preferably 10 Pa or more, even more preferably 15 Pa or more, and preferably 80 Pa or less, and even more preferably 60 Pa or less. The flow rate of the higher-order silane can be adjusted according to the total pressure, partial pressure, etc., and is, for example, between 0.1 sccm and 2 sccm.

[0028] When using higher-order silane as the raw material gas, the total pressure is 150 Pa or less. The total pressure can be adjusted by the supply rate of the higher-order silane raw material gas, or the combined supply rate of the raw material gas and inert gas, and the exhaust rate.

[0029] The manufacturing method of the present invention uses a processing vessel with a small volume and small diameter, resulting in a small ratio (transfer distance / mean free path) of the migration distance of Si atoms derived from the source gas, higher-order silane. This reduces the frequency of collisions between Si atoms in the gas phase, suppressing the generation of particles and islands. Therefore, even when using higher-order silane as the source gas, a flat and clean amorphous silicon film can be formed. The amorphous silicon film obtained by the manufacturing method of the present invention preferably has an arithmetic mean height (Ra) of 3 nm or less, more preferably 2 nm or less, and even more preferably 1 nm or less. In this specification, the arithmetic mean height (Ra) is the value calculated from the contour curve obtained by scanning a 3 μm square region with an atomic force microscope (AFM). That is, it is expressed by the following formula (1). Formula 1

[0030] JPEG0007832429000001.jpg16170 (where n is the number of measurement positions within a 3 μm square region (131072 points in this example), z i This represents the difference between the contour curve at the measurement point and the actual height data.

[0031] The manufacturing method of the present invention may include an annealing step in which an amorphous silicon film is annealed at 580°C or higher under an inert gas atmosphere to form a polysilicon film. This annealing process allows the obtained amorphous silicon film to be crystallized into a polysilicon film. The annealing temperature and time are not particularly limited, as long as crystallization progresses, but the higher the annealing temperature, the shorter the time required for crystallization. Also, the higher the deposition temperature of the amorphous silicon film, the easier it is for crystallization to proceed. At higher deposition temperatures, the migration of atoms due to thermal energy during film formation is promoted, and although it does not reach crystallization and remains amorphous, it is thought that each silicon atom has moved to a position close to its predetermined position in the crystal lattice. [Examples]

[0032] "Experiment 1" Using a semiconductor manufacturing apparatus that is a minimal fab system with a configuration similar to that shown in Figure 1, an amorphous silicon film with a thickness of approximately 160 nm was deposited by thermal CVD using trisilane (Si3H8) as the raw material gas and argon as the inert gas, with a trisilane / argon ratio of 0.4 / 2 sccm and a temperature of 600°C, while changing the total pressure and the partial pressure of trisilane. The processing vessel of the semiconductor manufacturing apparatus used was a quartz cylinder with an inner diameter of 2.1 cm, and the volume of the heating area was 34.7 cm³. 3 The heating region has a length of 10 cm, and the wafer is held in the axial center of this region.

[0033] The obtained amorphous silicon film surfaces were observed with an optical microscope to investigate the presence or absence of islands. In addition, the amorphous silicon films obtained in Examples 3-5, 7, and Comparative Examples 1 and 2 were observed using an electron force microscope, and their arithmetic mean height (Ra) was calculated. The manufacturing conditions and results are shown in Table 1. Furthermore, optical microscope images (20x magnification) and atomic force microscope images of Example 7, Comparative Examples 1 and 2 are shown in Figure 2. The maximum value on the vertical axis of the atomic force microscope images is 300 nm.

[0034] [Table 1]

[0035] Using the manufacturing methods described in Examples 1 to 7 of the present invention, we were able to obtain a flat, clean amorphous silicon film without islands. In contrast, the manufacturing methods of Comparative Examples 1 and 2 resulted in the formation of islands in the obtained amorphous silicon film.

[0036] In Experiment 1 described above, for each film deposition under different conditions, SF6 was flowed as a cleaning gas at 3 sccm, the pressure was set to 10 Pa, and 30 W of high-frequency power at a frequency of 13.56 MHz was introduced into the coil for inductively coupled plasma excitation to excite the SF6 cleaning plasma, followed by a 10-minute cleaning process. Figure 3 shows the appearance of the reaction vessel before and after cleaning. The amorphous silicon film adhering to the inner surface of the heated area was successfully removed by cleaning with a cleaning plasma.

[0037] "Experiment 2" Using the same semiconductor manufacturing apparatus as in Experiment 1, amorphous silicon films with a thickness of approximately 200 nm were deposited at different deposition temperatures, with a trisilane / argon ratio of 0.4 / 2 sccm, a total pressure of 80 Pa, and a trisilane partial pressure of 13.3 Pa. After measuring the crystallinity of the obtained amorphous silicon film, it was annealed under a nitrogen atmosphere at 580°C for 24 hours, and the crystallinity after annealing was measured. The results are shown in Table 2. [Table 2]

[0038] The manufacturing method of the present invention made it possible to obtain a completely amorphous film with a crystallinity of 0%. By annealing this completely amorphous film, a silicon film was obtained. Furthermore, it was confirmed that crystallization progressed more easily at higher deposition temperatures.

[0039] "Experiment 3" Using the same semiconductor manufacturing apparatus as in Experiment 1, film deposition was performed at temperatures ranging from 580 to 640°C in 20°C increments, with a trisilane / argon ratio of 0.4 / 2 sccm, a total pressure of 40 Pa, a trisilane partial pressure of 6.7 Pa, and an amorphous silicon film with a thickness of approximately 150 nm. Subsequently, the supply of trisilane was switched off and only argon was supplied. The temperature was raised to the predetermined annealing temperature over approximately 5 minutes, and the annealing process was performed for 10 minutes. The crystallization rate after the annealing process was then determined. The results are shown in Figure 4.

[0040] Crystallization was achieved in a short time by performing an annealing treatment immediately after deposition of the amorphous silicon film. It was confirmed that crystallization progressed more easily with higher annealing temperatures, and also that crystallization progressed more easily with higher film deposition temperatures. [Explanation of Symbols]

[0041] Semiconductor manufacturing equipment 100 Processing container 1 heating area 13 Plasma excitation region 14 Stage 2 Heating section 3 Plasma excitation mechanism 4 Coil 41 Raw material gas supply mechanism 5 Cleaning gas supply mechanism 6 Inert gas supply mechanism 7 Exhaust mechanism P

Claims

1. The volume of the heating area is 100 cm³ ３ The wafer surface, placed inside a cylindrical processing container having the following characteristics and an inner diameter of 1.5 cm to 4 cm, A method for manufacturing a semiconductor device, characterized by comprising a film formation step of forming an amorphous silicon film by thermal CVD under conditions of a total pressure of 150 Pa or less, a partial pressure of trisilane or higher-order silanes of 1.0 Pa or more and 100 Pa or less, and a temperature of 550°C or more and 650°C or less.

2. The method for manufacturing a semiconductor device according to claim 1, characterized by comprising an annealing step of annealing the amorphous silicon film at 580°C or higher under an inert gas atmosphere to form a polysilicon film.

3. The method for manufacturing a semiconductor device according to claim 1 or 2, characterized in that the higher-order silane is trisilane.

4. The method for manufacturing a semiconductor device according to claim 1 or 2, characterized in that the wafer has a diameter of 1 inch or less.

5. A cylindrical processing container, A stage is placed inside the processing container and holds the wafer, A heating unit for heating a wafer held in a predetermined position within the processing container, An excitation mechanism is provided above the heating section to excite the cleaning gas, A raw material gas supply mechanism that supplies raw material gas into the processing container, A cleaning gas supply mechanism that supplies cleaning gas into the processing container, An exhaust mechanism for exhausting the contents of the processing container, Having at least, A semiconductor manufacturing apparatus characterized in that the inner diameter of the processing vessel from the plasma excitation region to the heating region is 1.5 cm or more and 4 cm or less.

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