Semiconductor light-emitting device and bonded structure

Abstract

To provide a semiconductor light emitting device that exhibits high reliability of a bonded surface even if the semiconductor light emitting device has a structure where a submount substrate, on which a light emitting element has been mounted, is ultrasonically bonded to a metal substrate.SOLUTION: A semiconductor light emitting device comprises: a light emitting element; a ceramic submount substrate on which the light emitting element is mounted; and a metal mounting substrate on which the submount substrate is mounted. The submount substrate has a metal layer on its bonded surface that is bonded to the mounting substrate. The metal layer of the submount substrate and the mounting substrate are directly bonded without any bonding material. The bonded surface contains voids. The content ratio of the voids is higher in a central region than in a peripheral region within the main plane in the bonded surface.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a semiconductor light-emitting device having a structure in which a submount substrate on which a semiconductor light-emitting element is mounted is directly bonded to a metal substrate.

Background Art

[0002] Conventionally, a semiconductor light-emitting device in which a submount substrate on which a light-emitting element is die-bonded is mounted on a metal mounting substrate having excellent thermal conductivity is known. As the submount substrate, a ceramic substrate such as aluminum nitride having metal layers provided on the upper and lower surfaces is generally used. In the metal mounting substrate, a wiring pattern is formed on the surface of the metal substrate via an insulating layer. When mounting the submount substrate on the metal mounting substrate, an adhesive having a high thermal conductivity (solder, metal bumps or a heat-conductive adhesive containing a metal filler) is used.

[0003] In the case of solder bonding, for example, a solder material is printed on the metal substrate in a predetermined pattern, the submount substrate is set thereon, and a bonding portion is formed through a process of heating (230°C to 260°C) in a reflow furnace or the like.

[0004] In the case of metal bump bonding, for example, gold balls of about 10 to 100 μm are ultrasonically bonded to the metal substrate at intervals of 10 to 100 μm or more, and then the submount substrate is set thereon, and bump bonding is performed by ultrasonic waves.

[0005] In the case of bonding with a silver filler resin, for example, the silver filler resin is printed on the metal substrate, the submount substrate is set thereon, and heat curing (50°C to 150°C, about 2 hours) is performed for bonding.

[0006] Furthermore, as described in Patent Documents 1 and 2, ultrasonic bonding technology is known for directly joining two metal materials without using adhesives. Patent Document 3 discloses ultrasonic bonding of the electrode pads of a bare chip light-emitting element to the pattern electrodes of a submount substrate. Patent Document 4 discloses ultrasonic bonding of the lid material and frame of a package that seals a light-emitting element. [Prior art documents] [Patent Documents]

[0007] [Patent Document 1] Japanese Patent Publication No. 1999-010362 [Patent Document 2] Japanese Patent Publication No. 2010-023052 [Patent Document 3] Japanese Patent Publication No. 2022-065415 [Patent Document 4] Japanese Patent Publication No. 2022-018490 [Overview of the project] [Problems that the invention aims to solve]

[0008] When soldering a submount substrate with die-bonded light-emitting elements to a metal substrate, the solder thickness distribution at the joint can cause an angle of inclination on the light-emitting surface, resulting in defective products. Furthermore, if the solder thickness is thin (e.g., less than 100μm), the solder's crack resistance deteriorates, and it may not withstand thermal shock, leading to fracture of the solder joint. Also, increasing the solder thickness increases thermal resistance. The antioxidant (flux) contained in the solder may contaminate the light-emitting portion of the light-emitting element.

[0009] When using gold bumps to bond a submount substrate to a metal substrate, the bonded area becomes thicker. Furthermore, the space between the bumps increases thermal resistance. Additionally, gold bumps are expensive, and the equipment used to bond them is also costly, resulting in higher manufacturing costs.

[0010] When a submount substrate is bonded to a metal substrate using a resin containing metal fillers, the thermal conductivity of the bonding material is low, resulting in high thermal resistance at the joint. Furthermore, because the resin containing metal fillers is liquid, variations in the thickness of the adhesive layer occur, leading to significant variations in the thermal resistance at the joint. Additionally, the thickness of the joint becomes uneven in the in-plane direction, causing an inclination angle on the light-emitting surface and potentially resulting in defective products.

[0011] If ultrasonic bonding can be used when joining a submount substrate to a metal substrate, the two will be directly joined, eliminating the need for bonding material and thus avoiding problems such as a decrease in thermal conductivity at the joint.

[0012] However, when ultrasonically bonding a submount substrate with pre-installed light-emitting elements to a metal substrate, force is applied to the light-emitting elements when the submount substrate is pressed against the metal substrate with the ultrasonic tool, which may cause the light-emitting elements to break.

[0013] On the other hand, if the procedure involves ultrasonically bonding only the submount substrate to the metal substrate, and then die-bonding the light-emitting element to the submount substrate, the thermal expansion coefficients of the ceramic substrate and the metal substrate constituting the submount substrate are significantly different. Therefore, high-temperature heating during die bonding of the light-emitting element may cause the bonding surface between the submount substrate and the metal substrate to fracture. Furthermore, since the eutectic point of AuSn eutectic is higher than the temperature range in which the manufacturer guarantees the performance of the mounting substrate, AuSn eutectic cannot be used as a die bonding material.

[0014] Furthermore, even if the problem of force being applied to the light-emitting element is solved and the submount substrate on which the light-emitting element is mounted is ultrasonically bonded to a metal substrate, cracks are likely to occur at the bonding surface due to the heat generated by the light-emitting element during use, caused by the large difference in thermal expansion coefficients between the ceramic substrate and the metal substrate.

[0015] The ultrasonic bonding technology described in Patent Document 3 is for electrode pads of bare chips with a small bonding area, so the pressure applied to the bare chip is small. The ultrasonic bonding technology described in Patent Document 4 is for bonding lid members of semiconductor packages, so no pressure is applied to the light-emitting element. Therefore, even if the technologies of Patent Documents 3 and 4 are used, the problem of pressure being applied to the light-emitting element, or the problem of fracture or cracking of the bonding surface between the sub-substrate and the metal substrate cannot be solved.

[0016] The objective of the present invention is to provide a semiconductor light-emitting device in which a submount substrate equipped with a light-emitting element is ultrasonically bonded to a metal substrate, while maintaining high reliability of the bonding surface. [Means for solving the problem]

[0017] To achieve the above objective, the semiconductor light-emitting device of the present invention comprises a light-emitting element, a ceramic submount substrate on which the light-emitting element is mounted, and a metal mounting substrate on which the submount substrate is mounted. The submount substrate has a metal layer on the bonding surface with the mounting substrate. The metal layer of the submount substrate and the mounting substrate are directly bonded without the use of a bonding material, and voids are contained in the bonding surface. The central region within the main plane of the bonding surface is larger than the peripheral region. [Effects of the Invention]

[0018] According to the semiconductor light-emitting device of the present invention, although the submount substrate on which the light-emitting element is mounted is ultrasonically bonded to a metal substrate, voids are contained in the central region of the bonding surface, which allows for the reduction of thermal stress and thus high reliability. [Brief explanation of the drawing]

[0019] [Figure 1] (a) and (b) Cross-sectional views of semiconductor light-emitting devices of embodiments, and (c) explanatory diagram showing the distribution of voids on the bonding surface 40. [Figure 2] A flowchart showing the manufacturing process of the semiconductor light-emitting device according to the embodiment. [Figure 3] (a) to (g) Cross-sectional views showing the manufacturing process of the semiconductor light-emitting device according to the embodiments. [Figure 4] (a) is an enlarged view of the process in Fig. 3(d), and (b) and (c) are a top view and a cross-sectional view of the fixing jig 50. [Figure 5] Explanatory drawing showing the pressure distribution of the ultrasonic bonding process of the embodiment. [Figure 6] Explanatory drawing showing the metal bonding process by ultrasonic waves. [Figure 7] (a) and (b) Images of the bonding surface of the semiconductor light-emitting device of the embodiment taken with an ultrasonic microscope, (c) Graph showing the change in the ultrasonic reflectivity of the bonding surface of the semiconductor light-emitting device of the embodiment. [Figure 8] Cross-sectional photograph of the semiconductor light-emitting device of the embodiment. [Figure 9] (a) Diagram explaining the simulation model of the thermal stress of the semiconductor light-emitting device of the embodiment, (b) Diagram showing the distribution of the thermal stress of the simulation result, (c) Graph showing the relationship between the thermal stress relaxation effect and the void content. [Figure 10] Cross-sectional view showing the ultrasonic bonding process of the modification of the embodiment.

Mode for Carrying Out the Invention

[0020] The semiconductor light-emitting device of an embodiment of the present invention will be described below.

[0021] <<<Embodiment>>> <Configuration of the Semiconductor Light-Emitting Device> The configuration of the semiconductor light-emitting device of the embodiment will be described with reference to Fig. 1. Figs. 1(a) and (b) are both cross-sectional views of the semiconductor light-emitting device of the present embodiment. Fig. 1(a) is an example in which the upper surface of the metal substrate 31 is flat, and Fig. 1(b) is an example in which a step is provided on the upper surface of the metal substrate 31. Fig. 1(c) is an explanatory drawing showing the distribution of voids on the bonding surface.

[0022] In the semiconductor light-emitting device of the present embodiment, a light-emitting element 10 is bonded on a submount substrate 20 whose base is a ceramic substrate, and the lower surface of the submount substrate 20 is bonded to a mounting substrate 30.

[0023] (Submount board 20) The submount substrate 20 comprises a base ceramic substrate 21, a pair of wiring patterns 22 arranged on the upper surface of the ceramic substrate 21, and a back metal layer 23 arranged across the entire lower surface of the ceramic substrate 21. The light-emitting element 10 is die-bonded to the wiring patterns 22 on the upper surface using an element bonding material 11. The ceramic substrate 21 is made of a material with excellent thermal conductivity (e.g., AlN, SiN, Al2O3, etc.). The back metal layer 23 is a metal film with excellent thermal conductivity and adhesion to the ceramic substrate 21, and it is desirable that the outermost metal layer has a hardness equivalent to or lower than that of the metal substrate 31 of the mounting substrate 30. Furthermore, conductive paste, solder bonding material, or eutectic bonding material such as AuSn can be used as the element bonding material 11.

[0024] For example, a metal multilayer film is used in which a Cu layer / N layer / Pd layer / Au layer are stacked in this order from the ceramic substrate 21 side. The outermost Au layer has a hardness equivalent to that of the metal substrate 31 of the mounting substrate 30. However, it is not limited to a metal with an Au layer on the outermost surface; a metal with high corrosion resistance is preferred. As an example, in the case of a Cu layer / Ni layer / (Pd layer) / Au layer, the film thickness can be 50 μm / 4 μm / 0.1 μm / 0.1 μm, respectively.

[0025] Although a ceramic substrate 21 is used here, it is also possible to use a sapphire substrate, silicon (Si) substrate, gallium nitride (GaN) substrate, carbon nitride (SiC) substrate, etc.

[0026] (Mounted board 30) The mounting substrate 30 has a structure in which an insulating layer 32 is provided on the surface of a base metal substrate 31, and a circuit pattern 33 is mounted on the insulating layer 32. The metal substrate 31 is made of a metal with excellent thermal conductivity (for example, an Al substrate or a Cu substrate). The metal substrate 31 has a mounting area 31a for mounting the submount substrate 20, and the insulating layer 32 and circuit pattern 33 are not provided in the mounting area 31a, so the upper surface of the metal substrate 31 is exposed. The upper surface of the metal substrate 31 may be flat, as shown in Figure 1(a), or the upper surface of the mounting area 31a may be formed to be higher than the surrounding area by the thickness of the insulating layer 32 and the circuit pattern 33, as shown in Figure 1(b).

[0027] The insulating layer 32 is made of a material that can insulate the circuit pattern 33 from the metal substrate 31 with a predetermined dielectric strength. The material of the insulating layer 32 has a very low thermal conductivity compared to metals. For example, a fibrous reinforcing material called a prepreg is uniformly impregnated with a thermosetting resin such as epoxy, and the semi-cured material is processed into a desired pattern and mounted on the metal substrate 31. The insulating layer 32 is then cured. The circuit pattern 33 is made of a metal with low electrical resistance (for example, Cu).

[0028] (Joint surface 40) A submount substrate 20 is mounted on the mounting area 31a of the metal substrate 31, and the lower surface of the back metal layer 23 of the submount substrate 20 is directly bonded to the upper surface of the metal substrate 31 by ultrasonic bonding without the use of an adhesive material. In other words, the metal on the bottom surface of the back metal layer 23 of the submount substrate 20 and the metal substrate 31 are intermetallicly bonded without adhesive material by interatomic forces between dissimilar metals. Here, the Au of the back metal layer 23 on the submount substrate 20 and the Al of the metal substrate 31 are intermetallicly bonded. That is, the interface between the bottom surface of the submount substrate 20 and the upper surface of the mounting substrate 30 constitutes the bonding surface, and specifically, the entire interface between the lower surface of the back metal layer 23 and the upper surface of the metal substrate 31 constitutes the bonding surface.

[0029] Furthermore, the combination of the metal layer 23 on the back surface of the bonding surface and the metal substrate 31 may be any other metal, as long as a hard metal (such as Ni) is avoided on the outermost bonding surface. In addition to Al-Au bonding, other types of bonding such as Al-Al, Cu-Au, Au-Au, etc., are also possible.

[0030] (Void) The bonding surface 40 between the lower surface of the metal layer 23 on the back of the submount substrate 20 and the upper surface of the metal substrate 31 is ultrasonically bonded such that minute voids are contained at the bonding interface.

[0031] The size of the voids is preferably 5 μm or less, and particularly preferably an average of 1 μm or less.

[0032] The void content per unit area at the joint surface 40 varies depending on its location within the main plane of the joint surface 40. The central region 41 of the joint surface 40 contains more voids than the peripheral region 42.

[0033] Specifically, it is desirable that the void content be between 5% and 15% per unit area in the central region 41, and between 0% and 5% per unit area in the peripheral region. In particular, it is desirable that the central region 41 has a void content of 1.0% or more and 15% per unit area, while the peripheral region 42 has a void content of 0% or more and 5% per unit area.

[0034] When the light-emitting element 10 is viewed from above, the central region 41 includes the bottom region of the light-emitting element 10.

[0035] It is desirable that the central region 41 is located at a distance of 5% to 30% of the length and width dimensions of the submount substrate 20 from the periphery of the bonding surface 40 (the periphery of the submount substrate 20).

[0036] The size of the voids depends on the surface roughness of the lower surface of the back metal layer 23 and the upper surface of the metal substrate 31 before bonding, and the conditions during ultrasonic bonding. By controlling these factors, voids of 5 μm or less can be formed on the bonding surface. Preferably, the surface roughness of the lower surface of the back metal layer 23 and the upper surface of the metal substrate 31 before bonding is Rz(23) < 5 μm and Rz(31) < 8 μm, and in particular, Rz(23) < 3 μm and Rz(31) < 5 μm.

[0037] More specifically, of the surface of the back metal layer 23 of the submount substrate 20 and the surface of the metal substrate 31 before bonding in the bonding process, the surface with the greater surface roughness preferably has a surface roughness Rz (maximum height) of 0.5 μm or more and 5 μm or less.

[0038] The size of the central region 41 containing many voids depends on the opening area of ​​the cavity provided in the fixing jig to prevent pressure from being applied to the light-emitting element 10 during ultrasonic bonding. The opening area has upper and lower limits depending on the bonding conditions, such as the size of the light-emitting element 10 and the size and thickness of the ceramic substrate 21. Therefore, by determining these conditions in advance, it is possible to bond the elements so that the central region 41 of the desired size contains many voids.

[0039] The shape of the central region 41 depends on the opening shape of the cavity in the fixing jig used during ultrasonic bonding, so it can be formed into any shape other than a circle, such as a square.

[0040] The opening area and shape of the fixing jig, as well as the setting conditions for ultrasonic bonding, will be explained in detail later.

[0041] <Function of the joint surface 40> As described above, in this embodiment, the submount substrate 20 and the metal substrate 31 of the mounting substrate 30 are directly joined without using a bonding material on the bonding surface 40, so that the thermal resistance at the bonding surface 40 can be reduced to the greatest extent possible. As a result, the heat generated by the light-emitting element 10 can be conducted to the metal substrate 31 via the element bonding material 11, the submount substrate 20, and the bonding surface 40 to dissipate the heat.

[0042] Since no bonding material is used at the bonding surface 40, there is no variation in thermal resistance due to the thickness distribution of the bonding material, and heat from the light-emitting element 10 can be uniformly conducted from the entire bonding surface 40.

[0043] Furthermore, the bonding surface 40 is configured to contain voids of 5% to 15% in the central region 41 and 0% to 5% in the peripheral region 42. Therefore, even if internal stress is generated in the bonding surface 40 due to the heat from the light-emitting element 10 because the thermal expansion coefficients of the ceramic substrate 21 and the metal substrate 31 are significantly different, the stress can be relieved by the contraction or expansion of the voids. At this time, since the central region 41 contains more voids than the peripheral region 42, the stress can be relieved in the region directly below the light-emitting element 10 where the temperature rises the most and the greatest stress occurs. Also, since the peripheral region 42 has less voids than the central region 41, the contact area between the back metal layer 23 of the submount substrate 20 and the metal substrate 31 of the mounting substrate 30 is large, resulting in high bonding strength. Therefore, it bonds firmly even when thermal stress is applied, suppressing the occurrence of cracks.

[0044] Ultrasonic bonding is performed at room temperature, so there is no formation of intermetallic compounds at the bonding surface. Furthermore, because high-temperature heating is not required, there is the advantage of minimal thermal impact on the light-emitting element 10 during bonding. <Manufacturing process for semiconductor light-emitting devices> Next, the method for manufacturing the semiconductor light-emitting device of this embodiment will be described.

[0045] Figure 2 is a flow chart showing the manufacturing process, and Figures 3(a) to 3(g) are cross-sectional views showing the manufacturing process. Figure 4(a) is an enlarged view of the process in Figure 3(d), and Figures 4(b) and 4(c) are a top view and a cross-sectional view of the fixing jig 50. Figure 5 shows the pressure distribution during ultrasonic bonding, and Figure 6 shows the metal bonding process using ultrasound.

[0046] (Step S1) First, as shown in Figure 3(a), the light-emitting element 10 is mounted (die-bonded) on the wiring pattern 22 on the upper surface of the sub-substrate substrate 20 using AuSn eutectic as the element bonding material 11.

[0047] (Step S2) As shown in Figure 3(b), the submount substrate 20 is set in the fixing jig 50 so that the upper surface of the light-emitting element 10 is facing downwards.

[0048] The fixing jig 50 has a cavity 51 in the center for housing the light-emitting element 10, a first stepped section 52 on the outside for housing and supporting the submount substrate 20, and a second stepped section 53 on the outside for housing the mounting substrate 30 (see Figures 3(b), 4(a)-(c)).

[0049] Although the light-emitting element 10 is already mounted on the submount substrate 20 in step S1, when the submount substrate 20 is mounted on the first stepped portion 52 of the fixing jig 50, the light-emitting element 10 is housed in the cavity portion 51 and does not come into contact with the fixing jig 50. As a result, the submount substrate 20 can be supported by the fixing jig 50 in the process of step S4 in Figure 3(d) so that no pressure is applied to the light-emitting element 10.

[0050] In this case, since a circular region is formed as the central region 41 containing many voids in the bonding surface 40 (see Figure 1(b)), the opening shape of the cavity 51 is provided in a circular shape. Furthermore, the opening size of the cavity 51 needs to be larger than the size of the light-emitting element 10. In addition, since the submount substrate 20 is supported by the area of ​​the lower surface of the first stepped portion 52 excluding the opening of the cavity 51, it is necessary to secure an area in the first stepped portion 52 that can adequately support the submount substrate 20, depending on the size, material, thickness, bonding conditions, etc. of the submount substrate 20. Therefore, the size of the opening of the cavity 51 is set to be greater than or equal to the size of the light-emitting element 10, and less than or equal to the size that can secure the minimum required area on the lower surface of the first stepped portion 52.

[0051] (Step S3) Next, as shown in Figure 3(c), the mounting board 30 is placed on the submount board 20 inside the fixing jig 50.

[0052] (Step S4) Next, as shown in Figures 3(d) and 4(a), the ultrasonic tool 60 is brought into contact with the mounting substrate 30, and as shown in Figure 5, ultrasonic energy is applied to the metal substrate through the ultrasonic tool 60 while applying pressure to the mounting substrate 30 in a direction that presses it against the submount substrate 20.

[0053] As a result, as shown in Figure 6(1), pressure and ultrasonic vibrations from the ultrasonic tool 60 are applied to the metal substrate 31 of the mounting substrate 30 and the back metal layer 23 of the submount substrate 20. As shown in Figure 6(2), friction / plastic flow occurs between the surface of the metal substrate 31 and the back metal layer 23 in contact with it. As shown in Figure 6(3), the oxide film on the metal surface is repelled, and the new metal surface is exposed. The metal substrate 31 and the back metal layer 23 deform around the exposed metal-to-metal contact area, increasing the contact area. As a result, the entire contact surface is solid-state bonded by interatomic forces, as shown in Figure 6(4). Unlike fusion bonding, this solid-state bonding takes place in a solid state near room temperature, far below the melting point of the metal material.

[0054] At this time, a cavity 51 is provided in the fixing jig 50, and the peripheral portion of the submount substrate 20 where the light-emitting element 10 is not provided is supported by the first stepped portion 52 around the cavity 51. As a result, at the bonding surface 40 during bonding, the pressure applied to the central region is smaller than the pressure applied to the outer peripheral region, as shown by the arrow in Figure 5, resulting in a pressure distribution. Therefore, in the peripheral region 42 of the bonding surface 40, the surface irregularities of the lower surface of the back metal layer 23 and the upper surface of the metal substrate 31 are deformed by pressure and ultrasonic vibration, increasing the contact area, so voids are less likely to occur and a strong bond is formed. On the other hand, in the central region 41 of the bonding surface 40, the pressure is smaller than in the peripheral region, so some gaps remain in the surface irregularities of the lower surface of the back metal layer 23 and the upper surface of the metal substrate 31, forming voids.

[0055] This makes it possible to form a bonding surface 40 consisting of a central region 41 containing many voids and a peripheral region 42 with fewer voids.

[0056] While the vibration mode of the ultrasonic tool 60 may be linear vibration, ultrasonic composite vibration (a circular or elliptical vibration created by adding torsional vibration to linear vibration) vibrates in a circular pattern, making it easier to apply pressure to the outer periphery of the joint surface 40, thus enabling a stronger bond at the outer periphery of the joint surface.

[0057] (Step S5) Next, the bonded mounting board 30 and submount board 20 are removed from the fixing jig 50. Then, as shown in Figure 3(e), the upper electrode of the light-emitting element 10 is connected to one of the pair of wiring patterns 22 on the submount board 20 with a wire 71 by wire bonding. Furthermore, the pair of wiring patterns 22 and the circuit pattern 33 on the mounting board 30 are connected to each other with a pair of wires 72 by wire bonding.

[0058] Note that if the light-emitting element 10 is a flip chip, the wire 71 is not required. Also, if the light-emitting element 10 has two upper electrodes, the two wires 71 connect the pair of wiring patterns 22 on the submount substrate 20, respectively.

[0059] (Step S6) Next, as shown in Figure 3(f), a phosphor plate 80 is mounted on the upper surface of the light-emitting element 10, and a light-reflective frame 81 is mounted on a mounting substrate 30 at a predetermined distance from the submount substrate 20.

[0060] (Step S7) Finally, as shown in Figure 3(g), the inside of the frame 81 is filled with a sealing resin 82 containing a light-reflective filler, which embeds the light-emitting element 10 and the submount substrate 20, except for the top surface of the phosphor plate 80, and then cured.

[0061] As a result, a semiconductor light-emitting device can be manufactured.

[0062] Steps S6 and S7 can be performed as needed. Furthermore, any surface irregularities can be provided on the surface of the ultrasonic tool that contacts the mounting substrate 30, and on the surface of the first stepped portion 52 of the fixing jig 50 that contacts the submount substrate 20. This allows ultrasonic energy to be applied to the bonding surface 40 efficiently. In this case, the irregularities are transferred to each surface of the submount substrate 20 or mounting substrate 30 that comes into contact with the irregularities.

[0063] In this embodiment, although the semiconductor light-emitting device and its manufacturing method have been described as having only one light-emitting element 10, multiple light-emitting elements may be arranged on the submount substrate. In this case, when setting the device onto the fixing jig in step S2, multiple light-emitting elements can be housed in one cavity, or multiple light-emitting elements can be housed in multiple cavities as appropriate. [Examples]

[0064] As an example, a semiconductor light-emitting device was manufactured using the manufacturing method of the embodiment described above.

[0065] (Mounted board 30) The mounting board 30 used a metal substrate 31 made of Al, with dimensions of 36mm x 36mm x 2.0mmt.

[0066] (Submount board 20) The submount substrate 20 used was a ceramic substrate 21 made of AlN, with the outermost surface of the back metal layer 23 made of Au, and its dimensions were 3.0 mm × 4.0 mm × 0.48 mmt.

[0067] (Ultrasonic tool) The ultrasonic tool 60 is made of tool steel, and its contact area with the mounting substrate 30 is equal to or greater than the area of ​​the bonding surface 40. The surface of the ultrasonic tool 60 that contacts the mounting substrate 30 is provided with knurling (periodic fine irregularities) as a non-slip surface treatment.

[0068] (Fixing jig 50) The fixing jig 50 was made of stainless steel (pre-hardened). The first stepped portion 52 of the fixing jig 50 that supports the sub-mount substrate 20 may also be knurled, similar to the ultrasonic tool 60.

[0069] The diameter of the opening of the cavity 51 of the fixing jig 50 was set to φ1.8 mm. The size of the light-emitting element 10 is approximately 1 mm square.

[0070] (Joining conditions) The ultrasonic mode was set to composite vibration, with a frequency of 20kHz, static pressure of 2000N or less, oscillation time of 2.0 sec or less, and AMPL (current ratio corresponding to vibration amplitude) of 100% or less.

[0071] Specifically, the settings were as follows: frequency: 20kHz, AMPL: 10-80% (0-100%), static pressure: 100-1000N (0-2000N), and oscillation time: 0.1-2.0sec (0-5.0sec).

[0072] <Cross-sectional photograph of the joint surface 40> Figures 8(a) and 8(b) show cross-sectional photographs of the joint surface 40 obtained in the embodiment.

[0073] Figure 8(a) is a cross-sectional view of a bonding surface formed by ultrasonic bonding using an Al substrate as the metal substrate 31 and a Cu / Ni / Pd / Au multilayer film (outermost layer: Au layer) as the back metal layer 23.

[0074] Figure 8(a) shows that the surface of the metal substrate (Al substrate) 31 has a bonding surface that is similar to the surface irregularities of the Au layer of the back metal layer 23, which is the bonding partner. From this, it can be seen that in ultrasonic bonding, a bonding surface is formed that follows the surface shape of the side with greater hardness (the Au layer of the back metal layer 23). Therefore, if the surface irregularities of the side with greater hardness are too large, it is thought that the side with less hardness will not be able to follow its surface shape and will generate voids.

[0075] Figure 8(b) is a cross-sectional view of a bonding surface formed by ultrasonic bonding using a Cu substrate (outermost Au layer) with Au / Pd / Ni laminated on its surface as the metal substrate 31, and a Cu / Ni / Pd / Au laminated film (outermost Au layer) as the back metal layer 23.

[0076] Since both sides of the bonding surface have an Au layer as their outermost surface, the bonding surface is formed by the planar reconstruction of the Au metal. As shown in Figure 8(b), due to the surface reconstruction of the Au metal, the bonding surface is not a simple surface, but rather consists of alternating areas where the lower surface of the Au layer of the back metal layer 23 and the upper surface of the Au layer of the metal substrate 31 are in contact and areas where they are not, with the areas that are not in contact forming voids.

[0077] Figure 8(b) confirms the formation of minute voids ranging from 5 μm or less to approximately 1 μm in size.

[0078] <How to check the distribution of voids> Here, we will explain a method for determining the amount of voids in the junction surface of a semiconductor light-emitting device.

[0079] When an image of the bonding surface 40 is taken from the top surface of the light-emitting element 10 using an ultrasonic microscope (C-SAM: Constant-depth mode Scanning Acoustic Microscopy), the ultrasonic microscope image will show black (low reflectivity) where there are no voids in the bonding surface 40, and white (high reflectivity) where there are voids (see Figure 7(a)). This allows the amount of voids to be calculated from the grayscale of the ultrasonic microscope image. Figure 7(b) is an image of the bonding surface 40 with adjusted grayscale. The central region is whiter than the peripheral region, indicating a larger amount of voids.

[0080] Figure 7(c) is a graph of the ultrasonic reflectance of the joint surface 40, obtained from the grayscale in Figure 7(a). Since the ultrasonic reflectance is 100% outside the joint surface, i.e., in the interface region with air, it can be considered that the ultrasonic reflectance at the joint surface indicates the surface density of voids. From the graph in Figure 7(c), it can be seen that the reflectance in the central region of the joint surface is significantly lower than in the peripheral region, indicating that voids are distributed there.

[0081] Furthermore, the ultrasonic reflectance of the central region 41 in Figure 7(c) is 5-10%, and the surface density of voids in the central region 41 can be assumed to be 5-10%.

[0082] <Thermal stress simulation results> Here, simulations confirmed that the thermal stress of the joint surface 40 can be relieved by including a void amount of 5% to 15% per unit area in the central region 41 of the joint surface 40.

[0083] For a semiconductor light-emitting element model (Figure 9(a)) in which voids with a size (width) of 1 μm are placed at equal intervals in the central region 41 of the bonding surface 40 at ratios of 5%, 10%, and 15% per unit area, and no voids are placed in the peripheral region 42, the thermal stress distribution at Ta = 150°C was calculated using a two-dimensional simplified model (Ta: T [atmosphere], ambient temperature (around the bonding surface)). A known analysis simulation software (Femted®, manufactured by Murata Manufacturing Co., Ltd.) was used for the calculation. The calculation results are shown in Figure 9(b).

[0084] Furthermore, as a comparative example, the thermal stress distribution was also calculated for a model in which neither the central region 41 nor the peripheral region 42 contained voids (0%). The results are shown in Figure 9(b).

[0085] Furthermore, the thermal stress values ​​at the ends of the joint surface 40 of the thermal stress distribution shown in Figure 9(b) are shown in the graph in Figure 9(c). As is clear from Figure 9(c), the models of this embodiment that contain voids at a rate of 5%, 10%, and 15% in the central region 41 show a significant reduction in thermal stress compared to the comparative example that does not contain voids (0%). Moreover, the higher the void content, the greater the reduction in thermal stress.

[0086] Therefore, it was confirmed that thermal stress is reduced by forming minute voids in the central region 41 of the joint surface 40 that do not significantly affect heat conduction, and by creating a structure for the joint surface 40 where there are no voids in the outer periphery. As a result, crack generation in the outer periphery of the joint surface 40 due to thermal shock is suppressed, and reliability is improved.

[0087] Furthermore, if the central region 41 containing voids becomes even larger, further stress relaxation can be expected, but the peripheral region 42 will decrease, which will reduce the joint strength in the peripheral region, and the voids in the peripheral region may promote crack formation. In other words, there is a trade-off relationship between stress relaxation and crack formation at the outermost periphery of the joint surface 40, so it is desirable to set the size of the central region 41 to a range in which both the amount of stress relaxation and the joint strength at the outermost periphery can be achieved. Also, considering the proportion of voids in the central region 41 that does not affect thermal resistance, the proportion of voids per unit area is preferably less than approximately 30%, and more preferably less than approximately 15%.

[0088] The inventors have experimentally confirmed that even if a cavity exists directly beneath the element, if the junction area is 70% or more, no significant change in thermal resistance is observed.

[0089] Furthermore, according to the inventors' experiments, the size of the voids is what affects the thermal resistance. Voids with a size of 10 μm or less do not have a significant effect on the thermal resistance even if the proportion of voids in the central region 41 is large. However, as the proportion of voids in the central region 41 increases, larger voids tend to occur. Therefore, as mentioned above, the proportion of voids per unit area is preferably less than approximately 30%, and more preferably less than approximately 15%.

[0090] <<Variation>> In the above-described embodiment, in the ultrasonic bonding process of step S4 in the flow chart of Figure 2, the ultrasonic tool 60 was pressed against the back side of the mounting substrate 30 to apply ultrasonic vibrations to the mounting substrate 30, as shown in Figures 3(d) and 4(a). However, as a modified example, the ultrasonic tool 60 may be pressed against the upper surface of the submount substrate 20, as shown in Figure 10.

[0091] In this case, a cavity 61 is provided in the ultrasonic tool 60 to house the light-emitting element 10, so that the ultrasonic tool 60 does not come into contact with the light-emitting element 10.

[0092] The fixing jig 50 only needs to have recesses to support the mounting board 30.

[0093] The ultrasonic bonding process shown in the modified example in Figure 10 only requires vibrating a small submount substrate 20, compared to the ultrasonic bonding in Figure 4(a) where a large mounting substrate 30 is vibrated. Therefore, the bonding surface 40 can be bonded with less ultrasonic energy than in Figure 4(a), while minimizing damage to the submount substrate 20. As a result, even when the mounting substrate 30 is thick, ultrasonic energy can be efficiently applied to the bonding surface without attenuation.

[0094] The semiconductor light-emitting device technology of this embodiment can be used in luminaire light source units and white light source modules. [Explanation of Symbols]

[0095] 10 light-emitting elements 11-element bonding material 20 Submount boards 21 Ceramic substrate 22 Wiring Patterns 23. Metal layer on the back 30 Implemented circuit boards 31 Metal substrate 31a Loading area 32 Insulating layer 33 Circuit Patterns 40 Joint surface 41 Central area 42 Peripheral region 50 Fixing fixtures 51 Cavity 60 Ultrasonic Tools 61 Cavity 71 wire 72 wires 80 Phosphor Plates 81 Frame 82 Sealing resin

Claims

1. The device comprises a light-emitting element, a submount substrate on which the light-emitting element is mounted, and a metal mounting substrate on which the submount substrate is mounted. The submount substrate has a metal layer on the bonding surface with the mounting substrate, The metal layer of the submount substrate and the mounting substrate are directly bonded without the use of a bonding material, and the bonding surface contains voids. A semiconductor light-emitting device characterized in that the void content per unit area at the bonding surface is greater in the central region of the main plane of the bonding surface than in the peripheral region.

2. A semiconductor light-emitting apparatus according to claim 1, characterized in that the surface density of the void is 5% or more and 15% or less in the central region and 5% or less in the peripheral region.

3. A semiconductor light-emitting device according to claim 1, characterized in that, when the light-emitting element is viewed from above, the central region is larger than the bottom region of the light-emitting element.

4. A semiconductor light-emitting apparatus according to claim 1, characterized in that the size of the void is 5 μm or less.

5. A semiconductor light-emitting apparatus according to claim 1, characterized in that the metal layer provided on the bonding surface of the submount substrate with the mounting substrate has lower hardness than the metal mounting substrate.

6. The semiconductor light-emitting apparatus according to claim 1, wherein the metal mounting substrate is made of either Al or Cu, The submount substrate has a base ceramic substrate, and the ceramic substrate is made of AlN, SiN, and Al ２ O ３ Composed of one of the following: The semiconductor light-emitting device is characterized in that the metal layer is formed on the bonding surface of the ceramic substrate with the mounting substrate, and the metal layer is an Au layer.

7. The ceramic substrate has a metal layer formed on one side, and the metal substrate is bonded to the side of the ceramic substrate where the metal layer is formed. The metal layer of the ceramic substrate and the metal substrate are directly bonded without the use of a bonding material, and the bonding surface contains voids. A jointed structure characterized in that the void content per unit area at the jointed surface is greater in the central region of the main plane of the jointed surface than in the peripheral region.

Images