Wiring board and mounting structure using same

Abstract

A wiring board according to the present disclosure comprises a first insulation layer that has a first surface, a second insulation layer that has a via hole and is positioned on the first surface, and a via conductor part that passes through the second insulation layer. The via conductor part has a via land conductor that is positioned on the first surface, and a via hole conductor that is positioned in the via hole and is in contact with the via land conductor. The via land conductor has at least a first layer that includes a connection part in contact with the via hole conductor, and a second layer that is in contact with the first-insulation-layer side of the first layer. The via conductor part has a continuous crystal that spans the first layer and the via hole conductor with the connection part interposed therebetween. A first crystal grain size of the first layer is different than a second crystal grain size of the second layer.

Description

Wiring board and mounting structure using same

[0001] The present invention relates to a wiring board and a mounting structure using the same.

[0002] In wiring boards, as shown in Patent Document 1, vias (via holes) formed in an insulating layer are filled with conductors (via hole conductors) to electrically connect conductor layers located on the top and bottom surfaces of an insulating layer. The via hole conductors are usually connected to via lands at the via bottom. Stress tends to concentrate in the via hole conductors at the connection between the via bottom and the via land. Therefore, they may break when exposed to high temperature conditions.

[0003] Japanese Patent Application Laid-Open No. 2008-193025

[0004] The wiring board according to the present disclosure includes a first insulating layer having a first surface, a second insulating layer located on the first surface and having a via hole, and a via conductor portion penetrating the second insulating layer. The via conductor portion has a via land conductor located on the first surface and a via hole conductor contacting the via land conductor and located in the via hole. The via land conductor has at least a first layer including a connection portion contacting the via hole conductor and a second layer contacting the first insulating layer side of the first layer. The via conductor portion has continuous crystals spanning the first layer and the via hole conductor via the connection portion. The first crystal grain size of the first layer is different from the second crystal grain size of the second layer.

[0005] Furthermore, a mounting structure according to the present disclosure includes the above wiring board and an electronic component located in a mounting area of ​​the wiring board.

[0006] FIG. 2 is an explanatory diagram for explaining a wiring board according to an embodiment of the present disclosure. FIG. 3 is an electron microscope photograph showing an example of region X shown in FIG. 1. FIG. 4 is an explanatory diagram for explaining an example of a method for forming a via conductor portion in a wiring board according to an embodiment of the present disclosure. FIG. 5 is an explanatory diagram for explaining an example of a method for forming a via conductor portion in a wiring board according to an embodiment of the present disclosure. FIG. 6 is an explanatory diagram for explaining an example of a method for forming a via conductor portion in a wiring board according to an embodiment of the present disclosure.

[0007] As described above, stress tends to concentrate in the connection between the via bottom and the via land in the via-hole conductor. Therefore, when exposed to high temperatures, the via-hole conductor may break. Therefore, there is a need for a wiring board that has excellent connection strength between the via bottom and the via land and can reduce breakage due to crack propagation in the vertical and horizontal directions in the via land.

[0008] The wiring board according to the present disclosure has the configuration described in the section on means for solving the above problems, thereby providing excellent connection strength between the via bottom and the via land and reducing breakage due to crack propagation in the vertical and horizontal directions in the via land.

[0009] A wiring board according to an embodiment of the present disclosure will be described with reference to Figures 1 and 2. Figure 1 is an explanatory diagram for describing a wiring board 1 according to an embodiment of the present disclosure. As shown in Figure 1, the wiring board 1 according to the embodiment includes an insulating layer 2, a conductor layer 3, and a solder resist 4.

[0010] The insulating layer 2 includes a first insulating layer 21 and a second insulating layer 22. The first insulating layer 21 has upper and lower surfaces (first surface 211) and is not particularly limited as long as it is made of an insulating material. Examples of insulating materials include resins such as epoxy resin, bismaleimide-triazine resin, polyimide resin, and polyphenylene ether resin. Two or more of these resins may be mixed together. In the wiring board 1, the first insulating layer 21 corresponds to a core insulating layer. The thickness of the first insulating layer 21 is not particularly limited, and when the first insulating layer 21 corresponds to a core insulating layer, it is, for example, 100 μm or more and 3000 μm or less.

[0011] The first insulating layer 21 may contain a reinforcing material. Examples of the reinforcing material include insulating fabric materials such as glass fiber, glass nonwoven fabric, aramid nonwoven fabric, aramid fiber, and polyester fiber. Two or more types of reinforcing materials may be used in combination. Furthermore, the first insulating layer 21 may contain dispersed therein an inorganic insulating filler such as silica, barium sulfate, talc, clay, glass, calcium carbonate, or titanium oxide.

[0012] Through-hole conductors 21a are located in the first insulating layer 21 to electrically connect the top and bottom surfaces of the first insulating layer 21. The through-hole conductors 21a are located in through-holes that penetrate the first insulating layer 21 from the top surface to the bottom surface. The through-hole conductors 21a are formed, for example, by metal plating such as copper plating. The through-hole conductors 21a are connected to the conductor layers 3 formed on both surfaces of the first insulating layer 21. The through-hole conductors 21a may be located only on the inner wall surfaces of the through-holes 21a', or may fill the through-holes 21a'.

[0013] A build-up layer, in which conductor layers 3 and insulating layers 2 are alternately stacked, is located on the first surface 211 of the first insulating layer 21. The build-up layer includes at least two conductor layers 3 and one insulating layer 2. Of the insulating layers 2, the insulating layer 2 in contact with the first surface 211 of the first insulating layer 21 corresponds to the second insulating layer 22.

[0014] The conductor layer 3 is not limited as long as it is a conductor such as a metal. Specifically, the conductor layer 3 is formed of a metal foil such as a copper foil, a metal plating such as a copper plating, etc. The thickness of the conductor layer 3 is not particularly limited and is, for example, 5 μm or more and 20 μm or less.

[0015] The insulating layer 2 constituting the build-up layer is not particularly limited as long as it is made of a material having insulating properties, similar to the first insulating layer 21. As mentioned above, examples of the insulating layer 2 include resins such as epoxy resin, bismaleimide-triazine resin, polyimide resin, and polyphenylene ether resin. Two or more of these resins may be mixed together. The insulating layers 2 constituting the build-up layer may be made of the same resin or different resins. The insulating layers 2 constituting the build-up layer and the first insulating layer 21 may be made of the same resin or different resins. The thickness of the insulating layer 2 constituting the build-up layer is not particularly limited, and is, for example, 10 μm or more and 50 μm or less. The insulating layers 2 constituting the build-up layer may have the same thickness or different thicknesses.

[0016] The insulating layer 2 constituting the build-up layer may contain a reinforcing material. Examples of the reinforcing material include insulating fabric materials such as glass fiber, glass nonwoven fabric, aramid nonwoven fabric, aramid fiber, and polyester fiber. Two or more types of reinforcing materials may be used in combination. Furthermore, the insulating layer 2 constituting the build-up layer may have dispersed therein an inorganic insulating filler such as silica, barium sulfate, talc, clay, glass, calcium carbonate, or titanium oxide.

[0017] 1, a solder resist 4 may be located on the surface of the build-up layer. The solder resist 4 is made of a resin, such as an acrylic-modified epoxy resin. The solder resist 4 has openings for electrically connecting the conductor layer 3 to the electrodes of the element via solder 5. Examples of the element include a semiconductor integrated circuit element and an optoelectronic element.

[0018] Via conductors 31 are formed in the second insulating layer 22 to electrically connect the upper and lower surfaces of the second insulating layer 22. The via conductors 31 are located in via holes formed to penetrate the second insulating layer 22. In other words, the via conductors 31 are located to penetrate the second insulating layer 22.

[0019] As shown in Fig. 2, the via conductor portion 31 includes a via land conductor 3a and a via hole conductor 3b. Fig. 2 is an electron microscope photograph showing an example of region X shown in Fig. 1. In the wiring board 1, the via land conductor 3a is located on the first surface 211 of the first insulating layer 21. The via hole conductor 3b fills a via hole formed in the second insulating layer 22, and its bottom (the bottom surface closer to the first surface 211) is in contact with the via land conductor 3a. The via land conductor 3a and the via hole conductor 3b are part of the conductor layer 3 and are made of a metal such as copper.

[0020] In the wiring board 1, the via land conductor 3a includes a first layer 3a1, a second layer 3a2, and a third layer 3a3. The first layer 3a1 includes a connection portion 3a1' that contacts the via hole conductor 3b. The first layer 3a1 and the via hole conductor 3b are connected by a continuous crystal straddling the first layer 3a1 via the connection portion 3a1'. The second layer 3a2 is located closer to the first insulating layer 21 than the first layer 3a1 and is in contact with the first layer 3a1. The third layer 3a3 is located closer to the first insulating layer 21 than the second layer 3a2 and is in contact with the second layer 3a2. The continuous crystal can be confirmed, for example, by observing the cross-section of the via land conductor 3a and the via hole conductor 3b with a scanning electron microscope and confirming that at least one crystal grain is located straddling the first layer 3a1 and the via hole conductor 3b.

[0021] In the wiring board 1, the crystal grain size of the crystals constituting the first layer 3a1 (hereinafter referred to as the "first crystal grain size") is different from the crystal grain size of the crystals constituting the second layer 3a2 (hereinafter referred to as the "second crystal grain size"). That is, at the contact surface (connection portion 3a1') between the first layer 3a1 and the via-hole conductor 3b, not only are the first layer 3a1 and the via-hole conductor 3b connected by a continuous crystal, but the first crystal grain size and the second crystal grain size are different. At the contact surface (connection portion 3a1') between the first layer 3a1 and the via-hole conductor 3b, the first layer 3a1 and the via-hole conductor 3b are connected by a continuous crystal. Therefore, at the connection portion 3a1' between the first layer 3a1 and the via-hole conductor 3b, where thermal stress is likely to concentrate, the propagation of cracks, for example, in a direction (lateral direction) along the top surface of the via land conductor 3a, is reduced. Furthermore, since the first and second crystal grain sizes are different, the interfaces of the crystal grains in the first layer 3a1 and the second layer 3a2 are less likely to coincide with each other, thereby reducing the propagation of cracks along the thickness direction (vertical direction) of the via land conductor 3a.

[0022] When the second crystal grain size is larger than the first crystal grain size, for example, when a crack occurs in the thickness direction along the interface of the crystal grains of the first layer 3a1, the propagation of the crack can be reduced in areas other than the interface of the crystal grains of the second layer 3a2.

[0023] When the via land conductor 3a includes a first layer 3a1, a second layer 3a2, and a third layer 3a3, the first crystal grain size and the crystal grain size of the crystals constituting the third layer 3a3 (hereinafter referred to as the "third crystal grain size") may be smaller than the second crystal grain size. That is, the second crystal grain size is larger than the first crystal grain size and the third crystal grain size. By reducing the crystal grain sizes of the first layer 3a1 and the third layer 3a3, which are in contact with the insulating resin layer having a larger thermal expansion coefficient than the via land conductor 3a, the number of relatively flexible crystal grain boundaries increases. Therefore, thermal stress generated in the first layer 3a1 and the third layer 3a3 is more easily absorbed. Furthermore, even if a crack occurs in the thickness direction of the first layer 3a1 and the third layer 3a3, the second crystal grain size is larger than the first crystal grain size and the third crystal grain size, so that the propagation of the crack can be reduced in regions other than the crystal grain interfaces of the second layer 3a2.

[0024] The first crystal grain size may be, for example, 1 μm or more and 2.8 μm or less, or 1.5 μm or more and 2.1 μm or less. The second crystal grain size may be, for example, 2.9 μm or more and 9 μm or less, or 3.1 μm or more and 3.6 μm or less. The third crystal grain size may be, for example, 1 μm or more and 2.1 μm or less, or 1.4 μm or more and 1.8 μm or less. The crystal grain size is measured, for example, in accordance with JIS H 0501. Specifically, the number of crystal grains captured by a test line having a known length is counted. This measurement is performed at any five locations. Next, the arithmetic average value of the number of crystal grains obtained at the five locations is calculated. Next, the average line length per crystal grain of the test line (i.e., the crystal grain size) is determined.

[0025] The thicknesses of the first layer 3a1, the second layer 3a2, and the third layer 3a3 are not limited. For example, the thickness of the first layer 3a1 may be greater than the thicknesses of the second layer 3a2 and the third layer 3a3. The first layer 3a1 may have a thickness of, for example, 10 μm or more and 20 μm or less. The second layer 3a2 may have a thickness of, for example, 5 μm or more and 15 μm or less. The third layer 3a3 may have a thickness of, for example, 2 μm or more and 10 μm or less. The thickness of the first layer 3a1 can be defined, for example, as the distance between an imaginary line including many flat areas at the base of the irregularities on the surface of the first layer 3a1 facing the second insulating layer 22 and the interface between the first layer 3a1 and the second layer 3a2. The thickness of the second layer 3a2 can be defined, for example, as the distance between the interface between the first layer 3a1 and the second layer 3a2 and the interface between the second layer 3a2 and the third layer 3a3. The thickness of the third layer 3a3 can be defined as the distance between an imaginary line including many flat areas at the base of the irregularities on the surface of the third layer 3a3 facing the first insulating layer 21, and the interface between the second layer 3a2 and the third layer 3a3.

[0026] For example, if thermal stress occurs at the connection portion 3a1' between the first layer 3a1 and the via-hole conductor 3b, where thermal stress is likely to concentrate, if the first crystal grain size of the first layer 3a1 is relatively small, the direction of expansion is more likely to be dispersed even if thermal stress causes the crystal to expand. If the thickness of the first layer 3a1 is greater than the thickness of the second layer 3a2 and the thickness of the third layer 3a3, the direction of expansion is more likely to be dispersed. As a result, the occurrence of cracks and peeling can be further reduced.

[0027] The arithmetic mean roughness of the top and bottom surfaces of the via land conductor 3a, i.e., the surface of the first layer 3a1 facing the second insulating layer 22 and the surface of the third layer 3a3 facing the first insulating layer 21, is not limited. The surface of the first layer 3a1 facing the second insulating layer 22 refers to the surface in contact with the second insulating layer 22. By making the arithmetic mean roughness of either surface relatively large, the adhesion between the insulating layer 2 and the via land conductor 3a can be improved. On the other hand, by making the arithmetic mean roughness of either surface relatively small, it is possible to prevent degradation of electrical characteristics.

[0028] For example, the arithmetic mean roughness of the surface of the first layer 3a1 facing the second insulating layer 22 may be smaller than the arithmetic mean roughness of the surface of the third layer 3a3 facing the first insulating layer 21. In such a case, the adhesion between the first insulating layer 21 and the via land conductor 3a is improved, and the electrical characteristics of the conductor can be maintained in good condition. The arithmetic mean roughness of the surface of the first layer 3a1 facing the second insulating layer 22 may be, for example, 50 nm or more and 500 nm or less. The arithmetic mean roughness of the surface of the third layer 3a3 facing the first insulating layer 21 may be, for example, 200 nm or more and 1000 nm or less.

[0029] Next, one embodiment of a method for forming the via conductor portion 31 will be described with reference to Figures 3 to 5. Figures 3 to 5 are explanatory diagrams for describing an example of a method for forming the via conductor portion 31 in the wiring substrate 1 according to an embodiment of the present disclosure.

[0030] 3A, metal foil 3' such as copper foil is attached to the top and bottom surfaces (first surface 211) of first insulating layer 21. For example, a double-sided metal-clad laminate such as a double-sided copper-clad laminate may be prepared. This metal foil 3' corresponds to the third layer 3a3 of via land conductor 3a in wiring board 1 according to one embodiment.

[0031] 3B, through holes 21a' are formed so as to penetrate the top and bottom surfaces of the first insulating layer 21 to which the metal foil 3' is attached. The size and number of the through holes 21a' are set appropriately depending on the size of the wiring board 1 to be finally obtained, etc. The through holes 21a' are formed using, for example, a drill. If necessary, a desmear process or the like is performed to remove resin residue, etc.

[0032] Next, as shown in Figure 3C, a seed layer is formed on the surface of the metal foil 3' and on the inner wall surfaces of the formed through-holes 21a'. By forming the seed layer, metal can be efficiently deposited by electrolytic plating in the next step. The seed layer is formed of a metal such as copper.

[0033] 3D, a metal such as copper is deposited on the surface of the seed layer by electrolytic plating to form through-hole conductors 21a on the inner wall surfaces of through-holes 21a'. A layer of the same conductor as through-hole conductor 21a is also formed on the surface of metal foil 3' located on the top and bottom surfaces of first insulating layer 21. This layer of the same conductor as through-hole conductor 21a corresponds to second layer 3a2 of via land conductor 3a in wiring board 1 according to one embodiment.

[0034] In one embodiment of the wiring board 1, the crystal grain sizes of the layers constituting the via land conductor 3a are different. Therefore, it is necessary to make the crystal grain size of the metal foil 3′ different from the crystal grain size of the metal deposited by electroplating. During electroplating, the crystal grain size of the deposited metal can be adjusted, for example, by adjusting the current density or the amount of additives. Specifically, the crystal grain size of the deposited metal can be increased by increasing the current density or reducing the amount of brightener added. Conversely, the crystal grain size of the deposited metal can be reduced by decreasing the current density or increasing the amount of brightener added. Brightener adsorbs to the growth points of crystal nuclei and suppresses crystal growth. This generates new crystal nuclei on the plating surface, promoting crystal refinement and forming a dense plating film. In other words, increasing the amount of brightener reduces the crystal grain size, while decreasing the amount of brightener increases the crystal grain size.

[0035] Next, as shown in Fig. 3E, resin is filled into the through-holes 21a'. There are no limitations on the resin that can be filled into the through-holes 21a', and examples thereof include epoxy resin, bismaleimide-triazine resin, polyimide resin, and polyphenylene ether resin. After filling the through-holes 21a' with resin, as shown in Fig. 4A, the resin filled into the through-holes 21a' is polished so that it is substantially flush with the layer of conductor that is the same as the through-hole conductors 21a formed on the surface of the metal foil 3'.

[0036] Next, as shown in Fig. 4B, a metal such as copper is deposited by electroless plating and electrolytic plating on the surface that is substantially flush with the surface in Fig. 4A. The layer formed by this plating process corresponds to the first layer 3a1 of the via land conductor 3a in the wiring board 1 according to one embodiment. Therefore, it is necessary to match the crystal grain size with that of the via hole conductor 3b to be formed later. By matching the crystal grain size with that of the via hole conductor 3b, it is possible to finally form a continuous crystal that spans the first layer 3a1 and the via hole conductor 3b via the connection portion 3a1'. The method for adjusting the crystal grain size in electrolytic plating is as described above, and a detailed description thereof will be omitted.

[0037] Next, as shown in Fig. 4C, resist 6 is formed in the position where via land conductor 3a is to be formed. After forming resist 6, etching is performed to remove metal foil 3' and plated metal from the portion where resist 6 is not formed, as shown in Fig. 4D. Next, as shown in Fig. 5A, resist 6 is removed to form via land conductor 3a including first layer 3a1, second layer 3a2, and third layer 3a3.

[0038] Next, as shown in Fig. 5B, a second insulating layer 22 is formed on the first surface 211 of the first insulating layer 21 so as to cover the via land conductors 3a. The material forming the second insulating layer 22 is as described above, and a detailed description thereof will be omitted. After forming the second insulating layer 22, via holes with the via land conductors 3a as their bottom surfaces are formed in the second insulating layer 22, as shown in Fig. 5C. The via holes are formed using, for example, a laser. The size and number of the via holes are set appropriately depending on the size of the wiring board 1 to be finally obtained, etc.

[0039] 5D, a metal such as copper is deposited in the formed via hole by electroless plating and electrolytic plating, filling the via hole with the metal to form a via-hole conductor 3b. As described above, the crystal grain size of the via-hole conductor 3b should be matched with the crystal grain size of the first layer 3a1 of the via land conductor 3a. In this manner, a via conductor portion 31 is formed.

[0040] The mounting structure according to the present disclosure includes a wiring board 1 according to one embodiment and an element S located on the surface of the wiring board 1. A conductor layer 3 in an opening of a solder resist 4 is connected to an electrode of the element S via solder 5. As described above, examples of the element S include a semiconductor integrated circuit element and an optoelectronic element. The elements may be located on both surfaces of the wiring board 1, or the element S may be located on one surface and, for example, a motherboard may be located on the other surface.

[0041] The wiring board according to the present disclosure is not limited to the wiring board 1 according to the above-described embodiment. In the wiring board 1 according to the embodiment, the via land conductor 3a has a three-layer structure of a first layer 3a1, a second layer 3a2, and a third layer 3a3. However, in the wiring board according to the present disclosure, the via land conductor does not need to have a three-layer structure, and may have a two-layer structure of a first layer and a second layer.

[0042] When the via land conductor has a two-layer structure, the arithmetic mean roughness of the surface of the first layer facing the second insulating layer may be smaller than the arithmetic mean roughness of the surface of the second layer facing the first insulating layer, thereby improving adhesion between the first insulating layer and the via land conductor and maintaining good electrical properties as a conductor.

[0043] In a wiring board 1 according to one embodiment, the core insulating layer is the first insulating layer 21, and among the insulating layers 2 constituting the buildup layer, the insulating layer 2 in contact with the first surface 211 of the core insulating layer is the second insulating layer 22. Cracks and peeling are most likely to occur in the via conductors 31 located in the insulating layer 2 constituting the buildup layer in contact with the core insulating layer. Therefore, in the wiring board 1 according to one embodiment, it is sufficient that at least the above-described via conductors 31 are located in the insulating layer 2 constituting the buildup layer in contact with the core insulating layer. In other words, conventional via lands and via hole conductors may be located in the other insulating layers 2 constituting the buildup layer, or the above-described via conductors 31 may be located therein.

[0044] In cases where the above-mentioned via conductor portion 31 is located in another insulating layer 2 constituting the build-up layer, or in cases where there is no core insulating layer as in a coreless substrate, one insulating layer between the insulating layers constituting the build-up layer may be the ``first insulating layer,'' and the insulating layer located on the first surface of this first insulating layer may be the ``second insulating layer.''

[0045] Although the embodiments of the present disclosure have been described above, the invention according to the present disclosure is not limited to the above-described embodiments, and various modifications and improvements are possible within the scope of the present disclosure as shown in (1) and (6) below.

[0046] (1) A wiring board according to the present disclosure includes a first insulating layer having a first surface, a second insulating layer located on the first surface and having a via hole, and a via conductor portion penetrating the second insulating layer. The via conductor portion includes a via land conductor located on the first surface and a via hole conductor contacting the via land conductor and located in the via hole. The via land conductor includes at least a first layer including a connection portion contacting the via hole conductor and a second layer contacting the first insulating layer side of the first layer. The via conductor portion has continuous crystals spanning the first layer and the via hole conductor via the connection portion. The first crystal grain size of the first layer is different from the second crystal grain size of the second layer.

[0047] The present disclosure further discloses the following embodiments (2) to (5).

[0048] (2) In the wiring board described in (1) above, the second crystal grain size is larger than the first crystal grain size. (3) In the wiring board described in (1) or (2) above, the via land conductor further includes a third layer in contact with the first insulating layer side of the second layer, and the first crystal grain size and the third crystal grain size of the third layer are smaller than the second crystal grain size. (4) In the wiring board described in (3) above, the arithmetic mean roughness of the surface of the first layer facing the second insulating layer is smaller than the arithmetic mean roughness of the surface of the third layer facing the first insulating layer. (5) In the wiring board described in (3) or (4) above, the thickness of the first layer is larger than the thickness of the second layer and the thickness of the third layer.

[0049] (6) A mounting structure according to the present disclosure includes the wiring board according to any one of (1) to (5) above, and an electronic component located in a mounting area of ​​the wiring board.

[0050] REFERENCE SIGNS LIST 1 wiring board 2 insulating layer 21 first insulating layer 21a through-hole conductor 21a' through-hole 211 first surface 22 second insulating layer 3 conductor layer 31 via conductor portion 3a via land conductor 3a1 first layer 3a1' connection portion 3a2 second layer 3a3 third layer 3b via-hole conductor 4 solder resist 5 solder S element

Claims

1. a first insulating layer having a first surface; a second insulating layer located on the first surface and having a via hole; a via conductor portion penetrating the second insulating layer; Equipped with the via conductor portion includes a via land conductor located on the first surface, and a via hole conductor in contact with the via land conductor and located in the via hole, the via land conductor has at least a first layer including a connection portion in contact with the via hole conductor, and a second layer in contact with the first insulating layer side of the first layer, the via conductor portion has a continuous crystal extending across the first layer and the via hole conductor through the connection portion, the first grain size of the first layer is different from the second grain size of the second layer; Wiring board.

2. The wiring board according to claim 1 , wherein the second grain size is larger than the first grain size.

3. the via land conductor further includes a third layer in contact with the second layer on the first insulating layer side, The wiring board according to claim 1 , wherein the first grain size and the third grain size of the third layer are smaller than the second grain size.

4. The wiring board according to claim 3 , wherein an arithmetic mean roughness of the surface of the first layer facing the second insulating layer is smaller than an arithmetic mean roughness of the surface of the third layer facing the first insulating layer.

5. The wiring board according to claim 3 , wherein the first layer has a thickness greater than the second layer and the third layer.

6. A mounting structure comprising the wiring board according to any one of claims 1 to 5 and an electronic component located in a mounting area of ​​the wiring board.