Silicon-on-insulator semiconductor component, process platform, and manufacturing method

Abstract

The present application relates to a silicon-on-insulator semiconductor component, comprising: a substrate; a buried dielectric layer, provided on the substrate; a first electrode; a second electrode; and a drift region, provided on the buried dielectric layer. A drop structure is formed on the upper surface of the drift region, the drop structure comprising a first side close to the first electrode, a second side close to the second electrode and a transition region between the first side and the second side, and the upper surface of the second side being higher than the lower surface of the first side, such that the thickness of the drift region on the second side is greater than the thickness of same on the first side; the first electrode and the second electrode are configured such that: when reverse bias is applied to the component, a voltage applied to the second electrode is greater than a voltage applied to the first electrode.

Description

Silicon-on-insulator semiconductor components, process platform, and manufacturing method

[0001] Related applications

[0002] This application claims priority to Chinese patent application No. 2023107131192, filed on June 15, 2023, entitled “Silicon-on-insulator semiconductor components and process platform, and manufacturing method,” the entire text of which is hereby incorporated by reference. Technical Field

[0003] The present application relates to the field of semiconductor manufacturing, and in particular to a silicon-on-insulator semiconductor component, a silicon-on-insulator semiconductor process platform, and a method for manufacturing a silicon-on-insulator semiconductor component. Background Art

[0004] With the widespread application of ultra-large-scale integrated circuits (VLSIs) in various fields, the system has increasingly higher requirements for the development of high-voltage and high-power semiconductor devices. Integrated high-voltage devices (such as LDMOS, LIGBT, and high-voltage diodes) using silicon-on-insulator (SOI) technology combine the advantages of SOI technology and the device itself, with fast operating speed, low parasitic effects, high breakdown voltage, simple process preparation, and convenient integration. Therefore, they have been widely studied and applied. However, conventional silicon-on-insulator integrated high-voltage devices have difficulty achieving breakdown voltages of 1200V and above. Although the thickness of the buried oxide layer is related to the breakdown voltage, a thick buried oxide layer will reduce the thermal conductivity of the device. When the buried oxide layer is thick enough, it will not contribute to the breakdown voltage, and it will also lead to an increase in cost. Therefore, it is unrealistic to increase the breakdown voltage by further increasing the thickness of the buried oxide layer after the breakdown voltage reaches a certain value.

[0005] Summary of the Invention

[0006] In a first aspect, a silicon-on-insulator semiconductor component is provided, comprising: a substrate; a buried dielectric layer disposed on the substrate; a first electrode; a second electrode; a drift region disposed on the buried dielectric layer; a step structure is formed on the upper surface of the drift region, the step structure comprising a first side close to the first electrode, a second side close to the second electrode, and a transition region between the first side and the second side, the upper surface of the second side is higher than the lower surface of the first side, so that the thickness of the drift region on the second side is greater than the thickness on the first side; wherein the first electrode and the second electrode are configured such that when a reverse bias is applied to the component, the voltage applied by the second electrode is greater than the voltage applied by the first electrode.

[0007] In one embodiment, the component is a lateral double diffused metal-oxide-semiconductor field effect transistor, the first electrode is a source, the second electrode is a drain, and the lateral double diffused metal-oxide-semiconductor field effect transistor further includes a gate.

[0008] In one embodiment, the component is a lateral insulated gate bipolar transistor, the first electrode is an emitter, the second electrode is a collector, and the lateral insulated gate bipolar transistor further includes a gate.

[0009] In one embodiment, the component is a diode, the first electrode is an anode, and the second electrode is a cathode.

[0010] In one embodiment, the step structure is a step structure, including a first table located on the first side, a second table located on the second side, and a step wall located in the transition area, and the height difference between the second table and the first table is 3 to 10 microns.

[0011] In one embodiment, the inclination angle of the step wall is 20 degrees to 90 degrees.

[0012] In one embodiment, the drift region has a first conductivity type, and the component further includes a second conductivity type protective layer, which is located in the drift region and surrounds the corner formed by the first table and the step wall and the corner formed by the second table and the step wall, and the first conductivity type and the second conductivity type are opposite conductivity types.

[0013] In one embodiment, the component further includes a first electrode lead-out region and a second electrode lead-out region, and the first electrode lead-out region and the second electrode lead-out region are provided on the buried dielectric layer.

[0014] In one embodiment, the component further includes a field oxide layer, and the field oxide layer extends from a second side of the upper surface of the drift region close to the second electrode to a first side close to the first electrode.

[0015] In one embodiment, the component further includes an interlayer dielectric layer, and the interlayer dielectric layer at least covers the field oxide layer, the first electrode lead-out region, and the second electrode lead-out region.

[0016] In a second aspect, a silicon-on-insulator semiconductor process platform is provided, comprising the silicon-on-insulator semiconductor component described in any of the aforementioned embodiments, and further comprising at least one of a complementary metal-oxide-semiconductor field-effect transistor and a well resistor.

[0017] In a third aspect, a method for manufacturing a silicon-on-insulator semiconductor component is provided, comprising: obtaining a wafer, the wafer comprising a substrate, a buried dielectric layer on the substrate, and a drift region on the buried dielectric layer; forming a step structure on the upper surface of the drift region by photolithography and etching, the step structure comprising a first side, a second side, and a transition region between the first side and the second side, the upper surface of the second side being higher than the lower surface of the first side, so that the thickness of the drift region on the second side is greater than the thickness on the first side; forming a first electrode and a second electrode; the first side being a side close to the first electrode, and the second side being a side close to the second electrode; wherein the first electrode and the second electrode are configured such that when a reverse bias is applied to the component, the voltage applied by the second electrode is greater than the voltage applied by the first electrode.

[0018] In one embodiment, the step structure is a step structure, including a first table located on the first side, a second table located on the second side, and a step wall located in the transition region. Before forming the first electrode and the second electrode, the method further includes: forming a protective layer in the drift region at the step structure by ion implantation, and the protective layer surrounds the corner formed by the first table and the step wall and the corner formed by the second table and the step wall.

[0019] In one embodiment, the etching is a reactive ion etching process.

[0020] In a fourth aspect, another method for manufacturing a silicon-on-insulator semiconductor component is provided, comprising: obtaining a wafer, the wafer comprising a substrate, a buried dielectric layer on the substrate, and a first epitaxial layer on the buried dielectric layer; forming a second epitaxial layer in a partial area on the first epitaxial layer, forming a step structure at the junction of the first epitaxial layer and the second epitaxial layer, the step structure comprising a first side on one side of the second epitaxial layer, a second side on one side of the first epitaxial layer, and a transition region between the first side and the second side; forming a first electrode and a second electrode, the first side being a side close to the first electrode, and the second side being a side close to the second electrode; wherein the first electrode and the second electrode are configured such that when a reverse bias is applied to the component, the voltage applied by the second electrode is greater than the voltage applied by the first electrode.

[0021] The details of one or more embodiments of the present application are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the present application will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to better describe and illustrate the embodiments and / or examples of the applications disclosed herein, reference may be made to one or more of the accompanying drawings. The additional details or examples used to describe the accompanying drawings should not be considered to limit the scope of the disclosed applications, the presently described embodiments and / or examples, and any of the best modes currently understood for these applications.

[0023] FIG1 is a schematic cross-sectional view of a device in an embodiment in which the silicon-on-insulator semiconductor component is an LDMOS;

[0024] FIG2a is a schematic cross-sectional view of an SOI LDMOS having a whole protective layer formed thereon in accordance with an embodiment; FIG2b is a schematic cross-sectional view of an SOI LDMOS having protective layers surrounding two corners formed thereon in accordance with an embodiment; and FIG2c is a schematic cross-sectional view of an SOI LDMOS formed using a secondary epitaxial growth method in accordance with an embodiment;

[0025] FIG3 is a schematic diagram of a cross-sectional structure of a device in an embodiment in which the silicon-on-insulator semiconductor component is a LIGBT;

[0026] FIG4 is a cross-sectional schematic diagram of a LIGBT formed by a secondary epitaxial growth method in one embodiment;

[0027] FIG5 is a schematic cross-sectional view of a diode in an embodiment in which the silicon-on-insulator semiconductor component is a diode;

[0028] FIG6 is a cross-sectional schematic diagram of a diode formed by a secondary epitaxial growth method in one embodiment;

[0029] FIG7 is a schematic cross-sectional view of a silicon-on-insulator semiconductor process platform according to an embodiment of the present application;

[0030] FIG8 is a flow chart of a method for manufacturing a silicon-on-insulator semiconductor device according to an embodiment of the present application;

[0031] FIG9 is a flow chart of a method for manufacturing a silicon-on-insulator semiconductor device according to another embodiment of the present application;

[0032] FIG10 is a flowchart of steps between steps S420 and S430 in an embodiment in which the device manufactured is an SOI LDMOS;

[0033] 11a to 11e are schematic cross-sectional views of devices during the process of manufacturing SOI LDMOS according to the method shown in FIG10 ;

[0034] FIG12 is a flowchart of steps between steps S420 and S430 in one embodiment in which the device to be manufactured is an SOI LIGBT;

[0035] 13a to 13e are schematic cross-sectional views of devices during the process of manufacturing an SOI LIGBT according to the method shown in FIG12;

[0036] FIG14 is a flow chart of steps between steps S420 and S430 in one embodiment in which the device to be manufactured is an SOI diode;

[0037] 15a to 15d are schematic cross-sectional views of devices during the process of manufacturing an SOI diode according to the method shown in FIG14 ;

[0038] FIG16 is a schematic cross-sectional view of a silicon-on-insulator semiconductor process platform in one embodiment of forming a drift region step structure by reactive ion etching;

[0039] FIG17 is a schematic diagram of the cross-sectional structure of a silicon-on-insulator semiconductor process platform in an embodiment of forming a drift region step structure using secondary epitaxy. DETAILED DESCRIPTION

[0040] To facilitate understanding of the present application, a more comprehensive description of the present application will be provided below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.

[0041] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0042] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it may be directly on, adjacent to, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there may be no intervening elements or layers. In this specification, "connected" should be understood as "electrically connected," "communicatively connected," etc., if the connected circuits, modules, units, etc. have electrical signals or data transmission with each other. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application.

[0043] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein for convenience of description to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that the spatially relative terms are intended to include different orientations of the device in use and operation in addition to the orientations shown in the figures. For example, if the device in the drawings is flipped, then the elements or features described as "under" or "beneath" or "beneath" the other elements will be oriented as "over" the other elements or features. Thus, the exemplary terms "under" and "under" may include both the upper and lower orientations. The device may be oriented otherwise (rotated 90 degrees or in other orientations) and the spatial descriptors used herein are interpreted accordingly.

[0044] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present application. When used herein, the singular forms "a", "an" and "said / the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It is understood that "at least one" means one or more, and "a plurality" means two or more. "At least a portion of an element" refers to part or all of an element. It should also be understood that the terms "compose" and / or "comprise", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0045] Embodiments of the application are described herein with reference to cross-sectional views which are schematic illustrations of ideal embodiments (and intermediate structures) of the application. As such, variations from the shapes shown due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, embodiments of the application should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the actual shape of the region of the device and are not intended to limit the scope of the application.

[0046] The semiconductor field terms used in this article are technical terms commonly used by those skilled in the art. For example, for P-type and N-type impurities, in order to distinguish the doping concentration, P+ type represents P-type with heavy doping concentration, P-type represents P-type with medium doping concentration, P-type represents P-type with light doping concentration, N+ type represents N-type with heavy doping concentration, N-type represents N-type with medium doping concentration, and N-type represents N-type with light doping concentration.

[0047] For conventional SOI semiconductor process platforms, integrated high-voltage devices can usually only achieve a breakdown voltage of 600V and it is difficult to achieve a breakdown voltage of more than 1200V. Moreover, the withstand voltage of integrated high-voltage devices cannot be increased to more than 1200V by thickening the top silicon, because simply increasing the thickness of the top silicon cannot solve the problem of premature longitudinal breakdown. An exemplary SOI semiconductor process platform uses a structure with a thick buried oxide layer and a thin top silicon layer, which can enable integrated high-voltage devices to achieve a breakdown voltage of 1200V. This is because the breakdown voltage of the device increases with the thickness of the buried oxide layer within a certain range. At the same time, the thin top silicon layer limits the energy obtained by the carriers through the longitudinal electric field, making the device less likely to break down. However, this solution has obvious disadvantages, because the buried oxide layer of the SOI structure blocks the conduction of heat to the substrate, which leads to poor heat dissipation of the device, causing the local lattice temperature of the device to rise, causing the electrical parameters of the device to degrade. These degradation phenomena make the device reliability worse, and this problem is more obvious for devices with a thick buried oxide layer.

[0048] The present application proposes a silicon-on-insulator semiconductor device, comprising:

[0049] substrate;

[0050] A buried dielectric layer is provided on the substrate;

[0051] a first electrode;

[0052] a second electrode;

[0053] a drift region disposed on the buried dielectric layer; a step structure is formed on an upper surface of the drift region, the step structure comprising a first side close to the first electrode, a second side close to the second electrode, and a transition region between the first side and the second side, wherein the upper surface of the second side is higher than the lower surface of the first side, so that the thickness of the drift region on the second side is greater than that on the first side;

[0054] The first electrode and the second electrode are configured such that when a reverse bias is applied to the component, the voltage applied by the second electrode is greater than the voltage applied by the first electrode.

[0055] The above-mentioned silicon-on-insulator semiconductor component adopts a structure in which the thickness of the drift region at the low-voltage end of the device is smaller than the thickness of the drift region at the high-voltage end when a reverse bias is applied. In this way, the breakdown point of the device can be controlled below the high-voltage end, so that the drift region can be completely depleted, and the breakdown voltage of the device can still be improved without increasing the thickness of the buried oxide layer.

[0056] In one embodiment of the present application, the silicon-on-insulator semiconductor device further includes a first electrode lead-out region and a second electrode lead-out region. The first and second electrode lead-out regions are disposed on the buried dielectric layer and have P-type or N-type doping. The first electrode is located on the first electrode lead-out region and is electrically connected to the first electrode lead-out region; the second electrode is located on the second electrode lead-out region and is electrically connected to the second electrode lead-out region.

[0057] In one embodiment of the present application, the drift region has a first conductivity type, and the component also includes a second conductivity type protective layer, which is located in the drift region and surrounds the corner formed by the first table and the step wall and the corner formed by the second table and the step wall, and the first conductivity type and the second conductivity type are opposite conductivity types.

[0058] FIG1 is a schematic diagram of the cross-sectional structure of an embodiment in which the silicon-on-insulator semiconductor device is a lateral double-diffused metal-oxide-semiconductor field effect transistor (LDMOS). The LDMOS includes a substrate 110, a buried dielectric layer 120, a drift region 130, a first electrode 162, a second electrode 164, and a gate 166. The first electrode 162 is the source electrode, and the second electrode 164 is the drain electrode. The upper surface of the drift region 130 is higher on the side closer to the drain electrode (hereinafter referred to as the drift region high side) than on the side closer to the source electrode (hereinafter referred to as the drift region low side), thereby forming a step-down structure 131.

[0059] The LDMOS also includes a first electrode lead-out region (i.e., source region) 142 located on the lower side of the drift region and a second electrode lead-out region (i.e., drain region) 144 located on the upper side of the drift region. A first electrode 162 (i.e., source) is located on the first electrode lead-out region 142 and is electrically connected to the first electrode lead-out region 142. A second electrode 164 (i.e., drain) is located on the second electrode lead-out region 144 and is electrically connected to the second electrode lead-out region 144. In the embodiment shown in FIG1 , the gate 166 extends from the lower side of the drift region to the edge of the first electrode lead-out region 142 and may overlap with the first electrode lead-out region 142 by a certain area.

[0060] 1 , the LDMOS further includes a field oxide layer 147 , which extends from the high side of the drift region to the low side of the drift region. A portion of the gate 166 extends onto the field oxide layer 147 .

[0061] In the embodiment shown in FIG1 , the LDMOS is an N-type LDMOS, the drift region 130 is an N-type drift region, and the LDMOS further includes a P-type body region 132 located on the lower side of the drift region and an N-well 134 located on the upper side of the drift region. A first electrode lead-out region 142 is an N+ region located in the P-type body region 132. A second electrode lead-out region 144 is an N+ region located in the N-well 134.

[0062] In the embodiment shown in FIG1 , the LDMOS further includes a body lead region 146 located in the P-type body region 132 . The body lead region 146 is a P+ region. The first electrode 162 is electrically connected to the body lead region 146 .

[0063] In one embodiment of the present application, the LDMOS further includes an interlayer dielectric (ILD) layer 150. The interlayer dielectric layer 150 covers the gate 166, the field oxide layer 147, the first electrode lead-out region 142, the second electrode lead-out region 144, the body lead-out region 146 and other structures.

[0064] In one embodiment of the present application, the buried dielectric layer 120 is a buried oxide layer, and its material may be silicon dioxide.

[0065] In one embodiment of the present application, the step structure is a stepped structure, including a first mesa located on the first side, a second mesa located on the second side, and a step wall located in the transition region. The height difference between the second mesa and the first mesa (corresponding to H1 in FIG1 ) is 3 to 10 microns. A suitable height difference can ensure complete depletion of the drift region. The step wall has an inclination angle (corresponding to θ1 in FIG1 ) of 20 to 90 degrees. A suitable θ1 can ensure that the device does not break down prematurely at this angle.

[0066] When a reverse bias is applied to the LDMOS, a positive voltage is applied to the drain, and the gate 166, source, and substrate are grounded. The PN junction formed by the P-type body region 132 and the N-type drift region 130 is reverse biased. As the applied bias increases, the space charge region within the lowly doped drift region 130 expands toward the drain. The depletion region within the drift region 130 can extend up to the top surface of the buried oxide layer, and the electric field in this depletion region is virtually unaffected by the substrate 110. The presence of the buried oxide layer improves the device's longitudinal withstand voltage, preventing premature breakdown in the longitudinal direction as the depletion region expands toward the drain. Furthermore, the drift region at the source is thinner than the drift region at the drain. This allows the depletion region to expand more toward the drain when the device is operating in a reverse withstand voltage state, making it easier to deplete from the source to the drain. This allows the drift region 130 to be completely depleted before longitudinal breakdown, limiting the breakdown point to the interface between the drain drift region and the buried oxide layer. In this way, the breakdown voltage of the device can be increased without increasing the thickness of the buried oxide layer, so that the breakdown voltage of the device can reach above 1200V.

[0067] Referring to FIG. 2a , in one embodiment of the present application, the LDMOS further includes a protective layer 136 . The protective layer 136 is located in the drift region 130 , has a conductivity type opposite to that of the drift region 130 , and surrounds the corner formed by the first mesa and the step wall, as well as the corner formed by the second mesa and the step wall. The protective layer 136 can be a single piece as shown in FIG. 2a , or it can be a structure that surrounds both corners separately as shown in FIG. 2b . By forming a protective layer with a conductivity type opposite to that of the drift region 130 at the step corners, premature device breakdown caused by the concentration of electric field lines at the step corners can be avoided.

[0068] In some embodiments of the present application, the aforementioned drift region step structure of the silicon-on-insulator semiconductor component can be formed by a reactive ion etching (RIE) method or a secondary epitaxial method. The secondary epitaxy can obtain a more "vertical" drift region step, see Figure 2c. Figure 2c may be an LDMOS formed by the secondary epitaxy method. The main difference between it and the structure shown in Figure 1 is that the step structure is steeper. Its specific structure is not described here; the structure shown in Figure 1 can be formed by a reactive ion etching method. If the drift region step structure proposed in this application is realized by a single epitaxy plus reactive ion etching method or a secondary epitaxy method, a 1200V silicon-on-insulator semiconductor process platform can be realized; if a conventional single epitaxy method is used, a 600V silicon-on-insulator semiconductor process platform can be realized. Therefore, the 1200V process platform proposed in this application is compatible with the 600V process platform and has good compatibility.

[0069] FIG3 is a schematic diagram of the cross-sectional structure of the device in an embodiment in which the silicon-on-insulator semiconductor component is a lateral insulated gate bipolar transistor (LIGBT). The LIGBT includes a substrate 210, a buried dielectric layer 220, a drift region 230, a first electrode 262, a second electrode 264, and a gate 266. The first electrode 262 is an emitter, and the second electrode 264 is a collector. The upper surface of the drift region 230 is higher on the side close to the collector (hereinafter referred to as the drift region high side) than on the side close to the emitter (hereinafter referred to as the drift region low side), thereby forming a step structure 231.

[0070] The LIGBT in the embodiment shown in FIG3 is an N-type LIGBT. The drift region 230 is an N-type drift region. The LIGBT also includes a P-type first body region 234, a second body region 236, and an N-well 232. The N-well 232 and the second body region 236 are located on the high side of the drift region, while the first body region 234 is located on the low side of the drift region. A first N+ region 242 and a first P+ region 246 are provided in the first body region 234. An emitter 262 is electrically connected to the first N+ region 242 and the first P+ region 246. A second P+ region 248 is provided in the N-well 232, and a second N+ region 244 is provided in the second body region 236. A collector 264 is electrically connected to the second N+ region 244, the second P+ region 248, and the second body region 236. In the embodiment shown in FIG3, a gate 266 extends from the low side of the drift region to the edge of the first N+ region 242 and may overlap with the first N+ region 242 to a certain extent. When reverse bias is applied to the LIGBT, the collector is connected to high voltage and the emitter is connected to low voltage or ground.

[0071] 3 , the LIGBT further includes a field oxide layer 247 extending from the high side of the drift region to the low side of the drift region. A portion of the gate 266 extends onto the field oxide layer 247 .

[0072] In one embodiment of the present application, the LIGBT further includes an interlayer dielectric layer 250. The interlayer dielectric layer 250 covers the gate 266, the field oxide layer 247, the first N+ region 242, the first P+ region 246, the second N+ region 244, the second P+ region 248, the second body region 236 and other structures.

[0073] The LIGBT's drift region step structure can also be formed using reactive ion etching or secondary epitaxy. Secondary epitaxy can produce a more "vertical" drift region step, as shown in Figure 4. The main difference between Figure 4 and Figure 3 is the steeper step structure, the specific structure of which is not detailed here. The structure shown in Figure 3 can be formed using reactive ion etching, with the height difference H2 between the second mesa and the first mesa being 3 to 10 microns, and the step wall inclination angle θ2 being 20 to 90 degrees.

[0074] In one embodiment of the present application, the LIGBT further includes a protective layer. The protective layer is located in the drift region, has a conductivity type opposite to that of the drift region, and surrounds the corner formed by the first mesa and the step wall, as well as the corner formed by the second mesa and the step wall. The protective layer can be a single piece or can be structured to surround the two corners separately.

[0075] Figure 5 is a schematic cross-sectional view of a diode in one embodiment of a silicon-on-insulator semiconductor device. The diode includes a substrate 310, a buried dielectric layer 320, a drift region 330, a first electrode 362, and a second electrode 364. The first electrode 362 is an anode, and the second electrode 364 is a cathode. The upper surface of the drift region 330 is higher on the side closer to the cathode (hereinafter referred to as the drift region high side) than on the side closer to the anode (hereinafter referred to as the drift region low side), thereby forming a stepped structure 331.

[0076] The diode also includes a first electrode lead-out region (i.e., anode region) 342 located on the lower side of the drift region and a second electrode lead-out region (i.e., cathode region) 344 located on the upper side of the drift region. A first electrode 362 (i.e., anode) is located on and electrically connected to the first electrode lead-out region 342. A second electrode 364 (i.e., cathode) is located on and electrically connected to the second electrode lead-out region 344. When a reverse bias is applied to the diode, the cathode is connected to a high voltage, and the anode is connected to a low voltage or ground.

[0077] In the embodiment shown in FIG5 , the drift region 330 is an N-type drift region, and the diode further includes an N-well 334 located on the high side of the drift region. The second electrode lead-out region 344 is an N+ region located in the N-well 334. The first electrode lead-out region 342 is a P+ region located on the low side of the drift region.

[0078] In the embodiment shown in FIG. 5 , the diode further includes a field oxide layer 347 , which extends from the high side of the drift region to the low side of the drift region.

[0079] In one embodiment of the present application, the diode further includes an interlayer dielectric layer 350. The interlayer dielectric layer 350 covers structures such as the field oxide layer 347, the first electrode lead-out region 342, and the second electrode lead-out region 344.

[0080] The diode's drift region step structure can also be formed using reactive ion etching or secondary epitaxy. Secondary epitaxy can produce a more "vertical" drift region step, as shown in Figure 6. The main difference between Figure 6 and Figure 5 is that the step structure is steeper, and its specific structure is not described in detail here. The structure shown in Figure 5 can be formed using reactive ion etching, with the height difference H3 between the second mesa and the first mesa being 3 to 10 microns, and the step wall inclination angle θ3 being 20 to 90 degrees.

[0081] In one embodiment of the present application, the diode further includes a protective layer. The protective layer is located in the drift region, has a conductivity type opposite to that of the drift region, and surrounds the corner formed by the first mesa and the step wall, as well as the corner formed by the second mesa and the step wall. The protective layer can be a single piece or can be structured to surround the two corners separately.

[0082] The present application also provides a silicon-on-insulator semiconductor process platform, which includes the silicon-on-insulator semiconductor components as described in any of the aforementioned embodiments, and also includes low-voltage devices and / or passive devices. In one embodiment of the present application, the low-voltage device can be a complementary metal-oxide-semiconductor field effect transistor (CMOS), and the passive device can be a well resistor. Figure 7 is a schematic diagram of the cross-sectional structure of the silicon-on-insulator semiconductor process platform in one embodiment of the present application. In the embodiment shown in Figure 7, the silicon-on-insulator semiconductor process platform includes LDMOS, LIGBT, diode, CMOS and well resistor. The structures of LDMOS, LIGBT and diode have been introduced above and will not be repeated here. Different devices are isolated from each other by isolation structures. The height of the upper surface of the drift region of the CMOS and well resistor structures is the same as the height of the high side of the drift region.

[0083] The present application accordingly provides a method for manufacturing a silicon-on-insulator semiconductor component, which can be used to manufacture the silicon-on-insulator semiconductor component described in any of the above embodiments. Figure 8 is a flow chart of a method for manufacturing a silicon-on-insulator semiconductor component in one embodiment of the present application. In this embodiment, the drift region step structure is formed by etching. The manufacturing method includes the following steps:

[0084] S410, obtaining a wafer.

[0085] The wafer includes a substrate, a buried dielectric layer on the substrate, and a drift region on the buried dielectric layer. The drift region can be formed by epitaxy on the buried oxide layer.

[0086] S420 , forming a stepped structure on the upper surface of the drift region by photolithography and etching.

[0087] A certain thickness of the drift region (epitaxial layer) is etched away in the area exposed by the photoresist, so that the thickness of the epitaxial layer in the etched area is thinner than that in other parts. That is, the step structure includes a first side, a second side, and a transition region between the first and second sides. The upper surface of the second side is higher than the lower surface of the first side, so that the thickness of the drift region on the second side is thicker than that on the first side.

[0088] In one embodiment of the present application, etching is specifically performed using a reactive ion etching process, which has good anisotropy and can obtain a relatively steep transition zone. In addition, reactive ion etching has a fast etching speed and can accurately control the etching depth.

[0089] S430 , forming a first electrode and a second electrode.

[0090] The first side is a side close to the first electrode, and the second side is a side close to the second electrode.

[0091] The above-mentioned method for manufacturing silicon-on-insulator semiconductor components forms a component having a structure in which (when a reverse bias is applied) the thickness of the drift region at the low-voltage end of the device is less than the thickness of the drift region at the high-voltage end. In this way, the breakdown point of the device can be controlled below the high-voltage end, so that the drift region can be completely depleted, and the breakdown voltage of the device can still be increased without increasing the thickness of the buried oxide layer.

[0092] In one embodiment of the present application, after step S420 and before step S430, a step of forming a protective layer in the drift region at the step structure by ion implantation may also be included. The protective layer surrounds the corner formed by the first mesa and the step wall and the corner formed by the second mesa and the step wall. The conductivity type of the protective layer is opposite to the conductivity type of the drift region. The protective layer can be a whole block structure or a structure that surrounds the two corners respectively. In the embodiment in which the protective layer is a whole block structure, the length of the injection window of the protective layer (the length direction is the length direction of the conductive channel) is 110% to 120% of the length of the transition region (the length direction is the length direction of the conductive channel). Figure 16 is a schematic diagram of the cross-sectional structure of a silicon-on-insulator semiconductor process platform in an embodiment in which reactive ion etching is used to form a step structure in the drift region, in which the protective layer is a whole block structure. In the embodiment in which the protective layer is a structure that surrounds the two corners respectively, the length of each injection window of the protective layer is 5% to 10% of the length of the transition region.

[0093] FIG9 is a flow chart of a method for manufacturing a silicon-on-insulator semiconductor device according to another embodiment of the present application. In this embodiment, the step structure of the drift region is formed by secondary epitaxy, including the following steps:

[0094] S510, obtaining a wafer.

[0095] The wafer includes a substrate, a buried dielectric layer on the substrate, and a first epitaxial layer on the buried dielectric layer.

[0096] S520 , forming a second epitaxial layer in a partial region on the first epitaxial layer.

[0097] Photolithography can be used to expose a portion of the surface of the first epitaxial layer, and then epitaxial growth can be performed to form a second epitaxial layer in the exposed region. This creates a stepped structure at the interface between the first and second epitaxial layers. The stepped structure includes a first side on the side of the second epitaxial layer, a second side on the side of the first epitaxial layer, and a transition region between the first and second sides.

[0098] S530 , forming a first electrode and a second electrode.

[0099] In one embodiment of the present application, the step structure is a step structure, including a first table located on the first side, a second table located on the second side, and a step wall located in the transition zone, the height difference between the second table and the first table is 3 to 10 microns, and the inclination angle of the step wall is 20 degrees to 90 degrees.

[0100] In one embodiment of the present application, after step S520 and before step S530, a step of forming a protective layer in the drift region at the step structure by ion implantation may also be included. The protective layer surrounds the corner formed by the first mesa and the step wall and the corner formed by the second mesa and the step wall. The conductivity type of the protective layer is opposite to that of the drift region. The protective layer can be a whole block structure or a structure that surrounds two corners separately. In the embodiment in which the protective layer is a whole block structure, the length of the injection window of the protective layer (the length direction is the length direction of the conductive channel) is 110% to 120% of the length of the transition region (the length direction is the length direction of the conductive channel). In the embodiment in which the protective layer is a structure that surrounds two corners separately, the length of each injection window of the protective layer is 5% to 10% of the length of the transition region. Figure 17 is a schematic diagram of the cross-sectional structure of a silicon-on-insulator semiconductor process platform in an embodiment in which a drift region step structure is formed by secondary epitaxy. In this embodiment, the protective layer is a structure that surrounds two corners.

[0101] Taking the manufacture of SOI LDMOS as an example, the structure after step S420 is completed is shown in FIG11a. Referring to FIG10, the manufacturing method of SOI LDMOS further includes the following steps after step S420:

[0102] S421, forming a P-type body region and an N-well.

[0103] The P-type body region 132 and the N-well 134 can be formed by photolithography and ion implantation, as shown in Figure 11b. The P-type body region 132 is formed on a first side of the step-down structure, and the N-well 134 is formed on a second side of the step-down structure.

[0104] S422, forming a field oxide layer.

[0105] A field oxide layer 147 is formed on the surface of the drift region 130 and between the P-type body region 132 and the N-well 134, as shown in Figure 11c. The field oxide layer 147 can be formed by deposition or thermal oxidation.

[0106] S423 , forming a gate.

[0107] In the embodiment shown in FIG11 d , the gate 166 extends from the P-type body region 132 to the field oxide layer 147. The gate 166 may be made of polysilicon and may be formed by deposition, photolithography, and etching.

[0108] S424, forming a source region, a drain region and a body lead region.

[0109] Referring to Figure 11e, the N+ source region (i.e., the first electrode lead-out region 142) is formed in the P-type body region 132, the N+ drain region (i.e., the second electrode lead-out region 144) is formed in the N well 134, and the P+ body lead-out region 146 is formed in the P-type body region 132.

[0110] S425 , forming an interlayer dielectric layer and contact holes.

[0111] An interlayer dielectric layer 150 is deposited, and then etched to form contact holes. Step S430 is then performed to form a first electrode 162 and a second electrode 164, resulting in the structure shown in Figure 1. The first electrode 162 is electrically connected to the N+ source region, and the second electrode 164 is electrically connected to the N+ drain region. Steps S421 to S425 described above are applicable not only to embodiments where the drift region step structure is formed by reactive ion etching, but also to embodiments where the drift region step structure is formed by secondary epitaxy. However, the step structure formed by secondary epitaxy is steeper.

[0112] Taking the manufacture of SOI LIGBT as an example, the structure after step S420 is completed is shown in FIG13a. Referring to FIG12, the manufacturing method of SOI LIGBT further includes the following steps after step S420:

[0113] S621 , forming a first body region and an N-well.

[0114] The first body region 234 and the N-well 232 can be formed by photolithography and ion implantation, as shown in Figure 13b. The first body region 234 is formed on a first side of the step-down structure, and the N-well 232 is formed on a second side of the step-down structure.

[0115] S622, forming a field oxide layer.

[0116] A field oxide layer 247 is formed on the surface of the drift region 130, between the first body region 234 and the N-well 232, as shown in Figure 13c. The field oxide layer 247 can be formed by deposition or thermal oxidation.

[0117] S623 , forming a gate.

[0118] In the embodiment shown in FIG13 d , the gate 266 extends from the first body region 234 to the field oxide layer 247. The gate 266 may be made of polysilicon and may be formed by deposition, photolithography, and etching.

[0119] S624 , forming a first N+ region, a second N+ region, a first P+ region, a second P+ region and a second body region.

[0120] 13e, a first N+ region 242 and a first P+ region 246 are formed in the first body region 234. A second P+ region 248 is formed in the N well 232, and a second N+ region 244 is formed in the second body region 236.

[0121] S625 , forming an interlayer dielectric layer and contact holes.

[0122] An interlayer dielectric layer 250 is deposited and then etched to form contact holes. Step S430 is then performed to form a first electrode 262 and a second electrode 264, resulting in the structure shown in FIG3 . The first electrode 262 is electrically connected to the first N+ region 242 and the first P+ region 246, while the second electrode 264 is electrically connected to the second P+ region 248, the second N+ region 244, and the second body region 236. Steps S621 to S625 described above are applicable not only to embodiments in which the drift region step structure is formed by reactive ion etching, but also to embodiments in which the drift region step structure is formed by secondary epitaxy. However, the step structure formed by secondary epitaxy is steeper.

[0123] Taking the manufacture of SOI diode as an example, the structure after step S420 is completed is shown in FIG15a. Referring to FIG14, the manufacturing method of SOI diode further includes the following steps after step S420:

[0124] S721, forming an N-well.

[0125] An N-well 334 may be formed by photolithography and ion implantation, as shown in Figure 15b. The N-well 334 is formed on the second side of the step-down structure.

[0126] S722, forming a field oxide layer.

[0127] A field oxide layer 347 is formed on the surface of the drift region 330, as shown in Figure 15c. The field oxide layer 347 can be formed by deposition or thermal oxidation.

[0128] S723, forming an anode region and a cathode region.

[0129] 15 d , the N+ cathode region (ie, the second electrode lead-out region 344 ) is located in the N well 334 , and the P+ anode region (ie, the first electrode lead-out region 342 ) is formed on the first side of the step-down structure.

[0130] S724, forming an interlayer dielectric layer and contact holes.

[0131] An interlayer dielectric layer 350 is deposited, and then etched to form contact holes. Step S430 is then performed to form a first electrode 362 and a second electrode 364, resulting in the structure shown in FIG5 . The first electrode 362 is electrically connected to the P+ anode region, and the second electrode 364 is electrically connected to the N+ cathode region. Steps S721 to S724 described above are applicable not only to embodiments in which the drift region step structure is formed by reactive ion etching, but also to embodiments in which the drift region step structure is formed by secondary epitaxy. However, the step structure formed by secondary epitaxy is steeper.

[0132] It should be understood that, although the various steps in the flowchart of the present application are shown in sequence as indicated by the arrows, these steps are not necessarily performed in the order indicated by the arrows. Unless otherwise specified herein, there is no strict order restriction on the execution of these steps, and these steps can be performed in other orders. Moreover, at least a portion of the steps in the flowchart of the present application may include multiple steps or multiple stages, and these steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily to be performed in sequence, but can be performed in turn or alternately with other steps or at least a portion of steps or stages in other steps.

[0133] Throughout this specification, references to terms such as "some embodiments," "other embodiments," and "desired embodiments" indicate that a particular feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present application. The schematic descriptions of these terms throughout this specification do not necessarily refer to the same embodiment or example.

[0134] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0135] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A silicon-on-insulator semiconductor component, comprising: substrate; A buried dielectric layer is disposed on the substrate; a first electrode; a second electrode; A drift region, disposed on the buried dielectric layer; A step structure is formed on the upper surface of the drift region, the step structure includes a first side close to the first electrode, a second side close to the second electrode, and a transition region between the first side and the second side, the upper surface of the second side is higher than the lower surface of the first side, so that the thickness of the drift region on the second side is greater than the thickness on the first side; The first electrode and the second electrode are configured such that when a reverse bias is applied to the component, the voltage applied by the second electrode is greater than the voltage applied by the first electrode.

2. The silicon-on-insulator semiconductor device according to claim 1, wherein: The component is a lateral double diffused metal-oxide-semiconductor field effect transistor, the first electrode is a source, the second electrode is a drain, and the lateral double diffused metal-oxide-semiconductor field effect transistor also includes a gate.

3. The silicon-on-insulator semiconductor device according to claim 1, wherein: The component is a lateral insulated gate bipolar transistor, the first electrode is an emitter, the second electrode is a collector, and the lateral insulated gate bipolar transistor further includes a gate.

4. The silicon-on-insulator semiconductor device according to claim 1, wherein: The component is a diode, the first electrode is an anode, and the second electrode is a cathode.

5. The silicon-on-insulator semiconductor device according to any one of claims 1 to 4, wherein: The step structure is a step structure, including a first table located on the first side, a second table located on the second side, and a step wall located in the transition area, and the height difference between the second table and the first table is 3 to 10 microns. 6 . The silicon-on-insulator semiconductor device according to claim 5 , wherein the inclination angle of the step wall is 20 degrees to 90 degrees.

7. The silicon-on-insulator semiconductor device according to claim 5, wherein: The drift region has a first conductivity type, and the component also includes a second conductivity type protection layer, which is located in the drift region and surrounds the corner formed by the first table and the step wall and the corner formed by the second table and the step wall, and the first conductivity type and the second conductivity type are opposite conductivity types. 8 . The silicon-on-insulator semiconductor device according to claim 5 , further comprising a first electrode lead-out region and a second electrode lead-out region, wherein the first electrode lead-out region and the second electrode lead-out region are disposed on the buried dielectric layer. 9 . The silicon-on-insulator semiconductor device according to claim 8 , further comprising a field oxide layer, wherein the field oxide layer extends from a second side of the upper surface of the drift region close to the second electrode to a first side close to the first electrode. 10 . The silicon-on-insulator semiconductor device according to claim 9 , further comprising an interlayer dielectric layer, wherein the interlayer dielectric layer at least covers the field oxide layer, the first electrode lead-out region, and the second electrode lead-out region.

11. A silicon-on-insulator semiconductor process platform, wherein: The silicon-on-insulator semiconductor component comprises the silicon-on-insulator semiconductor component according to any one of claims 1 to 10, and further comprises at least one of a complementary metal-oxide-semiconductor field effect transistor and a well resistor.

12. A method for manufacturing a silicon-on-insulator semiconductor component, comprising: Obtaining a wafer, wherein the wafer includes a substrate, a buried dielectric layer on the substrate, and a drift region on the buried dielectric layer; Forming a step structure on the upper surface of the drift region by photolithography and etching, wherein the step structure includes a first side, a second side, and a transition region between the first side and the second side, wherein the upper surface of the second side is higher than the lower surface of the first side, so that the thickness of the drift region on the second side is greater than the thickness on the first side; forming a first electrode and a second electrode; the first side is a side close to the first electrode, and the second side is a side close to the second electrode; The first electrode and the second electrode are configured such that when a reverse bias is applied to the component, the voltage applied by the second electrode is greater than the voltage applied by the first electrode.

13. The method for manufacturing a silicon-on-insulator semiconductor device according to claim 12, wherein the step structure is a step structure, comprising a first table located on the first side, a second table located on the second side, and a step wall located in the transition region, and before forming the first electrode and the second electrode, the method further comprises: A protection layer is formed in the drift region at the stepped structure by ion implantation, and the protection layer surrounds a corner formed by the first mesa and the step wall and a corner formed by the second mesa and the step wall.

14. The method for manufacturing a silicon-on-insulator semiconductor device according to claim 12, wherein: The etching is a reactive ion etching process.

15. A method for manufacturing a silicon-on-insulator semiconductor component, comprising: Obtaining a wafer, wherein the wafer includes a substrate, a buried dielectric layer on the substrate, and a first epitaxial layer on the buried dielectric layer; Forming a second epitaxial layer on a partial area of ​​the first epitaxial layer, forming a step structure at the junction of the first epitaxial layer and the second epitaxial layer, the step structure comprising a first side on one side of the second epitaxial layer, a second side on one side of the first epitaxial layer, and a transition area between the first side and the second side; forming a first electrode and a second electrode, wherein the first side is a side close to the first electrode, and the second side is a side close to the second electrode; The first electrode and the second electrode are configured such that when a reverse bias is applied to the component, the voltage applied by the second electrode is greater than the voltage applied by the first electrode.

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