Bias circuit, radio frequency circuit, and radio frequency chip

Abstract

The present invention relates to the technical field of wireless communications. Disclosed are a bias circuit, a radio frequency circuit, and a radio frequency chip. The bias circuit comprises a signal input end, an overshoot circuit, a current mirror circuit, a voltage reverse circuit, a bias voltage output circuit, and a signal output end. The signal input end is connected to the current mirror circuit, the voltage reverse circuit and the bias voltage output circuit, respectively. A first end of the overshoot circuit is grounded, and a second end of the overshoot circuit is connected to the current mirror circuit. The signal input end is used for receiving an enable signal. The overshoot circuit is used for generating overshoot to compensate for the response speed of a radio frequency amplifier. The output end of the current mirror circuit is connected to a second input end of the voltage reverse circuit. The output end of the voltage reverse circuit is connected to a second input end of the bias voltage output circuit. A third input end of the bias voltage output circuit is used for being connected to a power supply, and the output end of the bias voltage output circuit is connected to the signal output end. The bias circuit of the present invention enables the transient response effect of the radio frequency amplifier to be fast.

Description

Bias circuit, RF circuit and RF chip Technical Field

[0001] The present invention relates to the field of wireless communication technology, and in particular to a bias circuit, a radio frequency circuit and a radio frequency chip. Background Art

[0002] With the development of communication technology, the continuous development of mobile terminals, and the gradual popularization of communication technology, RF front-end modules have become an important part of wireless communication technology. RF modules are RF chips that contain one or more RF devices, including RF amplifiers, RF switches, and amplifiers.

[0003] In the related art, in a typical TDD (duplex mode of a communication system) system's RF front-end module, such as a WIFI RF front-end module or RF amplifier, it is composed of the following parts: a power amplifier component for amplifying the input RF signal; a receiving circuit component for receiving the signal path, usually including a low-noise amplifier (LNA); an RF switch component for switching the transmit and receive paths; and a logic control component for controlling the working status of other components. The above components are assembled on a substrate, connected together by bonding, and packaged to complete the module. In the TDD RF front-end, the RF amplifier is controlled by an enable signal. When the enable signal is enabled, the bias voltage is activated and the bias voltage or bias current is output to the power amplifier, thereby driving the RF amplifier to work. During the operation of the TDD system, the RF front-end circuit / RF amplifier is always in an alternating state of on / off.

[0004] However, in actual circuits, due to factors such as device characteristics and switching time, the gain of the RF amplifier will increase at the moment it is turned on, resulting in asynchrony between the enable, bias and amplifier gain, resulting in poor transient response of the RF amplifier circuit.

[0005] Summary of the Invention

[0006] An object of the embodiments of the present invention is to provide a bias circuit to solve the problem of poor transient response of a radio frequency amplifier in the related art.

[0007] To solve the above technical problems, in a first aspect, an embodiment of the present invention provides a bias circuit for providing a bias voltage for a radio frequency amplifier, the bias circuit comprising a signal input terminal, an overshoot circuit, a current mirror circuit, a voltage reverse circuit, a bias voltage output circuit, and a signal output terminal; the signal input terminal is respectively connected to a first input terminal of the current mirror circuit, a first input terminal of the voltage reverse circuit, and a first input terminal of the bias voltage output circuit; a first terminal of the overshoot circuit is grounded, and a second terminal of the overshoot circuit is connected to a second input terminal of the current mirror circuit;

[0008] The signal input end is used to receive an enable signal;

[0009] The overshoot circuit is used to generate overshoot to compensate for the response speed of the radio frequency amplifier;

[0010] The output end of the current mirror circuit is connected to the second input end of the voltage inverting circuit;

[0011] The output end of the voltage inverting circuit is connected to the second input end of the bias voltage output circuit, the third input end of the bias voltage output circuit is used to connect to a power supply, and the output end of the bias voltage output circuit is connected to the signal output end.

[0012] Preferably, the overshoot circuit includes a first inductor and a first resistor, the first end of the first resistor serves as the first end of the overshoot circuit, the second end of the first resistor is connected to the first end of the first inductor, and the second end of the first inductor is connected as the second end of the overshoot circuit.

[0013] Preferably, the current mirror circuit includes a first transistor, a second transistor, a second resistor and a third resistor; the first end of the second resistor and the first end of the third resistor respectively serve as the first input end of the current mirror circuit, the second end of the second resistor is connected to the collector of the first transistor, and the collector of the first transistor also serves as the second input end of the current mirror circuit and is connected to the second end of the overshoot circuit; the emitter of the first transistor is grounded, the base of the first transistor is respectively connected to the collector of the first transistor and the base of the second transistor, the emitter of the second transistor is grounded, and the collector of the second transistor serves as the first end of the third resistor and the output end of the current mirror circuit.

[0014] Preferably, the first transistor and the second transistor are both NPN transistors.

[0015] Preferably, the bias circuit further includes a fourth resistor, a first end of the fourth resistor is connected to the output end of the current mirror circuit, and a second end of the fourth resistor is connected to the second input end of the voltage inverting circuit.

[0016] Preferably, the voltage reversal circuit includes a third transistor, a fifth resistor and a sixth resistor, the first end of the fifth resistor serves as the first input end of the voltage reversal circuit, the second end of the fifth resistor is connected to the collector of the third transistor, the collector of the third transistor also serves as the output end of the voltage reversal circuit, the base of the third transistor serves as the second input end of the voltage reversal circuit, the emitter of the third transistor is connected to the first end of the sixth resistor, and the second end of the sixth resistor is grounded.

[0017] Preferably, the bias voltage output circuit includes a fourth transistor, a fifth transistor, a seventh resistor, a sixth transistor and an eighth resistor, the first end of the seventh resistor serving as the first input end of the bias voltage output circuit, the second end of the seventh resistor being connected to the collector of the fourth transistor, the base of the fourth transistor being connected to the collector of the fourth transistor and the base of the sixth transistor respectively, the emitter of the fourth transistor being connected to the collector of the fifth transistor, and the collector of the fifth transistor being also connected to the base of the fifth transistor; the collector of the fifth transistor also serving as the second input end of the bias voltage output circuit, the emitter of the fifth transistor being grounded, the emitter of the sixth transistor serving as the output end of the bias voltage output circuit, the emitter of the sixth transistor being also connected to the first end of the eighth resistor, the second end of the eighth resistor serving as the third input end of the bias voltage output circuit, and the collector of the sixth transistor being grounded.

[0018] Preferably, the fourth transistor, the fifth transistor and the sixth transistor are all NPN transistors.

[0019] In a second aspect, an embodiment of the present invention provides a radio frequency circuit, which includes the above-mentioned bias circuit.

[0020] In a third aspect, an embodiment of the present invention provides a radio frequency chip, which includes the above-mentioned radio frequency circuit.

[0021] Compared with the related art, the bias circuit in the present invention connects the signal input end to the first input end of the current mirror circuit, the first input end of the voltage reverse circuit and the first input end of the bias voltage output circuit respectively, the first end of the overshoot circuit is grounded, and the second end of the overshoot circuit is connected to the second input end of the current mirror circuit. The signal input end is used to receive an enable signal. The overshoot circuit is used to generate overshoot to compensate for the response speed of the radio frequency amplifier. The output end of the current mirror circuit is connected to the second input end of the voltage reverse circuit; the output end of the voltage reverse circuit is connected to the second input end of the bias voltage output circuit, the third input end of the bias voltage output circuit is used to connect to a power supply, and the output end of the bias voltage output circuit is connected to the signal output end. By setting an overshoot circuit in front of the current mirror circuit, an overshoot is generated on the leading edge of the bias voltage to compensate for the response of the RF amplifier, thereby improving the response speed of the RF amplifier at the moment of turning on; the current is amplified by the current mirror circuit, and the output voltage is reversed by the voltage inversion circuit, so that the bias voltage output circuit can make corresponding bias adjustments according to the output voltage, effectively controlling the RF transmission power so that the enable, bias and amplifier gain are carried out synchronously, thereby effectively reducing the implementation complexity of the transmission power control, reducing radiation, reducing energy consumption, and improving the product life. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. Those skilled in the art can also derive other drawings based on these drawings without inventive work, among which:

[0023] FIG1 is a circuit diagram of a bias circuit provided in an embodiment of the present invention;

[0024] FIG2 is a timing waveform diagram of the bias circuit provided in an embodiment of the present invention.

[0025] In the figure, 100, bias circuit, 1, signal input terminal, 2, overshoot circuit, 3, current mirror circuit, 4, voltage reverse circuit, 5, bias voltage output circuit, 6, signal output terminal. DETAILED DESCRIPTION

[0026] The following is a clear and complete description of the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0027] Example 1

[0028] 1-2 , an embodiment of the present invention provides a bias circuit 100 for providing a bias voltage for a radio frequency amplifier. The bias circuit 100 includes a signal input terminal 1, an overshoot circuit 2, a current mirror circuit 3, a voltage reverse circuit 4, a bias voltage output circuit 5, and a signal output terminal 6. The signal input terminal 1 is respectively connected to a first input terminal of the current mirror circuit 3, a first input terminal of the voltage reverse circuit 4, and a first input terminal of the bias voltage output circuit 5. A first terminal of the overshoot circuit 2 is grounded, and a second terminal of the overshoot circuit 2 is connected to a second input terminal of the current mirror circuit 3.

[0029] The signal input terminal 1 is used to receive an enable signal;

[0030] The overshoot circuit 2 is used to generate overshoot to compensate for the response speed of the radio frequency amplifier;

[0031] The output end of the current mirror circuit 3 is connected to the second input end of the voltage reverse circuit 4;

[0032] The output end of the voltage inverting circuit 4 is connected to the second input end of the bias voltage output circuit 5 , the third input end of the bias voltage output circuit 5 is used to connect to the power supply, and the output end of the bias voltage output circuit 5 is connected to the signal output end 6 .

[0033] Among them, the enable signal is output from the signal input terminal 1 to the first input terminal of the current mirror circuit 3, the first input terminal of the voltage reversing circuit 4, and the first input terminal of the bias voltage output circuit 5 respectively; by arranging an overshoot circuit 2 in front of the current mirror circuit 3, an overshoot is generated at the leading edge of the bias voltage to compensate for the response of the RF amplifier, thereby improving the response speed of the RF amplifier at the moment of turning on; the current is amplified by the current mirror circuit 3, and the output voltage is reversed by the voltage reversing circuit 4, so that the bias voltage output circuit 5 can perform corresponding bias adjustment according to the output voltage, effectively controlling the RF transmission power, so that the enable, bias and amplifier gain are carried out synchronously, thereby effectively reducing the implementation complexity of the transmission power control, reducing radiation, reducing energy consumption, and improving the service life of the product.

[0034] In this embodiment, the overshoot circuit 2 includes a first inductor L1 and a first resistor R1, the first end of the first resistor R1 serves as the first end of the overshoot circuit 2, the second end of the first resistor R1 is connected to the first end of the first inductor L1, and the second end of the first inductor L1 serves as the second end of the overshoot circuit 2.

[0035] The addition of the first inductor L1 creates an overshoot on the bias voltage leading edge to compensate for the RF amplifier response, thereby improving the amplifier's response speed upon turn-on. The magnitude and duration of the overshoot can be adjusted by designing the resistance of the first resistor R1 and the inductance of the first inductor L1. For most TDD amplifiers, such as Wi-Fi amplifiers, the overshoot width is within 10µs, and the difference from the normal waveform amplitude is within 200mV. When the enable signal is enabled, the enable pin transitions from a low level to a high level.

[0036] In this embodiment, the current mirror circuit 3 includes a first transistor Q1, a second transistor Q2, a second resistor R2, and a third resistor R3. The first end of the second resistor R2 and the first end of the third resistor R3 respectively serve as the first input end of the current mirror circuit 3. The second end of the second resistor R2 is connected to the collector of the first transistor Q1. The collector of the first transistor Q1 also serves as the second input end of the current mirror circuit 3 and is connected to the second end of the overshoot circuit 2. The emitter of the first transistor Q1 is grounded, the base of the first transistor Q1 is connected to the collector of the first transistor Q1 and the base of the second transistor Q2 respectively, the emitter of the second transistor Q2 is grounded, and the collector of the second transistor Q2 serves as the output end of the current mirror circuit 3. By forming a current mirror with the first transistor Q1 and the second transistor Q2, the current waveform of the first transistor Q1 and the current waveform of the second transistor Q2 are the same. At the same time, the current waveforms of the first transistor Q1 and the second transistor Q2 are consistent. By setting the values ​​of the first resistor R1, the second resistor R2, and the first inductor L1, the overshoot amplitude and duration can be adjusted. For example, reducing the overshoot time improves the response speed of the RF amplifier when it is turned on, thereby synchronizing the RF amplifier's enable, bias, and amplifier gain, effectively reducing the complexity of implementing transmit power control.

[0037] In this embodiment, the first transistor Q1 and the second transistor Q2 are both NPN transistors, which are used to amplify the bias voltage signal and output it to the second input terminal of the voltage inverting circuit 4 through the second transistor Q2.

[0038] In this embodiment, the bias circuit 100 further includes a fourth resistor R4, a first end of which is connected to the output end of the current mirror circuit 3, and a second end of which is connected to the second input end of the voltage inverting circuit 4. The fourth resistor R4 is configured to transmit the voltage output by the second transistor Q2 to the second input end of the voltage inverting circuit 4, so that the voltage inverting circuit 4 receives the voltage and outputs it inversely to the bias voltage output circuit 5. The bias voltage output circuit 5 then outputs the corresponding bias voltage to the signal output end 6, which is then connected to the RF amplifier circuit. Since the leading edge is connected to the first inductor L1, a short overshoot is generated, which accelerates the turn-on time of the RF amplifier and improves the transient response of the amplifier.

[0039] In this embodiment, the voltage reversing circuit 4 includes a third transistor Q3, a fifth resistor R5, and a sixth resistor R6. The first end of the fifth resistor R5 serves as the first input end of the voltage reversing circuit 4. The second end of the fifth resistor R5 is connected to the collector of the third transistor Q3. The collector of the third transistor Q3 also serves as the output end of the voltage reversing circuit 4. The base of the third transistor Q3 serves as the second input end of the voltage reversing circuit 4. The emitter of the third transistor Q3 is connected to the first end of the sixth resistor R6. The second end of the sixth resistor R6 is grounded. The bias voltage is reversely converted by the third transistor Q3, the fifth resistor R5, and the sixth resistor R6 and output to the bias voltage output circuit 5. The bias voltage is then output via the bias voltage input circuit.

[0040] In this embodiment, the bias voltage output circuit 5 includes a fourth transistor Q4, a fifth transistor Q5, a seventh resistor R7, a sixth transistor Q6, and an eighth resistor R8. The first end of the seventh resistor R7 serves as the first input end of the bias voltage output circuit 5. The second end of the seventh resistor R7 is connected to the collector of the fourth transistor Q4. The base of the fourth transistor Q4 is connected to the collector of the fourth transistor Q4 and the base of the sixth transistor Q6, respectively. The emitter of the fourth transistor Q4 is connected to the collector of the fifth transistor Q5. The collector of the fifth transistor Q5 is also connected to the base of the fifth transistor Q5; the collector of the fifth transistor Q5 also serves as the second input terminal of the bias voltage output circuit 5, the emitter of the fifth transistor Q5 is grounded, the emitter of the sixth transistor Q6 serves as the output terminal of the bias voltage output circuit 5, the emitter of the sixth transistor Q6 is also connected to the first end of the eighth resistor R8, the second end of the eighth resistor R8 serves as the third input terminal of the bias voltage output circuit 5, and the collector of the sixth transistor Q6 is grounded.

[0041] In this embodiment, the fourth transistor Q4 , the fifth transistor Q5 , and the sixth transistor Q6 are all NPN transistors.

[0042] In this embodiment, when the enable signal is enabled, the enable pin changes from a low level to a high level at point A. Due to the energy storage effect of the first inductor L1, the current waveform flowing through the collector of the first transistor Q1 is shown as IQ1-C in FIG2 .

[0043] Since the first transistor Q1 and the second transistor Q2 form a current mirror, the current waveform flowing through the collector of the second transistor Q2 is shown as IQ2-C in FIG2 .

[0044] Under the action of the second transistor Q2 and the third resistor R3, the waveform of the voltage at point B is shown as VB in FIG. 2 .

[0045] The voltage at point B is transmitted to the base of the third transistor Q3 through the fourth resistor R4. Under the action of the third transistor Q3, the fifth resistor R5 and the sixth resistor R6, the waveforms of the voltage at point C and the voltage at point D are shown as VC / VD in FIG. 2 .

[0046] The base of the fourth transistor Q4 is connected to the collector of the fourth transistor Q4 , so the waveform of the base voltage of the fourth transistor Q4 is shown as VE in FIG. 2 .

[0047] The voltage at point E passes through the sixth transistor Q6 and is output from the emitter of the sixth transistor Q6 to generate a bias voltage VBIAS. The waveform of the bias voltage is shown in FIG. VBIAS.

[0048] The bias voltage VBIAS is applied to the RF amplifier circuit; since the overshoot circuit 2 set at the leading edge generates a short-time overshoot, the RF amplifier turn-on time is accelerated and the amplifier transient response is improved.

[0049] Example 2

[0050] An embodiment of the present invention provides a radio frequency circuit, comprising the bias circuit 100 described above. The bias circuit 100 of the first embodiment is applied to the radio frequency circuit, causing the bias circuit 100 to output a bias voltage, which is applied to the radio frequency amplifier circuit. Because the leading edge generates a short overshoot, the turn-on time of the radio frequency amplifier is accelerated, thereby improving the transient response of the amplifier.

[0051] Example 3

[0052] An embodiment of the present invention provides a radio frequency chip, which includes the radio frequency circuit of the second embodiment, and can effectively reduce the complexity of implementing transmit power control, reduce radiation, reduce energy consumption, and extend product life.

[0053] The above descriptions are merely embodiments of the present invention and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention description and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A bias circuit for providing a bias voltage for a radio frequency amplifier, characterized in that: The bias circuit comprises a signal input terminal, an overshoot circuit, a current mirror circuit, a voltage inversion circuit, a bias voltage output circuit and a signal output terminal; the signal input terminal is respectively connected to a first input terminal of the current mirror circuit, a first input terminal of the voltage inversion circuit and a first input terminal of the bias voltage output circuit, a first terminal of the overshoot circuit is grounded, and a second terminal of the overshoot circuit is connected to a second input terminal of the current mirror circuit; The signal input terminal is used to receive an enable signal; The overshoot circuit is used to generate overshoot to compensate for the response speed of the radio frequency amplifier; The output end of the current mirror circuit is connected to the second input end of the voltage inversion circuit; The output end of the voltage inverting circuit is connected to the second input end of the bias voltage output circuit, the third input end of the bias voltage output circuit is used to connect to a power supply, and the output end of the bias voltage output circuit is connected to the signal output end.

2. The bias circuit according to claim 1, wherein: The overshoot circuit includes a first inductor and a first resistor, the first end of the first resistor serves as the first end of the overshoot circuit, the second end of the first resistor is connected to the first end of the first inductor, and the second end of the first inductor is connected as the second end of the overshoot circuit.

3. The bias circuit according to claim 1, wherein: The current mirror circuit includes a first transistor, a second transistor, a second resistor and a third resistor; the first end of the second resistor and the first end of the third resistor respectively serve as the first input end of the current mirror circuit, the second end of the second resistor is connected to the collector of the first transistor, and the collector of the first transistor is also connected to the second end of the overshoot circuit as the second input end of the current mirror circuit; the emitter of the first transistor is grounded, the base of the first transistor is respectively connected to the collector of the first transistor and the base of the second transistor, the emitter of the second transistor is grounded, and the collector of the second transistor is respectively connected to the first end of the third resistor and the output end of the current mirror circuit.

4. The bias circuit according to claim 3, wherein: The first transistor and the second transistor are both NPN transistors.

5. The bias circuit according to claim 1, wherein: The bias circuit further includes a fourth resistor, a first end of the fourth resistor is connected to the output end of the current mirror circuit, and a second end of the fourth resistor is connected to the second input end of the voltage inversion circuit.

6. The bias circuit according to claim 5, wherein: The voltage reversal circuit includes a third transistor, a fifth resistor and a sixth resistor. The first end of the fifth resistor serves as the first input end of the voltage reversal circuit, the second end of the fifth resistor is connected to the collector of the third transistor, the collector of the third transistor also serves as the output end of the voltage reversal circuit, the base of the third transistor serves as the second input end of the voltage reversal circuit, the emitter of the third transistor is connected to the first end of the sixth resistor, and the second end of the sixth resistor is grounded.

7. The bias circuit according to claim 1, wherein: The bias voltage output circuit includes a fourth triode, a fifth triode, a seventh resistor, a sixth triode and an eighth resistor, wherein a first end of the seventh resistor serves as a first input end of the bias voltage output circuit, a second end of the seventh resistor is connected to the collector of the fourth triode, a base of the fourth triode is respectively connected to the collector of the fourth triode and the base of the sixth triode, an emitter of the fourth triode is connected to the collector of the fifth triode, and a collector of the fifth triode is also connected to the base of the fifth triode; the collector of the fifth triode also serves as a second input end of the bias voltage output circuit, an emitter of the fifth triode is grounded, an emitter of the sixth triode serves as an output end of the bias voltage output circuit, an emitter of the sixth triode is also connected to a first end of the eighth resistor, a second end of the eighth resistor serves as a third input end of the bias voltage output circuit, and a collector of the sixth triode is grounded.

8. The bias circuit according to claim 7, wherein: The fourth transistor, the fifth transistor and the sixth transistor are all NPN transistors.

9. A radio frequency circuit, characterized in that: The radio frequency circuit comprises the bias circuit as described in any one of claims 1-8.

10. A radio frequency chip, characterized in that: The radio frequency chip includes the radio frequency circuit according to claim 9.

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