Output circuit

Abstract

In an output circuit (1), a first P-type transistor (P1) has a source connected to VDD1 and a drain connected to an output node (out) via a node (na) and a second P-type transistor (P2). A third P-type transistor (P3) has a source connected to VDD2, a drain and a back gate connected to the node (na), and a gate connected to the output node (out). A voltage generation circuit (20) outputs the higher voltage of VDD1 or VDD2 to a back gate of the first P-type transistor (P1) in the rising transition state of VDD1 and VDD2, and outputs VDD1 to the back gate of the first P-type transistor (P1) in a normal state.

Description

Output Circuit

[0001] The present disclosure relates to an output circuit that outputs a signal to the outside of a semiconductor device (LSI (Large Scale Integration)).

[0002] As transistors become smaller, the voltage stress (breakdown voltage) that transistors can tolerate is decreasing. Therefore, output circuits that use low-breakdown-voltage transistors (hereinafter referred to as "low-breakdown-voltage transistors") to output high-voltage signals are known. Circuits that use low-breakdown-voltage transistors to transmit and receive signals with voltages exceeding their breakdown voltages use a structure in which transistors are cascaded to maintain the voltage applied to the transistors at or below their breakdown voltages.

[0003] For example, Patent Document 1 discloses an output circuit that prevents the voltage of the intermediate node of cascaded transistors from becoming unstable and fluctuating inadvertently during operation, while maintaining the voltage applied to the transistors at or below their withstand voltage.

[0004] Patent No. 5987619

[0005] However, the output circuit of Patent Document 1 may have an unnecessary current flowing in the circuit when the power is turned on, and there is a problem in reducing power consumption.

[0006] In view of the above problems, an object of the present disclosure is to provide an output circuit that solves the above problems.

[0007] In one aspect of the present disclosure, an output circuit receives a data input signal and outputs an output signal that changes in response to the data input signal, the output circuit comprising: a first P-type transistor having a source connected to a first power supply node, a drain connected to a first node, and a back gate connected to a second node; a second P-type transistor having a source connected to the first node, a drain connected to an output node from which the output signal is output, and a back gate connected to the first node; a third P-type transistor having a source connected to a second power supply node, a drain and a back gate connected to the first node, and a gate connected to the output node; and a voltage generation circuit that outputs the higher of the voltage of the first power supply node and the voltage of the second power supply node to the second node in a rising transition state of the voltage of the first power supply node and / or the second power supply node, and that outputs the voltage of the first power supply node to the second node in a normal state.

[0008] According to this aspect, in the output circuit, a voltage generating circuit is connected to the back gate (second node) of the first P-type transistor, and the voltage generating circuit is configured to output a higher voltage to the second node in a rising transition state of the voltages of the first power supply node and / or the second power supply node, and to output the voltage of the first power supply to the second node in a normal state.

[0009] As a result, unnecessary current is not generated in the output circuit during the rising transition of the voltage of the first power supply node and / or the second power supply node. Also, in the normal state, the intermediate node between the cascade-connected first P-type transistor and the second P-type transistor is fixed at a predetermined value without becoming unstable, thereby maintaining the effect of Patent Document 1.

[0010] According to the present disclosure, no unnecessary current is generated in the output circuit during the power supply rising transition state, and in the normal state, the voltage at the intermediate node between the cascaded first P-type transistor and second P-type transistor can be prevented from becoming unstable and fluctuating inadvertently, while the voltage applied to each transistor can be maintained below its withstand voltage.

[0011] Circuit configuration diagram of an output circuit according to the first embodiment Circuit configuration diagram of a voltage generating circuit according to the first embodiment Circuit configuration diagram of an output circuit according to the second embodiment Circuit configuration diagram of a voltage generating circuit according to the second embodiment Circuit configuration diagram of a voltage generating circuit according to the second embodiment Circuit configuration diagram of a voltage generating circuit according to the third embodiment Diagram showing connection example 1 of an output circuit Diagram showing connection example 2 of an output circuit Diagram showing connection example 3 of an output circuit

[0012] Hereinafter, embodiments will be described with reference to the drawings.

[0013] In the circuit configuration diagrams shown below, the illustrations are simplified and focus on the components related to the present disclosure. Therefore, for example, components illustrated as being directly connected may in the actual circuit configuration have other components interposed therebetween, resulting in an indirect connection. In other words, in the present disclosure, "connection" is a concept that broadly encompasses electrical connection, and includes not only direct connection but also indirect electrical connection via passive elements, etc.

[0014] In the following description, the nodes and terminals of the circuit and the signals passing through those nodes and terminals may be described using common symbols or names, and the names of power supplies and the voltages of those power supplies may be described using common symbols. Furthermore, the voltage of a terminal or node may be described as "(terminal name or node name) = (symbol indicating voltage)" or simply as "symbol indicating voltage." Specifically, for example, if the voltage of the output node out is VDD1, it may be described as "out = VDD1" or simply as "VDD1."

[0015] First Embodiment Fig. 1 is a circuit diagram of an output circuit 1 according to a first embodiment. The output circuit 1 in Fig. 1 receives a data input signal in and outputs an output signal out that changes in response to the data input signal in. The output signal out is output from an output node out. The output circuit 1 is provided, for example, in a signal output section of an LSI (see Figs. 7 to 9). In this case, the output node out is connected, for example, to an output pad of the LSI. Figs. 7 to 9 will be described later.

[0016] An external power supply VDD0 and an external power supply VDD2 are supplied to the output circuit 1 from outside the LSI on which the output circuit 1 is mounted. In the configuration of Fig. 1, the same voltage as the external power supply VDD0 is supplied to a power supply node VDD1 (corresponding to a first power supply node) of the output circuit 1. Furthermore, the voltage of the external power supply VDD2 is supplied to a power supply node VDD2.

[0017] Here, the voltage of the external power supply VDD0, i.e., VDD0 and VDD1, is higher than VDD2. The data input signal in varies between VDD2 and the voltage VSS of the ground node VSS (hereinafter also simply referred to as "VSS"). The output signal out varies between VDD1 and VSS in response to the data input signal in.

[0018] The output circuit 1 includes a level shift circuit 60, buffer circuits 40 and 50, P-type transistors P1, P2, and P3, N-type transistors N1, N2, and N3, and a voltage generation circuit 20. In this disclosure, each transistor is a metal oxide semiconductor field effect transistor (MOSFET). The breakdown voltage of each transistor is approximately VDD2, and the output circuit 1 is configured to output VDD1, which is higher than the breakdown voltage of each transistor. In the output stage of the output circuit 1, the P-type transistors P1 and P2 and the N-type transistors N1 and N2, to which VDD1 is applied, are cascade-connected. The specific configuration will be described below.

[0019] The level shift circuit 60 receives a data input signal in and an enable signal en as inputs. When the enable signal en is on (e.g., high level), the output circuit 1 performs normal operation (hereinafter simply referred to as "normal operation"), outputting an output signal out that changes according to the data input signal in. When the enable signal en is off (e.g., low level), the output of the output circuit 1 enters a high impedance state (hereinafter referred to as "non-operation state"). For example, the high level of the enable signal is VDD2, and the low level is VSS. The specific configuration of the level shift circuit 60 is not particularly limited, and a commonly known level shift circuit can be applied.

[0020] During normal operation, the level shift circuit 60 outputs to the node nf a signal nf that transitions between VDD1 and VDD2 in response to the data input signal in, and outputs to the node ng a signal ng that transitions between VDD2 and VSS in response to the data input signal in. In the non-operational state, the level shift circuit 60 outputs nf=VDD1 to the node nf and outputs ng=VSS to the node ng regardless of the data input signal in.

[0021] The buffer circuit 40 has an input connected to the node nf and an output connected to the gate of the P-type transistor P1 via the node nc. The specific configuration of the buffer circuit 40 is not particularly limited, and a conventional, widely known buffer circuit can be applied.

[0022] The buffer circuit 40 receives a signal nf that changes between VDD1 and VDD2, and applies a gate signal nc that changes between VDD1 and VDD2 in response to a data input signal in to the gate of the P-type transistor P1.

[0023] The P-type transistor P1 (corresponding to the first P-type transistor) has a source connected to the power supply node VDD1 and a drain connected to the output node out via the P-type transistor P2. That is, the P-type transistor P1 is cascade-connected to the output node out. More specifically, the P-type transistor P1 has a source connected to the power supply node VDD1 and a drain connected to a node na (corresponding to the first node). The P-type transistor P2 (corresponding to the second P-type transistor) has a gate connected to the power supply node VDD2, a source connected to the node na, and a drain connected to the output node out. The P-type transistor P3 (corresponding to the third P-type transistor) is provided between the power supply node VDD2 and the node na, and has a gate connected to the output node out.

[0024] When the gate signal nc changes from high level (VDD1) to low level (VDD2), the P-type transistor P1 changes from a non-conductive state to a conductive state. As a result, the potential of the output signal out is raised toward VDD1, and the output signal out transitions to a high level (VDD1). The specific operation of the output circuit 1 will be described in detail later.

[0025] The buffer circuit 50 has an input connected to the node ng and an output connected to the gate of the N-type transistor N2 via the node nd. The specific configuration of the buffer circuit 50 is not particularly limited, and a conventional buffer circuit that is widely known can be applied.

[0026] The buffer circuit 50 receives a signal ng that changes between VDD2 and VSS, and supplies a gate signal nd that transitions between VDD2 and VSS in response to a data input signal in to the gate of an N-type transistor N2 (corresponding to a first N-type transistor).

[0027] The source of the N-type transistor N2 is grounded to the ground node VSS, and the drain is connected to the output node out via the N-type transistor N1 (corresponding to the second N-type transistor). That is, the N-type transistor N2 is cascade-connected to the output node out. More specifically, the source of the N-type transistor N2 is connected to the ground node VSS, and the drain is connected to the node nb. The N-type transistor N1 has a gate connected to the power supply node VDD2, a source connected to the node nb (corresponding to the third node), and a drain connected to the output node out. The N-type transistor N3 (corresponding to the third N-type transistor) is provided between the power supply node VDD2 and the node nb, and has a gate connected to the output node out.

[0028] When the gate signal nd changes from low level (VSS) to high level (VDD2), the N-type transistor N2 changes from a non-conductive state to a conductive state, thereby pulling down the potential of the output signal out toward VSS, and the output signal out transitions to a low level (VSS).

[0029] The voltage generating circuit 20 outputs the higher of VDD1 and VDD2 to node ne (corresponding to the second node) in a rising transition state (hereinafter also referred to as a "power supply startup state") of the external power supply VDD0 and / or the external power supply VDD2. Furthermore, the voltage generating circuit 20 outputs VDD1 to node ne when the external power supplies VDD0 and VDD2 are in a normal state (hereinafter simply referred to as a "normal state") and the output circuit 1 is in a normal operation state or in a non-operation state. The "normal power supply state (normal state)" refers to a state in which a predetermined power supply voltage is supplied from the external power supplies VDD0 and VDD2. In other words, this is a state in which the output circuit 1 can operate normally with the supply from the external power supplies VDD0 and VDD2. The "normal state" also includes a state in which the power supply voltage of the external power supply VDD0 and / or the external power supply VDD2 fluctuates around a predetermined voltage due to various factors such as the operation of the output circuit 1.

[0030] Fig. 2 shows an example of the configuration of the voltage generating circuit 20. Note that the voltage generating circuit 20 may be realized by a circuit other than that shown in Fig. 2 that has the functions described in the above paragraph.

[0031] 2, the voltage generating circuit 20 includes P-type transistors P4 and P5. The P-type transistor P4 (corresponding to a fourth P-type transistor) has a source connected to a power supply node VDD1, a drain and a back gate connected to a node ne, and a gate connected to a power supply node VDD2. The P-type transistor P5 (corresponding to a fifth P-type transistor) has a source connected to a power supply node VDD2, a drain and a back gate connected to the node ne, and a gate connected to a power supply node VDD1.

[0032] --Operation of Output Circuit-- The operation of the output circuit 1 according to this embodiment will be described below.

[0033] [Power Supply Start-Up State: When External Power Supplies (VDD0, VDD2) are Turned On] From the viewpoint of lowering the voltage between the nodes of each transistor, the order of turning on the power supplies at the start of the external power supplies is such that the external power supply VDD2, which has a relatively low voltage, is turned on first, followed by the external power supply VDD0, which has a relatively high voltage. Furthermore, while the voltage is rising, the relationship VDD0 (VDD1) < VDD2 is maintained.

[0034] When the external power supplies VDD0 and VDD2 rise and the potential difference between the power supply nodes VDD2 and VDD1 (the gate-source voltage of the P-type transistor P5) exceeds the threshold voltage, the P-type transistor P5 turns on, and the node ne and the power supply node VDD2 become conductive.

[0035] At this time, a PN junction diode (not shown) of the P-type transistor P3 is formed between the power supply node VDD2 and the node na. However, as described above, since the node ne and the power supply node VDD2 are conductive, the power supply node VDD2 is not conductive with the power supply node VDD1 via the nodes na and ne, and no current flows. In other words, the output circuit 1 is configured so that no unnecessary current flows when the external power supply is turned on.

[0036] [Normal Operation] Next, a normal operation of the output circuit 1 after the external power supplies VDD0 and VDD2 have returned to their normal states will be described, that is, the operation when the enable signal en is at a high level.

[0037] As described above, in the normal state, the power supply node VDD1 is supplied with VDD1, which is the same voltage as VDD0. The power supply node VDD2 is supplied with VDD2, which is lower than VDD1.

[0038] In the voltage generating circuit 20, the P-type transistor P4 is turned on and the P-type transistor P5 is turned off, thereby establishing electrical continuity between the node ne and the power supply node VDD1.

[0039] When a high level is input as the data input signal in, nc=VDD1 and nd=VDD2. This causes the P-type transistor P1 to turn off, the N-type transistors N1 and N2 to turn on, and a low level (VSS) is output to the output node out. At this time, the P-type transistor P3 turns on, so that the node na and the power supply node VDD2 become conductive. As a result, the node na does not become undefined.

[0040] When a low level is input as the data input signal in, nc=VDD2 and nd=VSS. This causes P-type transistors P1 and P2 to turn on, N-type transistors N1 and N2 to turn off, and a high level (VDD1) is output to the output node out. At this time, N-type transistor N3 turns on, so node nb and power supply node VDD2 become conductive. As a result, node nb does not become undefined.

[0041] [Stopped State] Next, the stopped state of the output circuit 1 after the external power supplies VDD0 and VDD2 have returned to their normal states will be described, that is, the operation when the enable signal en is at a low level will be described.

[0042] As described above, in the non-operational state, the level shift circuit 60 outputs nf=VDD1 and ng=VSS regardless of the data input signal in. Therefore, nc=VDD1 and nd=VSS. This turns off the P-type transistor P1 and the N-type transistor N2, and the output node out becomes an undefined state (Hi-Z).

[0043] Here, for example, if the output node out becomes out<VDD2 and the potential difference exceeds the threshold voltage between the gate and source of the P-type transistor P3, the P-type transistor P3 turns on, and the node na and VDD2 become conductive. Then, when the gate-source and drain voltages of the P-type transistor P2 fall below the threshold voltage, P2 turns off. In this way, the node na and VDD2 become conductive, and the node na does not become undefined.

[0044] Furthermore, for example, when output node out becomes out>VDD2 and the potential difference exceeds the threshold voltage between the gate and source of N-type transistor N3, N-type transistor N3 turns on, and node nb and VDD2 become conductive. When the gate-source and drain voltages of N-type transistor N1 fall below the threshold voltage, N1 turns off. In this way, node nb and VDD2 become conductive, and node nb does not become undefined.

[0045] - Effects of the Present Embodiment - As described above, in the present embodiment, the voltage generation circuit 20 is connected to the back gate of the P-type transistor P1 in the output circuit 1. The voltage generation circuit 20 is configured to output the higher voltage of the power supply node VDD1 or the power supply node VDD2 to the node ne when the external power supplies VDD0 and VDD2 transition to rising edges, and to output the voltage of the first power supply to the node ne in the normal state.

[0046] As a result, when the external power supplies VDD0 and VDD2 transition to rising, i.e., when the power supply is started up, no unnecessary current is generated in the output circuit 1. Furthermore, in the normal state, the intermediate node between the cascaded P-type transistors P1 and P2 and the intermediate node between the cascaded N-type transistors N1 and N2 in the output stage are fixed to predetermined values ​​without becoming unstable, thereby maintaining the effect of Patent Document 1.

[0047] Second Embodiment An output circuit 2 according to this embodiment will be described below.

[0048] FIG. 3 is a circuit diagram of an output circuit 2 according to this embodiment. In FIG. 3, components corresponding to those in FIG. 1 are assigned common reference numerals. The following description will focus on differences from the first embodiment. Note that there is no intention to limit the configurations and various design parameters / process parameters, etc., of blocks and elements (e.g., transistors) assigned the same reference numerals in FIGS. 1 and 3 to those elements. In other words, the technical scope of the present disclosure includes configurations in which the various parameters of elements assigned the same reference numerals in FIGS. 1 and 3 differ from each other. The same applies to the relationships between the other drawings.

[0049] -Power Supply- In this embodiment, the voltage applied to each power supply node of the output circuit 2 is different from that in the first embodiment.

[0050] Specifically, in the output circuit 2, a voltage is applied from the external power supply VDD0 to a power supply node VDD1 via a step-down circuit 10, and a voltage is applied from the external power supply VDD0 to a power supply node Vbias via a step-down circuit 11.

[0051] The step-down circuit 10 outputs a voltage that is stepped down from VDD0 to VDD2 to the power supply node VDD1, that is, the relationship VDD1=VDD2 is established.

[0052] The step-down circuit 11 steps down VDD0 to Vbias and outputs the resulting voltage to the power supply node Vbias. Vbias is lower than VDD2, i.e., VDD2>Vbias.

[0053] Furthermore, similarly to the first embodiment, VDD2 is supplied from the external power supply VDD2 via the power supply node VDD2.

[0054] - Output Circuit - The output circuit 2 includes a level shift circuit 60, buffer circuits 40 and 50, P-type transistors P1, P2, and P3, N-type transistors N1, N2, and N3, and voltage generation circuits 20, 30, and 70. Here, the differences from the first embodiment will be mainly described. The voltage generation circuit 20 has the same configuration as in the first embodiment.

[0055] In a power-on state, the voltage generating circuit 70 outputs the higher voltage of VDD2 or Vbias. In a normal state and when the output circuit 2 is in a normal operation state or in a non-operation state, the voltage generating circuit 70 outputs VDD2.

[0056] Fig. 5 shows an example of the configuration of the voltage generating circuit 70. Note that the voltage generating circuit 70 may be realized by a circuit other than that shown in Fig. 5 that has the functions described in the above paragraph.

[0057] 5, the voltage generating circuit 70 includes P-type transistors P8 and P9. The P-type transistor P8 has a source connected to the power supply node VDD2, a drain and a back gate connected to the power supply node VDD2a, and a gate connected to the power supply node Vbias. The P-type transistor P9 has a source connected to the power supply node Vbias, a drain and a back gate connected to the power supply node VDD2a, and a gate connected to the power supply node VDD2.

[0058] The voltage generating circuit 30 (corresponding to a second voltage generating circuit) outputs the higher voltage of VDD1 or VDD2 to the node nh in a power-on state. The voltage generating circuit 30 also outputs VDD1 to the node nh in a normal state and when the output circuit 2 is in a normal operation state or in a stopped operation state.

[0059] 4 shows an example of the configuration of the voltage generating circuit 30 and its peripheral circuits according to this embodiment. Note that the voltage generating circuit 30 may be realized by a circuit other than that shown in FIG. 4 that has the functions described above.

[0060] 4, the voltage generating circuit 30 includes P-type transistors P6 and P7 and a pull-down circuit 31.

[0061] The P-type transistor P6 (corresponding to the fourth P-type transistor or the sixth P-type transistor) has a source connected to the power supply node VDD1, a drain and a back gate connected to the node nh, and a gate connected to the power supply node VDD2. The P-type transistor P7 (corresponding to the fifth P-type transistor or the seventh P-type transistor) has a source connected to the power supply node VDD2, a drain and a back gate connected to the node nh, and a gate connected to the power supply node VDD1.

[0062] The pull-down circuit 31 includes cascade-connected N-type transistors N4 and N5 between node nh and a ground node VSS. The drain of the N-type transistor N4 is connected to node nh, and the gate is connected to a power supply node VDD2a. The source of the N-type transistor N5 is connected to the ground node VSS, the drain is connected to the source of the N-type transistor N4, and an enable signal en is applied to the gate via a node en.

[0063] The gate of the P-type transistor P2 is connected to a node nc connected to the output of the buffer circuit 40, instead of the power supply node VDD2 in the first embodiment. Moreover, the gate of the P-type transistor P1 is connected to a node nh connected to the voltage generating circuit 30, instead of the node nc. The P-type transistor P3 is provided between the power supply node VDD2a and the node na, and has its gate connected to the output node out.

[0064] During normal operation, the level shift circuit 60 outputs a signal nf that changes between VDD2a and VSS in response to the data input signal in to a node nf, and outputs a signal ng that changes between VDD2a and VSS in response to the data input signal in to a node ng. In an operation-stopped state, the level shift circuit 60 outputs nf=VDD2a to the node nf and outputs ng=VSS to the node ng, regardless of the data input signal in.

[0065] As in the first embodiment, the specific configuration of the level shift circuit 60 is not particularly limited, and a conventional, widely known level shift circuit can be applied.

[0066] The buffer circuit 40 receives a signal nf that changes between VDD2a and VSS, and provides a gate signal nc that changes between VDD2a and VSS in response to a data input signal in to the gate of the P-type transistor P2. The buffer circuit 50 receives a signal ng that changes between VDD2a and VSS, and provides a gate signal nd that changes between VDD2a and VSS in response to the data input signal in to the gate of the N-type transistor N2. As with the first embodiment, the specific configurations of the buffer circuits 40 and 50 are not particularly limited, and conventionally known general buffer circuits can be applied.

[0067] The connection configuration of the N-type transistors N1, N2, and N3 is the same as in the first embodiment.

[0068] - Operation of Output Circuit - The operation of the output circuit 2 according to this embodiment will be described below, focusing on the differences from the first embodiment.

[0069] [Power Supply Start-Up State: When External Power Supplies (VDD0, VDD2) are Turned On] (Part 1) Here, we will explain the case where the order of turning on the power supplies when the external power supplies are turned on is such that the external power supply VDD2 is turned on before the external power supply VDD0, and while the voltage is rising, the relationship VDD0 (VDD1) < VDD2 is maintained.

[0070] At this time, the voltage generating circuit 20 operates in the same manner as in the first embodiment, and the node ne and the power supply node VDD2 are electrically connected.

[0071] In the voltage generating circuit 70, when the external power supplies VDD0 and VDD2 make a rising transition and the potential difference between the power supply node Vbias and the power supply node VDD2 (the gate-source voltage of the P-type transistor P8) exceeds the threshold voltage, the P-type transistor P8 turns on, and the power supply nodes VDD2 and VDD2a become conductive. At this time, a PN junction diode (not shown) of the P-type transistor P3 is formed between the power supply node VDD2a and the node na, but due to the same principle as in the first embodiment, the power supply node VDD2a does not become conductive with the power supply node VDD1 via the nodes na and ne.

[0072] Similarly, in the voltage generating circuit 30, when the potential difference between the power supply nodes VDD2 and VDD1 (the gate-source voltage of the P-type transistor P7) exceeds the threshold voltage, the P-type transistor P7 turns on, and the node nh and the power supply node VDD2 become conductive. At this time, the enable signal en is not input, i.e., the enable signal is at a low level. Therefore, the N-type transistor N5 turns off, nh=VDD2, and the P-type transistor P1 turns off. As a result, the power supply node VDD2a does not become conductive with the power supply node VDD1 via the P-type transistor P1.

[0073] (Part 2) Here, a case where the relationships VDD0 (VDD1)>VDD2 and Vbias>VDD2 are established while the voltage is rising in the power-on state will be described.

[0074] In the voltage generating circuit 20, when the potential difference between the power supply nodes VDD1 and VDD2 (the gate-source voltage of the P-type transistor P4) exceeds the threshold voltage, the P-type transistor P4 turns on, and the node ne and the power supply node VDD1 become conductive.

[0075] In the voltage generating circuit 30, when the potential difference between the power supply nodes VDD1 and VDD2 (the gate-source voltage of the P-type transistor P6) exceeds the threshold voltage, the P-type transistor P6 turns on, and the node nh and the power supply node VDD1 become conductive. As in the case of "Part 1," the enable signal is at a low level, and the N-type transistor N5 and the P-type transistor P1 are turned off. As a result, the power supply node VDD2a is not conductive with the power supply node VDD1 via the node ne and the P-type transistor P1.

[0076] In the voltage generating circuit 70, when the potential difference between the power supply node Vbias and the power supply node VDD2 (the gate-source voltage of the P-type transistor P9) exceeds the threshold voltage, the P-type transistor P9 turns on, and the power supply node Vbias and the power supply node VDD2a become conductive. As a result, the voltage of the node na rises via the PN junction diode (not shown) of the P-type transistor P3, so that the node na does not become unstable. In addition, the voltage between each node of the P-type transistor P1 drops.

[0077] [Normal Operation] Next, a normal operation of the output circuit 2 after the external power supplies VDD0 and VDD2 have returned to their normal states will be described, that is, an operation when the enable signal en is at a high level.

[0078] As described above, in the normal state, the power supply node VDD1 is supplied with the voltage output from the step-down circuit 10, and the power supply node Vbias is supplied with the voltage output from the step-down circuit 10. The magnitude relationship between the voltages is VDD0>VDD1=VDD2>Vbias.

[0079] In the voltage generating circuit 70, when the potential difference between the power supply node Vbias and the power supply node VDD2 (the gate-source voltage of the P-type transistor P8) exceeds the threshold voltage, the P-type transistor P8 turns on, and the power supply nodes VDD2 and VDD2a become conductive. That is, VDD2a=VDD2.

[0080] In the voltage generating circuit 20, both P-type transistors P4 and P5 are turned off, but PN junction diodes (not shown) are formed between the power supply nodes VDD1 and VDD2 and the node ne, respectively, so that the node ne is electrically connected to the power supply nodes VDD1 and VDD2 via the PN junction diodes.

[0081] In the voltage generating circuit 30, both P-type transistors P6 and P7 are turned off, but their respective PN junction diodes (not shown) are formed between the power supply nodes VDD1 and VDD2 and the node nh. Furthermore, when the N-type transistors N4 and N5 are turned on, the voltage of the node nh drops to a voltage obtained by dividing VDD2 by the PN junction diodes and the on-resistance of the N-type transistors N4 and N5. Here, the P-type transistor P1 is turned on by designing the voltage of the node nh so that the potential difference between VDD1 and the node nh (the gate-source voltage of the P-type transistor P1) exceeds the threshold voltage.

[0082] When a high level is input as the data input signal in, nc = VDD2a and nd = VDD2a. As mentioned above, VDD2a = VDD2, so nc = nd = VDD2. This causes P-type transistor P2 to turn off, N-type transistors N1 and N2 to turn on, and a low level (VSS) is output to output node out. At this time, P-type transistor P3 turns on, so node na and power supply node VDD2 become conductive. As a result, node na does not become undefined.

[0083] When a low level is input as the data input signal in, nc=VSS and nd=VSS. This causes the P-type transistor P2 to turn on, the N-type transistors N1 and N2 to turn off, and a high level (VDD1) is output to the output node out. At this time, the N-type transistor N3 does not turn on, but the node nb becomes a voltage that is VDD2 dropped by the threshold voltage of the N-type transistor N1. This prevents the node nb from becoming undefined.

[0084] [Stopped State] Next, the stopped state of the output circuit 2 after the external power supplies VDD0 and VDD2 have returned to their normal states will be described, that is, the operation when the enable signal en is at a low level will be described.

[0085] As described above, in the non-operational state, the level shift circuit 60 outputs nf=VDD2a and ng=VSS regardless of the data input signal in. Therefore, nc=VDD2a=VDD2 and nd=VSS. This turns off the P-type transistor P2 and the N-type transistor N2, and the output node out becomes an undefined state (Hi-Z).

[0086] Here, for example, when the voltage at the output node out becomes out<VDD2, if the potential difference between the voltage at the output node out and VDD2 (the gate-source voltage of the P-type transistor P3) exceeds the threshold voltage, the P-type transistor P3 turns on, and the node na and the power supply node VDD2a become conductive. As a result, the node na does not become unstable.

[0087] - Effects of the Present Embodiment - As described above, in the present embodiment, similar to the first embodiment, in the power supply startup state (the rising transition state of the external power supplies VDD0 and VDD2), no unnecessary current is generated in the output circuit 2. Furthermore, in the normal state, the intermediate node between the P-type transistors P1 and P2 and the intermediate node between the N-type transistors N1 and N2 in the cascaded output stage are fixed to predetermined values ​​without becoming unstable, thereby maintaining the effects of Patent Document 1.

[0088] Furthermore, even when it is assumed that the relationships VDD1 (VDD0)>VDD2 and Vbias>VDD2 are satisfied during power-on, no unnecessary current is generated. Also, the inter-node voltage of the transistor P1 can be reduced.

[0089] Third Embodiment An output circuit 2 according to this embodiment will be described below. The circuit configuration in Fig. 3 is the same as that of the second embodiment, but the configurations of the voltage generation circuit 20 and the voltage generation circuit 30 are different from those of the second embodiment. Here, the differences from the second embodiment will be mainly described.

[0090] FIG. 6 shows an example of the configuration of the voltage generating circuit 20 and the voltage generating circuit 30 according to this embodiment.

[0091] 6, the voltage generating circuit 20 includes an N-type transistor N6 and a P-type transistor P10 in addition to the configuration of FIG. 4. The N-type transistor N6 is provided between nodes nj and enb, and its gate is connected to a power supply node VDD1. The P-type transistor P10 has its source and back gate connected to a power supply node VDD2, its drain connected to node nj, and its gate connected to node en (corresponding to an enable node). Note that the gate of the P-type transistor P4 is connected to node nj instead of the power supply node VDD2. Furthermore, an inverted enable signal enb, which is an inverted version of the enable signal en, is applied to node enb (corresponding to an inverted enable node).

[0092] 4, the voltage generating circuit 30 includes an N-type transistor N7 and a P-type transistor P11. The N-type transistor N7 is provided between the node nk and the node enb, and its gate is connected to the power supply node VDD1. The P-type transistor P11 has its source and back gate connected to the power supply node VDD2, its drain connected to the node nk, and its gate connected to the node en. The gate of the P-type transistor P6 is connected to the node nk instead of the power supply node VDD2.

[0093] - Operation of Output Circuit - The operation of the output circuit 2 according to this embodiment will be described below, focusing on the differences from the second embodiment.

[0094] [Power-on state: when external power supplies (VDD0, VDD2) are turned on] In the power-on state, the enable signal en is not input, i.e., the enable signal en is at a low level. Therefore, in the voltage generating circuit 20, the P-type transistor P10 is turned on and the N-type transistor N6 is turned off. Similarly, in the voltage generating circuit 30, the P-type transistor P11 is turned on and the N-type transistor N7 is turned off. This results in substantially the same configuration as in the second embodiment, and the circuit operates in the same way as in the second embodiment.

[0095] [Normal Operation] Next, a normal operation of the output circuit 2 after the external power supply VDD0 and the power supply VDD2 have returned to their normal states will be described, that is, the operation when the enable signal en is at a high level and the inverted enable signal enb is at a low level will be described.

[0096] In the voltage generating circuit 20, the N-type transistor N6 turns on, nj=VSS, and the P-type transistor P4 turns on. Also, in the voltage generating circuit 30, the N-type transistor N7 turns on, the node nk=VSS, and the P-type transistor P6 turns on. As a result, the nodes ne and nh become conductive with the power supply node VDD1, and the circuit operates in the same manner as in the second embodiment.

[0097] [Stopped State] Next, the stopped state of the output circuit 2 after the external power supplies VDD0 and VDD2 have returned to their normal states will be described, that is, the operation when the enable signal en is at a low level will be described.

[0098] In the voltage generating circuits 20 and 30, the N-type transistors N6 and N7 are turned off and the P-type transistors P10 and P11 are turned on. As a result, nj=nk=VDD2, and the circuit operates in the same manner as in the second embodiment.

[0099] - Effects of this embodiment - As described above, this embodiment provides the same effects as the second embodiment.

[0100] Furthermore, in this embodiment, the P-type transistors P4 and P6 are turned on during normal operation, so that the power supply node VDD1 and the nodes ne and nh are electrically connected with low impedance. This makes the potentials of the nodes ne and nh more stable than in the configuration of embodiment 2, in which electrical connection is established via the PN junction diodes of the P-type transistors P4 and P6. This prevents fluctuations in the on-resistance of the P-type transistor P1, making this configuration suitable for higher-speed operation.

[0101] <Connection Examples of Output Circuits> FIGS. 7 to 9 show connection examples of the output circuit 1 of the first embodiment and the output circuit 2 of the second or third embodiment.

[0102] (Connection Example 1) FIG. 7 shows connection example 1 in which the output circuits 1 and 2 according to the embodiment are used in an LSI 81. In FIG.

[0103] In connection example 1, an LSI 81 includes an output circuit 1, an output circuit 2, and a regulator 83 that steps down an external power supply VDH and outputs the stepped down voltage to a power supply node VDL. That is, there is a relationship of VDH>VDL.

[0104] Here, the external power supply VDH corresponds to the external power supply VDD0 in the first and second embodiments. The power supply node VDL corresponds to the power supply node VDD1 in the second embodiment. The external power supply VDD2 described in the first and second embodiments is not shown. The same applies to FIGS. 8 and 9.

[0105] The output circuit 1 receives a data input signal in1 and outputs an output signal out that transitions between VDH and VSS in response to the data input signal in1 to an output terminal Ta1. The output terminal Ta1 is connected to an input terminal Tb1 of another LSI 82, for example.

[0106] The output circuit 2 receives a data input signal in2 and outputs an output signal out that transitions between VDL and VSS in response to the data input signal in2 to an output terminal Ta2. The output terminal Ta2 is connected to an input terminal Tb2 of another LSI 82, for example.

[0107] With the above configuration, in connection example 1, output circuit 1 outputs a high level signal of VDH with a relatively large amplitude, and output circuit 2 outputs a high level signal of VDL with a relatively small amplitude.

[0108] (Connection Example 2) FIG. 8 shows a connection example 2 in which the output circuits 1 and 2 according to the embodiment are used in an LSI 81. In FIG.

[0109] In connection example 2, an LSI 81 includes an output circuit 1, an output circuit 84, and a regulator 83 that steps down the external power supply VDH and outputs the stepped-down voltage to a power supply node VDL.

[0110] The output circuit 1 receives a data input signal in1 and outputs an output signal out that transitions between VDH and VSS in response to the data input signal in1 to an output terminal Tc1. The output terminal Tc1 is connected to an input terminal Td1 of another LSI 82, for example.

[0111] The output circuit 84 includes two output circuits 2, 2 and a resistor Rm connected between the outputs of the two output circuits 2, 2.

[0112] One output circuit 2 receives a data input signal in2 and outputs an output signal out that transitions between VDL and VSS in response to the data input signal in2 to an output terminal Tc2. The output terminal Tc2 is connected to an input terminal Td2 of another LSI 82, for example.

[0113] The other output circuit 2 receives a data input signal in2 and outputs an output signal out that transitions between VDL and VSS in response to the data input signal in2 to an output terminal Tc3. The output terminal Tc3 is connected to an input terminal Td3 of another LSI 82, for example.

[0114] In this connection example, it is possible to output a small-amplitude signal from the output circuit 84 at a higher speed than in connection example 1, and it can be suitably used for small-amplitude differential output such as LVDS (Low Voltage Differential Signaling).

[0115] (Connection Example 3) Figure 9 shows connection example 3 in which the output circuits 1 and 2 of the embodiment are used in an LSI 81. In order to increase the functionality of an LSI, multiple output circuits may share signal output wiring. This connection example is a configuration that addresses such a case, and the output signal of one output circuit is applied to another output circuit that is not operating, thereby controlling so that unnecessary current does not occur between the output circuits. A specific example will be described below.

[0116] - Power Supply - In connection example 3, the step-down circuit 10 is configured to output different voltages to the power supply node VDD1 depending on whether the output circuit 1 is in normal operation or in a stopped state. When the output circuit 1 is operating normally, that is, when the enable signal en is at a high level, the step-down circuit 10 outputs a voltage stepped down from VDD0 to VDD2 to the power supply node VDD1. That is, the relationship is VDD1 = VDD2. When the output circuit 1 is in a stopped state, that is, when the enable signal en is at a low level, the step-down circuit 10 outputs VDD0 to the power supply node VDD1. That is, the relationship is VDD1 > VDD2.

[0117] -Output Circuit and Peripheral Configuration- In connection example 3, an LSI 81 includes an output circuit 1, an output circuit 2, and a regulator 83 that steps down the external power supply VDH and outputs it to a power supply node VDL.

[0118] The output circuit 1 receives a data input signal in1 and outputs an output signal out that transitions between VDH and VSS in response to the data input signal in1 to an output terminal Te. The output terminal Te is connected to an input terminal Tf of another LSI 82, for example.

[0119] The output circuit 2 receives a data input signal in2 and outputs an output signal out that transitions between VDL and VSS in response to the data input signal in2 to an output terminal Te. The output terminal Te is connected to an input terminal Tf of another LSI 82, for example.

[0120] -Operation of Output Circuit- The operation of the output circuits 1 and 2 according to this connection example will be described below.

[0121] [Power-on state: when external power supply (VDH) is turned on] In the power-on state, the output circuits 1 and 2 operate in the same manner as in the "power-on state" described in the first to third embodiments.

[0122] [Output circuit 1: stopped state, output circuit 2: normal operation] Output circuit 1 operates in the same manner as in the "stopped state" described in embodiment 1, and output circuit 2 operates in the same manner as in the "normal operation" described in embodiment 2 or embodiment 3.

[0123] [Output Circuit 1: Normal Operation, Output Circuit 2: Stopped Operation] When output circuit 1 operates normally and output circuit 2 is stopped, output circuit 2 stops the operation of voltage step-down circuit 10 and supplies a voltage of the same value as VDD0 to power supply node VDD1. That is, the relationship is VDD0=VDD1>VDD2>Vbias.

[0124] For example, in the output circuit 2, in the voltage generating circuit 20, the P-type transistor P4 is turned on, and the node ne and the power supply node VDD1 are electrically connected (see FIG. 4). In addition, in the voltage generating circuit 30, the P-type transistor P6 is turned on and the N-type transistor N5 is turned off, so nh=VDD1 and the P-type transistor P1 is turned off. As described above, the P-type transistor P2 and the N-type transistor N2 are also turned off, so the output node out is in an undefined state (out=Hi-Z). At this time, the P-type transistor P1 is off, so there is no electrical connection between the power supply nodes VDD1 and VDD2a via the P-type transistors P1 and P3.

[0125] For example, when the output circuit 1 outputs out=VDH (high level), out=VDH turns off the P-type transistor P3 and also turns off the N-type transistor N2. As a result, the output node out (connected to the output node out of the output circuit 1) is not electrically connected to the power supply node VDD2a and the ground node VSS. Furthermore, when the N-type transistor N3 is turned on, the node nb is electrically connected to the power supply node VDD2a, and the node nb does not become undefined.

[0126] For example, when the output circuit 1 outputs out=VSS (low level), the P-type transistor P1 is turned off, so there is no continuity between the power supply node VDD1 and the output node out (connected to the output node out of the output circuit 1). Also, when out=VSS, the P-type transistor P3 is turned on, so that the node na and the power supply node VDD2a are connected. As a result, the node na does not become undefined.

[0127] Other Embodiments The technology of the present disclosure is not limited to the configurations described in the above embodiments, and many modifications, such as changes, substitutions, additions, and omissions, are possible by a person of ordinary skill in the art within the technical spirit of the present disclosure. Furthermore, new embodiments can be created by combining the components described in the above embodiments.

[0128] For example, in connection example 3, the output node out of output circuit 1 and the output node out of output circuit 2 are connected inside LSI 81, but for example, the output node out of output circuit 1 and the output node out of output circuit 2 may be connected outside LSI 81, and the same effect can be obtained.

[0129] The present disclosure is highly effective because, when the power supply is turned on, no unnecessary current is generated in the output circuit, and, in the normal state, the voltage at the intermediate node of the cascaded transistors is prevented from becoming unstable and fluctuating inadvertently, while the voltage applied to the transistors can be maintained below their withstand voltage.

[0130] 1 Output circuit 2 Output circuit 20 Voltage generation circuit 30 Voltage generation circuit (second voltage generation circuit) 31 Pull-down circuit N1 N-type transistor (second N-type transistor) N2 N-type transistor (first N-type transistor) N3 N-type transistor (third N-type transistor) N6 N-type transistor (first N-type transistor) P1 P-type transistor (first P-type transistor) P2 P-type transistor (second P-type transistor) P3 P-type transistor (third P-type transistor) P4 P-type transistor (fourth P-type transistor) P5 P-type transistor (fifth P-type transistor) P6 P-type transistor (fourth P-type transistor, sixth P-type transistor) P7 P-type transistor (fifth P-type transistor, seventh P-type transistor) P10 P-type transistor (sixth P-type transistor) VDD1 Power supply node (first power supply node) VDD2 Power supply node (second power supply node) VSS Ground node (third power supply node) en Node (enable node) enb Node (inverted enable node) na Node (first node) nb Node (third node) ne Node (second node) nj Node (third node) nh Node (third node)

Claims

1. An output circuit that receives a data input signal and outputs an output signal that changes in response to the data input signal, comprising: a first P-type transistor having a source connected to a first power supply node, a drain connected to a first node, and a back gate connected to a second node; a second P-type transistor having a source connected to the first node, a drain connected to an output node from which the output signal is output, and a back gate connected to the first node; a third P-type transistor having a source connected to a second power supply node, a drain and a back gate connected to the first node, and a gate connected to the output node; and a voltage generation circuit that outputs the higher of the voltage of the first power supply node and the voltage of the second power supply node to the second node in a rising transition state of the voltage of the first power supply node and / or the second power supply node, and outputs the voltage of the first power supply node to the second node in a normal state.

2. An output circuit according to claim 1, characterized in that the voltage generating circuit comprises: a fourth P-type transistor having a source connected to the first power supply node, a drain and a back gate connected to the second node, and a gate connected to the second power supply node; and a fifth P-type transistor having a source connected to the second power supply node, a drain and a back gate connected to the second node, and a gate connected to the first power supply node.

3. An output circuit according to claim 2, comprising an enable node to which an enable signal is applied for switching between a normal operation state and a non-operational state of said output circuit, and an inverted enable node to which an inverted enable signal obtained by inverting the enable signal is applied, wherein in said voltage generating circuit, the gate of said fourth P-type transistor is connected to said second power supply node via a sixth P-type transistor whose gate is connected to said enable node, and a first N-type transistor is provided between said inverted enable node and the gate of said fourth P-type transistor.

4. An output circuit according to claim 1, further comprising a second voltage generating circuit connected to the gate of said first P-type transistor via a third node, said second voltage generating circuit comprising: a fourth P-type transistor having a source connected to said first power supply node, a drain and a back gate connected to said third node, and a gate connected to said second power supply node; a fifth P-type transistor having a source connected to said second power supply node, a drain and a back gate connected to said third node, and a gate connected to said first power supply node; and a pull-down circuit which pulls down said third node during normal operation of said output circuit.

5. An output circuit according to claim 4, comprising an enable node to which an enable signal is applied for switching said output circuit between a normal operation state and a non-operational state, and an inverted enable node to which an inverted enable signal obtained by inverting the enable signal is applied, and wherein in said voltage generating circuit, the gate of said fourth P-type transistor is connected to said second power supply node via a sixth P-type transistor whose gate is connected to said enable node, and a first N-type transistor whose gate is connected to said first power supply node is provided between said inverted enable node and the fourth node.

6. An output circuit according to claim 1, comprising: a first N-type transistor having a source connected to a third power supply node and a drain connected to a third node; a second N-type transistor having a source connected to the third node and a drain connected to the output node; and a third N-type transistor provided between the second power supply node and the third node, and having a gate connected to the output node.

7. An output circuit that receives a data input signal and outputs an output signal that changes in response to the data input signal, comprising: a first P-type transistor having a source connected to a first power supply node, a drain connected to a first node, and a back-gate connected to a second node; a second P-type transistor having a source connected to the first node, a drain connected to an output node from which the output signal is output, and a back-gate connected to the first node; a third P-type transistor having a source connected to a second power supply node that is lower than the voltage of the first power supply node in a normal state, a drain and back-gate connected to the first node, and a gate connected to the output node; and a voltage generation circuit, wherein the voltage generation circuit comprises: a fourth P-type transistor having a source connected to the first power supply node, a drain and back-gate connected to the second node, and a gate connected to the second power supply node; and a fifth P-type transistor having a source connected to the second power supply node, a drain and back-gate connected to the second node, and a gate connected to the first power supply node.

8. An output circuit according to claim 7, comprising: an enable node to which an enable signal is applied for switching between a normal operation state and a non-operational state of said output circuit; and an inverted enable node to which an inverted enable signal obtained by inverting the enable signal is applied; and in said voltage generating circuit, the gate of said fourth P-type transistor is connected to said second power supply node via a sixth P-type transistor whose gate is connected to said enable node, and a first N-type transistor is provided between said inverted enable node and the gate of said fourth P-type transistor.

9. An output circuit according to claim 7, further comprising a second voltage generating circuit connected to the gate of said first P-type transistor via a third node, said second voltage generating circuit comprising: a sixth P-type transistor having a source connected to said first power supply node, a drain and a back gate connected to said third node, and a gate connected to said second power supply node; a seventh P-type transistor having a source connected to said second power supply node, a drain and a back gate connected to said third node, and a gate connected to said first power supply node; and a pull-down circuit which pulls down said third node during normal operation of said output circuit.

10. An output circuit according to claim 9, comprising: an enable node to which an enable signal is applied for switching said output circuit between a normal operation state and a non-operational state; and an inverted enable node to which an inverted enable signal obtained by inverting the enable signal is applied; and in said voltage generating circuit, the gate of said fourth P-type transistor is connected to said second power supply node via a sixth P-type transistor whose gate is connected to said enable node, and a first N-type transistor whose gate is connected to said first power supply node is provided between said inverted enable node and the fourth node.

11. An output circuit according to claim 7, comprising: a first N-type transistor having a source connected to a third power supply node having a voltage lower than that of the second power supply node and a drain connected to the third node; a second N-type transistor having a source connected to the third node and a drain connected to the output node; and a third N-type transistor provided between the second power supply node and the third node and having a gate connected to the output node.

Images