Array substrate and preparation method therefor

Abstract

The present invention provides an array substrate and a preparation method therefor. The array substrate comprises: a substrate; a plurality of first electrodes, which are arranged in the same layer and arranged in an array on one side of the substrate; an insulating filling layer, which is located between every two adjacent first electrodes among the plurality of first electrodes; and an insulating barrier layer, which is located between the insulating filling layer and the first electrodes to separate the insulating filling layer from the first electrodes.

Description

Array substrate and manufacturing method thereof TECHNICAL FIELD

[0001] The present application belongs to the field of display, and particularly relates to an array substrate and a manufacturing method thereof. BACKGROUND

[0002] OLED (Organic Light-Emitting Diode) display screens are widely concerned due to their self-luminous, low power consumption, thinness, flexibility, bright colors, high contrast, fast response rate and other advantages. SUMMARY

[0003] The present application provides an array substrate and a manufacturing method thereof. The array substrate can prevent the cathode from piercing the first electrode through the charge generation layer, thereby avoiding the leakage effect of the light-emitting device. In addition, the opening of the light-emitting device corresponding to the first electrode can be increased to the limit opening, thereby increasing the luminous brightness and improving the luminous efficiency of the light-emitting device.

[0004] The present application provides an array substrate, comprising: a substrate; a plurality of first electrodes, which are arranged in an array on one side of the substrate; an insulating filling layer between two adjacent first electrodes of the plurality of first electrodes; and an insulating barrier layer between the insulating filling layer and the first electrode to separate the insulating filling layer and the first electrode.

[0005] In some embodiments, the first electrode comprises a first sub-layer, a second sub-layer and a third sub-layer, which are stacked in sequence away from the substrate; the insulating barrier layer covers at least the sidewall of the second sub-layer of the first electrode. The insulating filling layer covers the sidewalls of the first sub-layer and the third sub-layer of the first electrode and covers the insulating barrier layer.

[0006] In some embodiments, the thickness of the insulating barrier layer in the direction perpendicular to the sidewall of the second sub-layer of the first electrode is 100-200 angstroms.

[0007] In some embodiments, the insulating barrier layer comprises fluorocarbon polymer.

[0008] In some embodiments, the distance between two adjacent first electrodes of the plurality of first electrodes is 180-250 nm.

[0009] In some embodiments, the included angle between the sidewall of the first electrode and the substrate is greater than 0° and less than or equal to 90°.

[0010] In some embodiments, a surface of the insulating fill layer facing away from the substrate is coplanar with a surface of the third sub-layer of the first electrode facing away from the substrate.

[0011] In some embodiments, a distance between a surface of the insulating fill layer facing away from the substrate and the substrate is less than a distance between a surface of the third sub-layer of the first electrode facing away from the substrate and the substrate.

[0012] In some embodiments, a recess is formed on a surface of the insulating fill layer facing away from the substrate, an edge of the recess and a distance between the edge and a sidewall of the first electrode adjacent to the recess is greater than 0 and less than 100 nm.

[0013] In some embodiments, the insulating fill layer comprises silicon oxide, silicon nitride, or silicon oxynitride.

[0014] In some embodiments, the first sub-layer and the third sub-layer of the first electrode each comprise titanium, and the second sub-layer comprises aluminum.

[0015] In some embodiments, a thickness of the second sub-layer of the first electrode is greater than a thickness of each of the first sub-layer and the third sub-layer.

[0016] In some embodiments, the array substrate further comprises a pixel defining layer, a light emitting functional layer, and a second electrode. The pixel defining layer is located on a side of the array substrate away from the first electrode and the insulating fill layer, and is configured to define a plurality of first openings and a plurality of second openings, a footprint of the first opening on the substrate overlaps with a footprint of the first electrode on the substrate, and a footprint of the second opening on the substrate overlaps with a footprint of the insulating fill layer on the substrate. The light emitting functional layer is located on a side of the pixel defining layer away from the first electrode and the insulating fill layer. The second electrode is located on a side of the light emitting functional layer away from the pixel defining layer. The light emitting functional layer in the first opening is in contact with the first electrode, and the light emitting functional layer comprises at least one charge generation layer and a plurality of light emitting layers stacked, the charge generation layer is located between adjacent light emitting layers, and at least the charge generation layer in the light emitting functional layer is broken at the second opening.

[0017] In some embodiments, the pixel defining layer includes a first sub-layer, a second sub-layer located on a side of the first sub-layer distal to the first electrode, and a third sub-layer located on a side of the second sub-layer distal to the first sub-layer. Among edges of the second sub-layer, the first sub-layer, and the third sub-layer of the pixel defining layer proximate respective edges of the second opening, an edge of the first sub-layer projects from an edge of the second sub-layer, and an edge of the third sub-layer projects from edges of the first sub-layer and the second sub-layer. Among edges of the second sub-layer, the first sub-layer, and the third sub-layer of the pixel defining layer proximate respective edges of the first opening, the edges are aligned with one another.

[0018] In some embodiments, the first sub-layer, the second sub-layer, and the third sub-layer of the pixel defining layer each include silicon oxide.

[0019] In some embodiments, the first electrode is an anode and the second electrode is a cathode.

[0020] According to a second aspect of the present disclosure, a method for manufacturing an array substrate is provided, including: providing a substrate; forming a plurality of first electrodes on one side of the substrate in an array and in a same layer; forming an insulating filling layer between two adjacent first electrodes of the plurality of first electrodes; and forming an insulating blocking layer between the insulating filling layer and the first electrodes to space the insulating filling layer and the first electrodes apart.

[0021] In some embodiments, forming the insulating blocking layer includes: after forming a pattern of the first electrodes by dry etching, reducing a flow rate of oxygen introduced into a dry etching process chamber to below 50 sccm, while introducing a trifluoromethane gas into the process chamber, and adjusting a ratio of the flow rates of the trifluoromethane gas and a carbon tetrafluoride gas in the process chamber to 100% to 500%, and continuing dry etching to form the insulating blocking layer on sidewalls of the first electrodes.

[0022] In some embodiments, forming the insulating blocking layer includes: after forming a pattern of the first electrodes by dry etching, reducing a flow rate of oxygen introduced into a dry etching process chamber to below 50 sccm, while introducing a sulfur hexafluoride gas into the process chamber, and adjusting a ratio of the flow rates of the sulfur hexafluoride gas and a carbon tetrafluoride gas in the process chamber to 100% to 200%, and continuing dry etching to form the insulating blocking layer on sidewalls of the first electrodes.

[0023] The array substrate provided by the present application can at least block the direct contact between the charge generation layer and the second area of the sidewall of the first electrode, thereby preventing the indirect contact between the cathode and the first electrode through the charge generation layer caused by the cathode puncture, and further avoiding the leakage effect of the light emitting device. On the other hand, the silicon oxide layer with a certain thickness as the lateral protection layer does not need to be reserved in the interval area between the adjacent first electrodes, so that the width of the interval area between the adjacent first electrodes can be reduced to the process limit width, and further the opening of the light emitting device corresponding to the first electrode can be increased to the limit opening, so that the luminous brightness of the light emitting device can be increased and the luminous efficiency can be improved. BRIEF DESCRIPTION OF DRAWINGS

[0024] Fig. 1a is a schematic diagram of filling the anode interval area in the preparation process of the Micro-OLED array substrate in the related art;

[0025] Fig. 1b is a schematic diagram of over-etching the silicon oxide layer of the anode interval area in the related art;

[0026] Fig. 1c is an electron microscope diagram of over-etching the silicon oxide layer of the anode interval area in the related art;

[0027] Fig. 1d is a schematic diagram of the structure of the Micro-OLED array substrate after the preparation of the pixel definition layer in the related art;

[0028] Fig. 1e is a schematic diagram of the structure of the Micro-OLED array substrate with cathode puncture leakage in the related art;

[0029] Fig. 1f is a schematic diagram of the width of the anode interval area and the lateral protection layer in the related art;

[0030] Fig. 2a is a schematic diagram of the partial structure of an array substrate in an embodiment of the present application;

[0031] Fig. 2b is a schematic diagram of the partial structure of another array substrate in an embodiment of the present application;

[0032] Fig. 2c is a schematic diagram of the partial structure of another array substrate in an embodiment of the present application;

[0033] Fig. 2d is an electron microscope diagram of the edge side of the first electrode covered with the insulating blocking layer in the array substrate in an embodiment of the present application;

[0034] Fig. 3 is a schematic diagram of the partial structure of an array substrate in an embodiment of the present application. DETAILED DESCRIPTION

[0035] In order for those skilled in the art to better understand the technical solutions of the present application, the array substrate and the manufacturing method thereof will be further described in detail below in combination with the drawings and specific embodiments.

[0036] In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the embodiments of the present disclosure will be described clearly and completely below in combination with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by those of ordinary skill in the art without any creative effort fall within the protection scope of the present disclosure.

[0037] Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure shall have the meanings commonly understood by those skilled in the art to which the present disclosure belongs. The terms "first", "second", and similar terms used in the present disclosure do not denote any order, quantity, or importance, but are used to distinguish different components. Similarly, the terms "include" or "contain" and similar terms mean that the elements or objects before the terms encompass the elements or objects listed after the terms and their equivalents, and do not exclude other elements or objects. The terms "connect" or "connected" and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms "upper", "lower", "left", "right", and the like are used only to represent relative positional relationships, and when the absolute positions of the described objects are changed, the relative positional relationships can also be changed accordingly.

[0038] Exemplary embodiments are described herein with reference to cross-sectional and / or plan view illustrations that are schematic illustrations of idealized embodiments. In the drawings, the thickness of layers and regions are exaggerated for clarity. Accordingly, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, the exemplary embodiments should not be construed as limited to the particular shapes of regions as illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. The regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to limit the scope of the exemplary embodiments.

[0039] The embodiments of the present disclosure are not limited to the embodiments shown in the drawings, but include modifications of configurations formed based on manufacturing processes. Therefore, the regions exemplified in the drawings have a schematic property, and the shapes of the regions shown in the drawings exemplify the specific shapes of the regions, but are not intended to be limiting.

[0040] In the related art, as shown in FIG. 1a, the preparation process of the Micro-OLED array substrate is as follows: after forming the anode 8 pattern, the substrate 1 is filled with a silicon oxide (SiOx) layer 9, and then the LHC (Lateral Height Coverage, dry etching lateral leveling) process is used to level the side surface of the anode pattern area 10 and the anode spacing area 11 away from the substrate 1. In the theoretical case, the difference between the side surface of the anode pattern area 10 and the anode spacing area 11 away from the substrate 1 is 0.

[0041] At present, the LHC process first removes the photoresist on the side surface of the silicon oxide layer 9 away from the substrate 1, and then removes the silicon oxide layer on the side surface of the anode pattern area 10 and the anode spacing area 11 away from the substrate 1, so that the side surface of the anode pattern area 10 and the anode spacing area 11 away from the substrate 1 is flush. In this step, the EPD (End Point Detection, detecting the change of the etching film layer to stop etching) etching process is used. Due to the narrow window of the EPD etching process, one or two seconds of time can cause the silicon oxide layer 9 located in the anode spacing area 11 to be over-etched, thereby increasing the water level of the anode spacing area 11, as shown in FIG. 1b.

[0042] At present, the height difference a between the side surface of the anode pattern area 10 and the side surface of the anode spacing area 11 away from the substrate 1 after the LHC process is about 900 angstroms in the worst case, as shown in Fig. 1c. After the LHC process, the process continues on the structure formed to complete the preparation of the pixel definition layer 5 and the first opening 501 and the second opening 502 therein, as shown in Fig. 1d. Then, the light-emitting functional layer 6 of the Micro-OLED device is evaporated, which includes a plurality of stacked organic light-emitting layers 62 and a charge generation layer 61 between adjacent organic light-emitting layers 62, and the charge generation layer 61 can further excite the plurality of stacked organic light-emitting layers 62 to emit light. The charge generation layer 61 can be blocked by the inscribed structure of the sidewall of the second opening 502, thereby blocking the lateral leakage current between adjacent Micro-OLED devices. After the evaporation of the light-emitting functional layer 6, the charge generation layer 61 will be in direct contact with the anode 8 due to the excessive water level of the anode spacing area 11, and the edge side of the light-emitting functional layer 6 will be in direct contact with the anode 8, and the light-emitting functional layer 6 will be severely deformed due to the excessive water level of the anode spacing area 11. The light-emitting functional layer 6 is in contact with the anode 8 at the first opening 501, and then a cathode 12 is formed on the side of the light-emitting functional layer 6 away from the anode 8 to form a sandwich structure of the Micro-OLED device at the first opening 501. When the cathode 12 is continuously deposited on the side of the light-emitting functional layer 6 away from the anode 8, the cathode 12 will be severely deformed under the influence of the severe deformation of the light-emitting functional layer 6, resulting in the direct contact between the cathode 12 and the charge generation layer 61, thereby causing the indirect contact between the cathode 12 and the anode 8, forming cathode puncture, and aggravating the leakage effect, as shown in Fig. 1e.

[0043] In addition, based on the Micro-OLED array substrate structure prepared according to the above preparation process and the characteristics of the silicon oxide material used to fill the anode spacing area 11, a certain thickness b (≥ 150 nm) of silicon oxide needs to be reserved as a lateral protection layer in the anode spacing area 11 between adjacent anode pattern areas 10 along the arrangement direction of the anode pattern area 10 and the anode spacing area 11 to prevent the direct contact between the charge generation layer 61 and the edge side of the anode 8, thereby preventing the contact between the cathode 12 and the anode 8, and further avoiding the risk of leakage. Therefore, at present, the width c of the anode spacing area 11 (i.e. the distance between two adjacent anodes) can only be 500 nm, as shown in Fig. 1f, and the width c of the anode spacing area 11 cannot reach the process limit, so that the first opening 501 in the pixel definition layer 5 cannot reach the limit opening, thereby causing the decrease of the light-emitting brightness and the decrease of the light-emitting efficiency of the Micro-OLED device.

[0044] To solve the above problems, the embodiment of the present application provides an array substrate, as shown in FIG. 2a, FIG. 2b, FIG. 2c and FIG. 2d, comprising a substrate 1, a plurality of first electrodes 2 arranged on one side of the substrate 1 and in the same layer, the plurality of first electrodes 2 are arranged in an array, further comprising an insulating barrier layer 3 arranged on the edge side of the first electrode 2, the edge side of the first electrode 2 comprises a first area 201, a second area 202 and a third area 203, the first area 201, the second area 202 and the third area 203 are sequentially distributed away from the substrate 1, and the insulating barrier layer 3 covers at least the second area 202 of the edge side of the first electrode 2.

[0045] The array substrate can be applied to a Micro-OLED display panel, a Mini-OLED display panel or an OLED display panel. The first electrode 2 is an anode of a light emitting device in the Micro-OLED display panel, the Mini-OLED display panel or the OLED display panel. As shown in FIG. 1e, in the related art, the charge generation layer in the light emitting device directly contacts the edge side of the anode, especially more easily directly contacts the second area 202 of the edge side of the anode, because the water level of the spacing area between the anodes is too large. Therefore, in order to block the direct contact between the charge generation layer and the edge side of the anode, at least the direct contact between the charge generation layer and the second area 202 of the edge side of the anode needs to be blocked.

[0046] In the embodiment, by making the insulating barrier layer 3 cover at least the second area 202 of the edge side of the first electrode 2, on the one hand, the direct contact between the charge generation layer and the second area 202 of the edge side of the first electrode 2 can be at least blocked, thereby preventing the cathode from piercing the charge generation layer to indirectly contact the first electrode 2, and further avoiding the leakage effect of the light emitting device; on the other hand, a certain thickness of silicon oxide as a lateral protection layer does not need to be reserved in the spacing area between the adjacent first electrodes 2, so that the width of the spacing area between the adjacent first electrodes 2 can be reduced to the process limit width, and further the opening of the light emitting device corresponding to the first electrode 2 can be increased to the limit opening, so that the luminous brightness of the light emitting device can be finally increased and the luminous efficiency thereof can be improved.

[0047] In some embodiments, as shown in FIG. 2a, FIG. 2b and FIG. 2c, the first electrode 2 comprises a first sub-layer 21, a second sub-layer 22 and a third sub-layer 23, the first sub-layer 21, the second sub-layer 22 and the third sub-layer 23 are sequentially stacked away from the substrate 1, the thickness of the second sub-layer 22 is greater than the thickness of the first sub-layer 21, and the thickness of the second sub-layer 22 is greater than the thickness of the third sub-layer 23, the edge side (i.e., the side wall) of the first sub-layer 21 is the first area 201, the edge side of the second sub-layer 22 is the second area 202, and the edge side of the third sub-layer 23 is the third area 203.

[0048] In some embodiments, the material of the first sub-layer 21 and the third sub-layer 23 is titanium, and the material of the second sub-layer 22 is aluminum.

[0049] In some embodiments, the included angle θ between the edge side of the first electrode 2 and the substrate 1 is greater than 0° and less than or equal to 90°.

[0050] In some embodiments, the included angle between the first region 201, the second region 202 and the third region 203 of the edge side of the first electrode 2 and the substrate 1 is the same, i.e., θ is greater than 0° and less than or equal to 90°.

[0051] In one embodiment, the insulating barrier layer 3 covers or directly contacts the sidewall of the second sub-layer 21 of the first electrode 2, but does not cover or directly contact the sidewall of the first sub-layer 21 and the third sub-layer 23 of the first electrode 2.

[0052] In some embodiments, the thickness h of the insulating barrier layer 3 covering the sidewall of the second sub-layer 22 of the first electrode 2 in the direction perpendicular to the edge side of the first electrode 2 ranges from 100 to 200 angstroms. The insulating barrier layer 3 with such thickness can well block the direct contact between the charge generation layer and the edge side of the first electrode 2, thereby preventing the cathode from piercing the cathode and the first electrode 2 through the indirect contact between the charge generation layer, and further avoiding the leakage effect of the light emitting device.

[0053] In some embodiments, the material of the insulating barrier layer 3 includes fluorocarbon polymer. The insulating barrier layer 3 with such material can block the direct contact between the charge generation layer and the edge side of the first electrode 2, so that the lateral protection layer between the charge generation layer and the edge side of the first electrode 2 is no longer needed, and further the width of the spacing region between the adjacent first electrodes 2 can be reduced to the process limit width, and the opening of the light emitting device corresponding to the first electrode 2 can be increased to the limit opening, so that the luminous brightness of the light emitting device can be increased and the light emitting efficiency can be improved.

[0054] In some embodiments, the spacing s between the adjacent two first electrodes 2 ranges from 180 to 250 nm. By providing the insulating barrier layer 3 on the edge side of the first electrode 2, the direct contact between the charge generation layer and the edge side of the first electrode 2 can be blocked, and compared with the current width of the anode spacing region which can only be 500 nm, the width of the spacing region between the adjacent first electrodes 2 in the present embodiment can be reduced to the process limit width, and further the opening of the light emitting device corresponding to the first electrode 2 can be increased to the limit opening.

[0055] In some embodiments, as shown in FIG. 2a, the array substrate further comprises an insulating filling layer 4 between the adjacent first electrodes 2, the insulating filling layer 4 covering or directly contacting the sidewalls of the first sub-layer 21 and the third sub-layer 23 of the first electrode 2. The insulating filling layer 4 covers or directly contacts the insulating barrier layer 3, which separates the insulating filling layer 4 from the second sub-layer 22 of the first electrode 2.

[0056] The side surface of the insulating filling layer 4 facing away from the substrate 1 is flush with or in the same plane as the side surface of the first electrode 2 facing away from the substrate 1. In this way, there is no gap between the side surface of the first electrode 2 facing away from the substrate 1 and the space between the adjacent first electrodes 2, thereby reducing the severe deformation of the light-emitting functional layer and the cathode formed on the side of the first electrode 2 facing away from the substrate 1 at the space between the adjacent first electrodes 2, and further avoiding the cathode puncture leakage effect caused by the direct contact between the cathode and the charge generation layer in the light-emitting functional layer.

[0057] In some embodiments, as shown in FIG. 2b, the array substrate further comprises an insulating filling layer 4 between the adjacent first electrodes 2, the distance S1 between the side surface of the insulating filling layer 4 facing away from the substrate 1 and the upper surface M of the substrate 1 is less than the distance S2 between the side surface of the third sub-layer 23 of the first electrode 2 facing away from the substrate 1 and the upper surface M of the substrate 1. That is, there is a gap between the surface of the insulating filling layer 4 facing away from the substrate 1 and the surface of the first electrode 2 facing away from the substrate 1. Since the insulating barrier layer 3 is provided on the edge side of the first electrode 2, the charge generation layer will not be in direct contact with the edge side of the first electrode 2 in the area of the edge side of the first electrode 2 not covered by the insulating filling layer 4, thereby preventing the indirect contact between the cathode and the first electrode 2 through the charge generation layer caused by the cathode puncture, and further avoiding the leakage effect of the light-emitting device.

[0058] In some embodiments, as shown in FIG. 2c, the array substrate further comprises an insulating filling layer 4 between the adjacent first electrodes 2, a groove 40 is formed on the side of the insulating filling layer 4 facing away from the substrate 1, and the distance m between the edge of the groove 40 and the edge side of the first electrode 2 adjacent to the edge is greater than 0 and less than 100 nm.

[0059] The part of the insulating filling layer 4 between the edge of the groove 40 of the insulating filling layer 4 and the edge side of the first electrode 2 closest to the edge of the groove 40 (i.e. the insulating filling layer 4 with a length of m) can serve as a lateral protection layer in the spacing area between the adjacent first electrodes 2. On the basis of covering the insulating barrier layer 3 on the edge side of the first electrode 2, the lateral protection layer can further prevent direct contact between the charge generation layer and the edge side of the first electrode 2; and compared with the lateral protection layer with a thickness of ≥ 150 nm at present, the thickness of the lateral protection layer in the embodiment is obviously reduced, i.e. less than 100 nm, so that the width of the spacing area between the adjacent first electrodes 2 can be reduced to the process limit width, and then the opening of the light emitting device corresponding to the first electrode 2 can be increased to the limit opening, and finally the light emitting brightness of the light emitting device can be increased and the light emitting efficiency thereof can be improved.

[0060] In some embodiments, the insulating filling layer 4 can adopt a silicon oxide, silicon nitride or silicon oxynitride material.

[0061] Based on the above structure of the array substrate, the embodiment of the present application further provides a preparation method of the array substrate, comprising: providing a substrate; preparing a plurality of first electrodes on one side of the substrate; and further comprising preparing an insulating barrier layer on the edge side of the first electrode, the edge side of the first electrode comprising a first area, a second area and a third area, the first area, the second area and the third area being distributed away from the substrate in sequence, and the insulating barrier layer covering at least the second area of the edge side of the first electrode.

[0062] In some embodiments, the preparation of the insulating barrier layer comprises: after forming the pattern of the first electrode by dry etching, reducing the flow rate of oxygen introduced into the dry etching process chamber to below 50 sccm, simultaneously introducing trifluoromethane (CHF3) gas into the process chamber, and adjusting the flow rate ratio of the trifluoromethane gas (CHF3) and the carbon tetrafluoride (CF4) gas in the process chamber to 100% to 500%, and continuing dry etching to form the insulating barrier layer on the edge side of the first electrode.

[0063] In some embodiments, the preparation of the insulating barrier layer comprises: after forming the pattern of the first electrode by dry etching, reducing the flow rate of oxygen introduced into the dry etching process chamber to below 50 sccm, simultaneously introducing sulfur hexafluoride (SF6) gas into the process chamber, and adjusting the flow rate ratio of the sulfur hexafluoride gas and the carbon tetrafluoride gas in the process chamber to 100% to 200%, and continuing dry etching to form the insulating barrier layer on the edge side of the first electrode.

[0064] In some embodiments, the dry etching to form the pattern of the first electrode comprises: firstly, sequentially depositing a metal film layer (e.g., titanium, aluminum, titanium stack) and an insulating protective layer (e.g., silicon nitride protective layer) of the first electrode on the substrate; then, performing photoresist coating, exposure and development to remove the photoresist corresponding to the area outside the pattern of the first electrode; and then, performing dry etching on the substrate after the foregoing steps to sequentially remove the residual photoresist corresponding to the area outside the pattern of the first electrode, remove the insulating protective layer in the area outside the pattern of the first electrode, and remove the metal film layer in the area outside the pattern of the first electrode; thereby forming the pattern of the first electrode. The step of preparing the insulating barrier layer is performed in the post-etching treatment after the dry etching to form the pattern of the first electrode.

[0065] In some embodiments, the method for preparing the array substrate further comprises preparing an insulating filling layer after the preparation of the insulating barrier layer is completed. The preparation of the insulating filling layer comprises: using an insulating material (e.g., silicon oxide) to perform full-area filling on the substrate after the formation of the pattern of the first electrode, and then performing LHC (Lateral Height Coverage) process to flatten the side surface of the interval area between the pattern of the first electrode and the first electrode away from the substrate, thereby forming the insulating filling layer. When performing the LHC process, step-by-step etching can be performed, and an EPD (End Point Detection) etching process can be used to capture signals, so as to reduce the water level of the interval area between the first electrodes as much as possible, and obtain an array substrate structure in which the side surface of the interval area between the first electrodes away from the substrate is flush, thereby reducing the serious deformation of the light-emitting functional layer and the cathode formed on the side of the first electrode 2 away from the substrate 1 at the interval area between adjacent first electrodes 2, and further reducing or avoiding the cathode puncture leakage effect caused by the direct contact between the cathode and the charge generation layer in the light-emitting functional layer.

[0066] The array substrate provided in the embodiments can at least cover the second area of the edge side surface of the first electrode by the insulating barrier layer, which can at least block the direct contact between the charge generation layer and the second area of the edge side surface of the first electrode, thereby preventing the indirect contact between the cathode and the first electrode through the charge generation layer caused by the cathode puncture, and further avoiding the leakage effect of the light-emitting device. On the other hand, a certain thickness of silicon oxide as a lateral protective layer does not need to be reserved in the interval area between adjacent first electrodes, so that the width of the interval area between adjacent first electrodes can be reduced to the process limit width, and the opening of the light-emitting device corresponding to the first electrode can be increased to the limit opening, thereby increasing the luminous brightness and improving the luminous efficiency of the light-emitting device.

[0067] In some embodiments, as shown in FIG. 3, the array substrate further comprises a pixel defining layer 5, a light emitting functional layer 6 and a second electrode 7, the pixel defining layer 5 is located on the side of the array substrate away from the substrate 1, the pixel defining layer 5 is provided with a plurality of first openings 501 and a plurality of second openings 502, the first openings 501 are located in the area of the first electrode 2 on the substrate 1, and the second openings 502 are located in the area of the insulating filling layer 4 on the substrate 1; the light emitting functional layer 6 and the second electrode 7 are sequentially stacked on the side of the pixel defining layer 5 away from the array substrate, the light emitting functional layer 6 in the first openings 501 is in contact with the first electrode 2, the light emitting functional layer 6 comprises at least one charge generation layer 61 and a plurality of light emitting layers 62 which are stacked, the charge generation layer 61 is located between adjacent light emitting layers 62, and the charge generation layer 61 in the light emitting functional layer 6 is at least disconnected at the second openings 502.

[0068] The first electrode 2, the light emitting functional layer 6 and the second electrode 7 are sequentially stacked to form a light emitting device, such as a Micro-OLED device, a Mini-OLED device or an OLED device. The charge generation layer 61 can further excite the plurality of stacked light emitting layers 62 to emit light. The charge generation layer 61 in the light emitting functional layer 6 is at least disconnected at the second openings 502, thereby blocking the lateral leakage current between adjacent light emitting devices.

[0069] In some embodiments, the pixel defining layer 5 comprises a first sub-layer 51, a second sub-layer 52 and a third sub-layer 53, the first sub-layer 51, the second sub-layer 52 and the third sub-layer 53 are sequentially stacked away from the substrate, and at the edge of the second openings 502, the edges of the second sub-layer 52, the first sub-layer 51 and the third sub-layer 53 are sequentially distributed on the substrate 1 in a direction away from the first electrode 2 on the substrate 1. In this way, an inner groove structure G is formed on the edge end surface of the second openings 502 of the pixel defining layer 5, the inner groove structure G can at least block the at least charge generation layer 61 in the light emitting functional layer 6, thereby blocking the lateral leakage current between adjacent light emitting devices.

[0070] As shown in FIG. 3, the inner groove structure G is formed on the edge end surface of the second opening 502. The edges of the first sub-layer 51, the second sub-layer 52 and the third sub-layer 53 of the pixel defining layer 5 close to the first opening 501 are aligned with each other. Among the edges of the first sub-layer 51, the second sub-layer 52 and the third sub-layer 53 of the pixel defining layer 5 close to the second opening 502, the edge of the first sub-layer 51 protrudes from the edge of the second sub-layer 52, and the edge of the third sub-layer 53 protrudes from the edge of the first sub-layer 51. Both the two layers of light emitting functional layers 62 and the charge generation layer 61 between the two layers of light emitting functional layers 62 fall into the second opening 502. Not only the charge generation layer 61 is interrupted at the inner groove structure G, but also the two layers of light emitting functional layers 62 are interrupted at the inner groove structure G, so as to form the interruption surface T, as shown in FIG. 3.

[0071] In some embodiments, the first sub-layer 51 adopts a silicon oxide material, the second sub-layer 52 adopts a silicon nitride material, and the third sub-layer 53 adopts a silicon oxide material.

[0072] In some embodiments, when the pixel defining layer 5 is prepared, a pattern of the first opening 501 is etched first; then a region of the pixel defining layer 5 corresponding to a non-first opening region is etched to form an intermediate opening; finally, the etching selection ratio is adjusted to etch the intermediate opening to form the second opening 502 with the edge end surface of the inner groove structure.

[0073] The array substrate provided in the embodiment can not only avoid the leakage effect of the light emitting device, but also increase the opening of the light emitting device, thereby increasing the light emitting brightness and the light emitting efficiency.

[0074] The array substrate can be used in an OLED panel, a Micro OLED panel, a Mini OLED panel, an OLED television, electronic paper, a mobile phone, a tablet computer, a notebook computer, a display, a notebook computer, a digital photo frame, a navigator, or any product or component with a display function.

[0075] It can be understood that the above embodiments are only exemplary embodiments for illustrating the principles of the present application, and the present application is not limited thereto. Various modifications and improvements can be made by those skilled in the art without departing from the spirit and essence of the present application, and these modifications and improvements are also considered as the protection scope of the present application.

Claims

1. An array substrate, comprising: a substrate; a plurality of first electrodes disposed in a same layer and arranged in an array on one side of the substrate; an insulating filling layer between two adjacent first electrodes of the plurality of first electrodes; and an insulating barrier layer between the insulating filling layer and the first electrodes to space the insulating filling layer and the first electrodes apart. 2.The display substrate of claim 1, wherein the first electrode comprises a first sub-layer, a second sub-layer, and a third sub-layer, the first sub-layer, the second sub-layer, and the third sub-layer are stacked in sequence away from the substrate, the insulating barrier layer covers at least a sidewall of the second sub-layer of the first electrode, the insulating filling layer covers sidewalls of the first sub-layer and the third sub-layer of the first electrode and covers the insulating barrier layer. 3.The array substrate of claim 2, wherein a thickness of the insulating barrier layer in a direction perpendicular to the sidewall of the second sub-layer of the first electrode is 100-200 angstroms. 4.The array substrate of claim 1, wherein the insulating barrier layer comprises a fluorocarbon polymer. 5.The array substrate of claim 1, wherein a spacing between two adjacent first electrodes of the plurality of first electrodes is 180-250 nm. 6.The array substrate of claim 1, wherein an included angle between a sidewall of the first electrode and the substrate is greater than 0° and less than or equal to 90°. 7.The array substrate of any one of claims 2-6, wherein a surface of the insulating filling layer facing away from the substrate is coplanar with a surface of the third sub-layer of the first electrode facing away from the substrate. 8.The array substrate of any one of claims 2-6, wherein a distance between a surface of the insulating filling layer facing away from the substrate and the substrate is less than a distance between a surface of the third sub-layer of the first electrode facing away from the substrate and the substrate. 9.The array substrate of any one of claims 2-6, wherein a groove is formed on a surface of the insulating filling layer facing away from the substrate, a distance between an edge of the groove and a sidewall of the first electrode adjacent to the groove is greater than 0 and less than 100 nm. 10.The array substrate of claim 1, wherein the insulating filling layer comprises silicon oxide, silicon nitride, or silicon oxynitride. 11.The array substrate of claim 2, wherein the first sub-layer and the third sub-layer of the first electrode each comprise titanium, and the second sub-layer comprises aluminum. 12.The array substrate of claim 2, wherein a thickness of the second sub-layer of the first electrode is greater than a thickness of each of the first sub-layer and the third sub-layer. 13.The array substrate of claim 1, further comprising a pixel defining layer, a light emitting functional layer, and a second electrode. ​ The pixel defining layer is located on the side of the array substrate opposite to the first electrode and the insulating filling layer, and is used to define a plurality of first openings and a plurality of second openings. The orthographic projection of the first opening on the substrate overlaps with the orthographic projection of the first electrode on the substrate, and the orthographic projection of the second opening on the substrate overlaps with the orthographic projection of the insulating filling layer in the array substrate on the substrate. The light-emitting functional layer is located on the side of the pixel defining layer away from the first electrode and the insulating filling layer; The second electrode is located on the side of the light-emitting functional layer away from the pixel defining layer. The light-emitting functional layer in the first opening is in contact with the first electrode. The light-emitting functional layer includes at least one charge-generating layer and multiple light-emitting layers stacked together, wherein the charge-generating layer is located between adjacent light-emitting layers. At least the charge-generating layer in the light-emitting functional layer is disconnected at the second opening.

14. The array substrate according to claim 13, wherein The pixel defining layer includes a first sub-layer, a second sub-layer located on the side of the first sub-layer away from the first electrode, and a third sub-layer located on the side of the second sub-layer away from the first sub-layer. In the pixel-defining layer, at each edge of the second sub-layer, the first sub-layer, and the third sub-layer near the second opening, the edge of the first sub-layer protrudes from the edge of the second sub-layer, and the edge of the third sub-layer protrudes from the edges of the first and second sub-layers. The edges of the second sub-layer, the first sub-layer, and the third sub-layer of the pixel defining layer near the first opening are aligned with each other.

15. The array substrate according to claim 14, wherein The first sub-layer, the second sub-layer, and the third sub-layer of the pixel defining layer all comprise silicon oxide.

16. The array substrate according to claim 13, wherein The first electrode is the anode, and the second electrode is the cathode.

17. A method for fabricating an array substrate, comprising: Provide substrate; Multiple first electrodes are formed in an array on one side of the substrate and located in the same layer; An insulating fill layer is formed between two adjacent first electrodes among the plurality of first electrodes. An insulating barrier layer is formed between the insulating fill layer and the first electrode to separate the insulating fill layer from the first electrode.

18. The method of manufacturing an array substrate according to claim 17, wherein, Forming an insulating barrier layer includes: After the pattern of the first electrode is formed by dry etching, the flow rate of oxygen introduced into the dry etching process chamber is reduced to below 50 sccm, while trifluoromethane gas is introduced into the process chamber. The flow rate ratio of trifluoromethane gas to carbon tetrafluoride gas in the process chamber is adjusted to 100% to 500%, and dry etching continues to form the insulating barrier layer on the sidewall of the first electrode.

19. The method of manufacturing an array substrate according to claim 17, wherein, Forming an insulating barrier layer includes: After the pattern of the first electrode is formed by dry etching, the flow rate of oxygen introduced into the dry etching process chamber is reduced to below 50 sccm, while sulfur hexafluoride gas is introduced into the process chamber. The flow rate ratio of sulfur hexafluoride gas to carbon tetrafluoride gas in the process chamber is adjusted to 100% to 200%, and dry etching continues to form the insulating barrier layer on the sidewall of the first electrode.

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