Layered structure, crystal film, semiconductor apparatus, electronic device, and system

Abstract

[Problem] To provide a layered structure which is useful for a semiconductor apparatus and the like and which has excellent crystallinity. [Solution] Used is a layered structure in which a crystal thin film comprising a second crystal is laminated on a crystal substrate comprising a first crystal, either directly or with another layer therebetween, wherein the first crystal and the second crystal both contain germanium dioxide or a mixed crystal thereof as a main component, and the first crystal and the second crystal both have the same crystal structure. Said layered structure is applied to a semiconductor apparatus and the like.

Description

Stacked structure, crystalline film, semiconductor device, electronic device and system

[0001] The present invention relates to a laminated structure useful for semiconductor devices.

[0002] In recent years, rutile-structure germanium dioxide (r-GeO) has been developed as a promising ultra-wide bandgap (UWBG) semiconductor for future power electronics devices. ２ ) is attracting attention. ２ has a band gap of 4.68 eV, can be used to produce n-type and p-type semiconductors, and can be fabricated inexpensively, so it is expected to be a next-generation semiconductor device.

[0003] Non-Patent Document 1, Patent Document 1, Patent Document 2, and Patent Document 3 disclose r-TiO ２ r-GeO on (001) substrate ２ A laminated structure in which crystalline films are stacked has been investigated. However, after the peer review of Non-Patent Document 1, Non-Patent Document 2 was submitted as an erratum (Non-Patent Document 2). It was found that the crystal grains (abnormal grains) described in Non-Patent Document 1, Patent Document 1, Patent Document 2, and Patent Document 3 were rutile-type germanium dioxide crystals, and the remaining portions were amorphous phases. That is, only amorphous phases were formed in the majority of the structures, and even if a crystalline phase was formed, only crystal grains were formed in a portion of the structures. Furthermore, the cross-sectional TEM image of Non-Patent Document 2 reveals that a large number of dislocation densities existed in the portions where a crystalline phase was partially formed. Therefore, a method for producing a crystalline film with low dislocation density and excellent crystallinity has been eagerly awaited.

[0004] H. Takane, K. Kaneko. , “Establishment of a growth route of crystallized rutile GeO2 thin film (≧ 1 mm / h) and its structural Applied Physics Letters Vol. 119, pp. 062104(1-6) (2021). H. Takane, K. Kaneko. , Erratum: “Establishment of a growth route of crystallized rutile GeO2 thin film (≧1 μm / h) and its structural Applied Physics Letters Vol. 120, 099903(1-3) (2022).

[0005] International Publication No. 2023 / 008452 International Publication No. 2023 / 008453 International Publication No. 2023 / 008454

[0006] An object of the present invention is to provide a laminated structure having excellent crystallinity that is useful for semiconductor devices and the like.

[0007] As a result of intensive research to achieve the above object, the inventors have newly developed a mist CVD apparatus using a guide partition, and have used the mist CVD apparatus using the guide partition to successfully create a laminated structure in which a crystal thin film made of a second crystal is laminated directly or via another layer on a crystal substrate made of a first crystal, wherein both the first crystal and the second crystal contain oxide crystals whose main component is germanium.The inventors have found that the resulting crystal can be easily produced at low cost, has a low dislocation density, and has excellent crystallinity, making it useful for semiconductor devices, etc., and have discovered that such a laminated structure can solve all of the above-mentioned conventional problems at once.Furthermore, after obtaining the above findings, the inventors have conducted further research and have completed the present invention.

[0008] That is, the present invention relates to the following inventions. [1] A laminated structure in which a crystal thin film made of a second crystal is laminated directly or via another layer on a crystal substrate made of a first crystal, the laminated structure being characterized in that both the first crystal and the second crystal contain germanium dioxide or a mixed crystal thereof as a main component. [2] The laminated structure according to [1] above, in which both the first crystal and the second crystal have the same crystal structure. [3] The laminated structure according to [1] above, in which both the first crystal and the second crystal have a rutile structure. [4] The laminated structure according to [1] above, in which both the first crystal and the second crystal are semiconductors. [5] The crystal thin film has a dislocation density of 1×10 １０ cm ―２ The laminate structure according to the following [1]. [6] The laminate structure according to the above [1], wherein the crystal thin film is a single crystal thin film. [7] The laminate structure according to the above [1], wherein the crystal thin film has a thickness of 1 μm or more. [8] The volume of the crystal substrate is 15 mm ３ [9] The laminated structure according to the above [1], wherein the area of ​​the crystal thin film is 5 mm ２

[10] A crystal thin film containing germanium dioxide or a mixed crystal thereof as a main component, wherein the dislocation density is 1×10 １０ cm ―２A crystal thin film characterized by the following.

[11] A semiconductor device including a stacked structure, wherein the stacked structure is the stacked structure described in [1] above.

[12] The semiconductor device according to

[11] above, which is a power device.

[13] The semiconductor device according to

[11] above, which is a Schottky barrier diode (SBD), a junction barrier Schottky diode (JBS), a metal semiconductor field effect transistor (MESFET), a static induction transistor (SIT), a high electron mobility transistor (HEMT), a metal oxide semiconductor field effect transistor (MOSFET), a junction field effect transistor (JFET), an insulated gate bipolar transistor (IGBT), or a light emitting diode (LED).

[14] An electronic device including a semiconductor device, wherein the semiconductor device is the semiconductor device described in

[11] above.

[15] A system including an electronic device, wherein the electronic device is the electronic device described in

[14] above.

[0009] The laminated structure of the present invention is useful for semiconductor devices and the like, and exhibits excellent crystallinity.

[0010] FIG. 1 is an example of a schematic configuration diagram of a film forming apparatus preferably used in the present invention. FIG. 2 is a diagram schematically showing an atomization apparatus preferably used in the present invention. FIG. 3 is a diagram schematically showing a cross-sectional side view of an atomization apparatus preferably used in the present invention. FIG. 4 is a diagram schematically showing a preferred example of a Schottky barrier diode (SBD) of the present invention. FIG. 5 is a diagram schematically showing a preferred example of a high electron mobility transistor (HEMT) of the present invention. FIG. 6 is a diagram schematically showing a preferred example of a metal oxide semiconductor field effect transistor (MOSFET) of the present invention. FIG. 7 is a diagram schematically showing a preferred example of a junction field effect transistor (JFET) of the present invention. FIG. 8 is a diagram schematically showing a preferred example of an insulated gate bipolar transistor (IGBT) of the present invention. FIG. 9 is a diagram schematically showing a preferred example of a light-emitting device (LED) of the present invention. FIG. 10 is a diagram schematically showing a preferred example of a junction barrier Schottky diode (JBS) of the present invention. FIG. 11 is a diagram schematically showing a preferred example of a metal semiconductor field effect transistor (MESFET) of the present invention. FIG. 12 is a diagram schematically showing a preferred example of a static induction transistor (SIT) of the present invention. FIG. 13 is a schematic diagram for explaining a part of the manufacturing process of the SIT of FIG. 12. FIG. 14 is an example of a schematic configuration diagram of a crucible for a bulk crystal growth apparatus preferably used in the present invention. FIG. 15 is an example of a schematic configuration diagram of a bulk crystal growth apparatus preferably used in the present invention. FIG. 16 is a diagram showing measurement results of a bulk crystal by X-ray diffraction measurement in Example 1. FIG. 17 is a micrograph showing an example of a cross-sectional TEM image in Example 1. FIG. 18 is a diagram showing electron diffraction spots of a crystal film and a crystal substrate in a cross-sectional TEM in Example 1. FIG. 19 is a micrograph showing an example of a cross-sectional TEM image in Example 1. FIG. 20 is a micrograph showing an example of a cross-sectional TEM image in Example 2. FIG. 21 is a diagram showing electron diffraction spots of a crystal film and a crystal substrate in a cross-sectional TEM in Example 2. FIG. 22 is a micrograph showing an example of a cross-sectional TEM image in Example 2. FIG. 23 is a diagram showing a cross-sectional TEM image in Comparative Example 1.

[0011] The laminated structure of the present invention is a laminated structure in which a crystal thin film made of a second crystal is laminated on a crystal substrate made of a first crystal directly or via another layer, and is characterized in that both the first crystal and the second crystal contain germanium dioxide or a mixed crystal thereof as a main component. The crystal thin film of the present invention is a crystal thin film containing germanium dioxide or a mixed crystal thereof as a main component, and has a dislocation density of 1×10 １０ cm ―２ The mixed crystal is not particularly limited as long as it is a mixed crystal of germanium dioxide and another metal compound. For example, GeO ２ and SnO ２ , TiO ２ , V.O. ２ , MnO ２ , RuO ２ , CsO ２ , IrO ２ , CuO ２ , PbO ２ , AgO ２ , CrO ２ , SiO ２ , SiC, GaN, or a mixed crystal of two or more of these metal oxides. In this specification, "layer" can be read as "film." A "laminated structure" is a structure including one or more crystalline layers, and may also include a layer other than a crystalline layer (e.g., an amorphous layer). The crystalline layer is preferably a single crystalline layer, but may also be a polycrystalline layer.

[0012] In the present invention, the term "main component" refers to a composition ratio (atomic ratio) of the germanium dioxide or its mixed crystal in the crystal of 50 at% or more. In an embodiment of the present invention, the content of the germanium dioxide or its mixed crystal in the crystal is preferably 70 at% or more, more preferably 90 at% or more, in terms of composition ratio in the crystal. This preferred range results in a better interface, improved electrical properties, and improved semiconductor properties. The crystal may also contain a metal oxide other than germanium dioxide. Examples of the other metal oxide include one or more metals selected from Group 14 metals of the periodic table other than germanium (e.g., tin or silicon) or Group 4 metals of the periodic table (e.g., titanium, zirconia, or hafnium). The atomic ratio of the germanium dioxide or its mixed crystal in the crystal is preferably 0.5 or more. By setting the atomic ratio of germanium dioxide or its mixed crystal within such a preferred range, a crystalline film having better semiconductor properties can be realized. In addition, in the present invention, the crystal is not particularly limited in terms of crystal structure, and may be a rutile crystal structure which is a tetragonal system, an α-quartz structure which is a trigonal system, a β-quartz structure which is a hexagonal system, or an orthorhombic CaCl ２ It may have a type crystal structure, such as α-PbO ２ The rutile crystal structure is preferably a tetragonal crystal structure, and the rutile crystal structure is preferably a tetragonal crystal structure.

[0013] In the present invention, it is preferable that both the first crystal and the second crystal have the same crystal structure, and it is preferable that both the first crystal and the second crystal have a rutile structure. It is also preferable that both the first crystal and the second crystal are semiconductors. According to these preferable ranges, the crystallinity is better and the semiconductor characteristics can be more excellent. The dislocation density of the crystal thin film is 1×10 １０ cm ―２It is preferable that the dislocation density is not more than 1 / 2 mm. Within such a preferable range, better crystallinity can be obtained, and the breakdown voltage and electrical properties can also be improved. Furthermore, the "dislocation density" in the present invention refers to a value determined from the number of dislocations per unit area observed from a planar or cross-sectional TEM image.

[0014] In the present invention, the area of ​​the crystal thin film is 5 mm ２ It is preferable that the volume of the crystal substrate is 15 mm or more. ３ It is preferable that the crystal is a semiconductor. Within these preferable ranges, the crystal can have a better breakdown voltage and can obtain better electrical properties.

[0015] The above-described preferred crystal thin film or laminated structure can be more easily obtained, for example, by using a film-forming apparatus shown in Figure 14. The thickness of the crystal thin film is not particularly limited as long as it does not impede the object of the present invention, but in the present invention, it is preferably 1 µm or more. By setting the thickness to such a preferred value, when the laminated structure is applied to a semiconductor device, the semiconductor device can be endowed with superior electrical properties such as high voltage resistance.

[0016] The crystal thin film of the present invention is not particularly limited as long as it does not impede the objectives of the present invention, but preferably contains a dopant. The dopant is not particularly limited as long as it does not impede the objectives of the present invention, but preferably contains a Group 15 element or a Group 13 element of the periodic table. Examples of the Group 15 element of the periodic table include nitrogen, phosphorus, arsenic, antimony, and bismuth. Examples of the Group 13 element of the periodic table include boron, aluminum, gallium, and indium. Within these preferred ranges, better electrical properties can be obtained and the film can be more easily manufactured.

[0017] The crystal substrate is not particularly limited as long as it does not impede the object of the present invention, and may be a known substrate, an insulating substrate, a conductive substrate, or a semiconductor substrate. It may also be a single crystal substrate or a polycrystalline substrate. The crystal substrate may also be a substrate having a metal film on its surface. When the crystal substrate is a conductive substrate, a vertical device can be fabricated without removing the substrate. Furthermore, the volume of the crystal substrate is 15 mm ３ The crystal substrate is preferably, for example, n ＋ n-type Si substrate, n-type Si substrate, ＋ The Si substrate may be a n-type Si substrate or a n-type SiC substrate. ２ The conductive substrate may contain a dopant such as ZnO. When forming a film on the Si substrate, a conductive buffer layer can be introduced as an intermediate layer. Examples of the conductive buffer layer include a metal film or a doped semiconductor film. Examples of the metal film include a film containing at least one or two elements of Group 4, Group 11, or Group 10 of the periodic table. Examples of the elements of Group 4 of the periodic table include Ti, Zr, or Hf. Examples of the elements of Group 11 of the periodic table include Cu, Ag, or Au. Examples of the elements of Group 10 of the periodic table include Ni, Pd, or Pt. The crystal structure of the crystal substrate preferably has a rutile crystal structure. Examples of the substrate having a rutile crystal structure include rutile-structured GeO. ２ Substrate, magnesium fluoride substrate or rutile structure TiO ２ The crystal substrate may have an off-axis angle. Within this preferred range, the semiconductor characteristics can be further improved, the crystallinity can be improved, and the substrate can be more easily applied to semiconductor devices and the like.

[0018] In the present invention, a film may be formed directly on the substrate, but a layer different from the crystal layer (for example, an n-type semiconductor layer, n ＋ type semiconductor layer, n－ The semiconductor layer may be formed on the substrate via other layers, such as a silicon-doped semiconductor layer (e.g., a silicon-doped semiconductor layer), an insulating layer (including a semi-insulating layer), or a buffer layer. In particular, a buffer layer can be suitably used to reduce the difference in lattice constant between the crystal substrate and the semiconductor layer. Examples of materials for the buffer layer include SnO. ２ , TiO ２ , V.O. ２ , MnO ２ , RuO ２ , CsO ２ , IrO ２ , GeO ２ , CuO ２ , PbO ２ , AgO ２ , CrO ２ , SiO ２ , SiC, GaN, and mixed crystals thereof.

[0019] The crystal substrate can be more easily grown as a crystal having a rutile structure by using, for example, a crystal growth apparatus as shown in FIG. 15 . While the crystal growth conditions are not particularly limited, it is preferable to add lithium carbonate and molybdenum oxide and produce the crystal under heating at 800°C to 1000°C. Doping can also be performed appropriately using the crystal growth apparatus. The doped crystal substrate can be suitably used as a semiconductor crystal substrate, and n-type or p-type dopants can be used for the doping. Examples of n-type dopants include antimony (Sb), arsenic (As), bismuth (Bi), phosphorus (P), fluorine (F), niobium (Nb), vanadium (V), tantalum (Ta), and tungsten (W). Examples of p-type dopants include aluminum (Al), gallium (Ga), and indium (In). The present invention also encompasses stacked structures obtained in this manner.

[0020] The semiconductor layer can be more easily obtained by depositing a crystalline thin film containing germanium dioxide or its mixed crystal as a main component, for example, using the film deposition apparatus shown in FIG. 1 . Furthermore, doping can also be performed appropriately using the film deposition apparatus. The doped crystalline thin film can be suitably used as a semiconductor film or semiconductor layer, and n-type or p-type dopants can be applied using conventional doping methods for oxide semiconductors. Examples of n-type dopants include antimony (Sb), arsenic (As), bismuth (Bi), phosphorus (P), fluorine (F), niobium (Nb), vanadium (V), tantalum (Ta), and tungsten (W). Examples of p-type dopants include aluminum (Al), gallium (Ga), and indium (In). The present invention also encompasses stacked structures obtained in this manner.

[0021] The laminated structure can be used as is or after known processing such as substrate peeling, using known means, for example, in semiconductor devices. Examples of such semiconductor devices include Schottky barrier diodes (SBDs), junction barrier Schottky diodes (JBSs), metal semiconductor field-effect transistors (MESFETs), static induction transistors (SITs), high electron mobility transistors (HEMTs), metal oxide semiconductor field-effect transistors (MOSFETs), junction field-effect transistors (JFETs), insulated gate bipolar transistors (IGBTs), and light-emitting diodes (LEDs). The laminated structure can also be used in modules incorporating such semiconductor devices, electronic devices incorporating such semiconductor devices, and components thereof. The laminated structure is useful for a variety of applications, particularly power devices. The semiconductor devices can be classified into horizontal devices (horizontal devices) in which an electrode is formed on one side of the semiconductor layer, and vertical devices (vertical devices) in which electrodes are formed on both the front and back sides of the semiconductor layer. In the present invention, the semiconductor device can be used in both horizontal and vertical devices.

[0022] Examples of semiconductor devices suitable for use in the present invention will be described in more detail below with reference to the drawings, but the present invention is not limited to these examples. Preferred examples in which germanium dioxide or a mixed crystal thereof is used as a semiconductor layer containing the germanium dioxide or a mixed crystal thereof as a main component will be shown below.

[0023] FIG. － type semiconductor layer 101a,n ＋ 1 shows a preferred example of a Schottky barrier diode (SBD) including a p-type semiconductor layer 101b, a p-type semiconductor layer 102, a metal layer 103, an insulator layer 104, a Schottky electrode 105a, and an ohmic electrode 105b. The metal layer 103 is made of a metal such as Al and covers the Schottky electrode 105a.

[0024] FIG. 5 shows an n-type semiconductor layer 121a having a wide band gap, an n-type semiconductor layer 121b having a narrow band gap, and ＋ 1 shows a preferred example of a high electron mobility transistor (HEMT) including a p-type semiconductor layer 121c, a p-type semiconductor layer 123, a gate electrode 125a, a source electrode 125b, a drain electrode 125c, and a substrate 129.

[0025] FIG. 6 shows － The first n-type semiconductor layer 131a ＋ type semiconductor layer 131b, second n ＋ p-type semiconductor layer 131c, p-type semiconductor layer 132, ＋ 1 shows a preferred example of a metal oxide semiconductor field effect transistor (MOSFET) including a p-type semiconductor layer 132a, a gate insulating film 134, a gate electrode 135a, a source electrode 135b, and a drain electrode 135c. ＋ The n-type semiconductor layer 132 a may be a p-type semiconductor layer or may be the same as the p-type semiconductor layer 132 .

[0026] FIG. 7 shows － The first n-type semiconductor layer 141a ＋ type semiconductor layer 141b, second n ＋ 1 shows a preferred example of a junction field effect transistor (JFET) comprising a p-type semiconductor layer 141c, a p-type semiconductor layer 142, a gate electrode 145a, a source electrode 145b, and a drain electrode 145c.

[0027] FIG. 8 shows the n-type semiconductor layer 151, － type semiconductor layer 151a,n ＋ 1 shows a preferred example of an insulated gate bipolar transistor (IGBT) including a p-type semiconductor layer 151b, a p-type semiconductor layer 152, a gate insulating film 154, a gate electrode 155a, an emitter electrode 155b, and a collector electrode 155c.

[0028] (LED) Fig. 9 shows an example of a semiconductor device of the present invention that is a light-emitting diode (LED). The semiconductor light-emitting device of Fig. 9 includes an n-type semiconductor layer 161 on a second electrode 165b, and a light-emitting layer 163 is stacked on the n-type semiconductor layer 161. A p-type semiconductor layer 162 is stacked on the light-emitting layer 163. A light-transmitting electrode 167 that transmits light generated by the light-emitting layer 163 is provided on the p-type semiconductor layer 162, and a first electrode 165a is stacked on the light-transmitting electrode 167. The semiconductor light-emitting device of Fig. 9 may be covered with a protective layer except for the electrode portion.

[0029] Examples of materials for the translucent electrode include conductive oxide materials containing indium (In) or titanium (Ti). ２ O ３ , ZnO, SnO ２ , Ga ２ O ３ , TiO ２ , CeO ２ Alternatively, a mixed crystal of two or more of these materials or a doped material thereof may be used. A translucent electrode can be formed by applying these materials by a known method such as sputtering. After the formation of the translucent electrode, thermal annealing may be performed to make the translucent electrode transparent.

[0030] In the semiconductor light-emitting element of FIG. 9, the first electrode 165a is a positive electrode and the second electrode 165b is a negative electrode, and current is passed through these electrodes to the p-type semiconductor layer 162, the light-emitting layer 163, and the n-type semiconductor layer 161, causing the light-emitting layer 163 to emit light.

[0031] Examples of materials for the first electrode 165a and the second electrode 165b include metals such as Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Au, Pt, V, Mn, Ni, Cu, Hf, W, Ir, Zn, In, Pd, Nd, and Ag, or alloys thereof; conductive metal oxide films such as tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), and indium zinc oxide (IZO); organic conductive compounds such as polyaniline, polythiophene, and polypyrrole; and mixtures thereof. The method for forming the electrodes is not particularly limited, and they can be formed on the substrate according to a method appropriately selected from wet methods such as printing, spraying, and coating; physical methods such as vacuum deposition, sputtering, and ion plating; and chemical methods such as CVD and plasma CVD, taking into consideration their suitability for the material.

[0032] 10 shows the main part of a junction barrier Schottky diode (JBS) which is one of the preferred embodiments of the present invention. The JBS in FIG. 10 has an ohmic electrode 1020, n － type semiconductor layers 1010a,n ＋ The semiconductor device of FIG. 10 includes a p-type semiconductor layer 1010b, a Schottky electrode 1030, and an electric field relaxation region 1060. The Schottky electrode 1030 is composed of metal layers 1030a, 1030b, and 1030c. In the semiconductor device of FIG. 10, the outer ends of metal layers 1030a and / or 1030b serving as second electrode layers are located outside the outer end of metal layer 1030c serving as a first electrode layer. In the semiconductor device of FIG. 10, the electric field relaxation region 1060 includes at least two electric field relaxation regions 1060 in a plane including at least a portion of the second electrode layer that is located outside the outer end of the first electrode layer and the outer end of the second electrode. In the semiconductor device of FIG. 10, the electric field relaxation region 1060 is composed of a p-type semiconductor and forms a PN junction with the n-type semiconductor layer 1010a.

[0033] 10 may be formed by any known method without particular limitation, as long as it does not impede the object of the present invention, such as forming a film by vacuum deposition, CVD, sputtering, or various coating techniques, followed by patterning by photolithography, or directly patterning by printing or the like.

[0034] (MESFET) Fig. 11 shows an example of a metal semiconductor field effect transistor (MESFET) according to the present invention. The MESFET of Fig. 8 is － type semiconductor layers 111a,n ＋ The semiconductor layer 111b, the buffer layer 118, the semi-insulating layer 114, the gate electrode 115a, the source electrode 115b, and the drain electrode 115c are provided.

[0035] The materials for the gate electrode, drain electrode, and source electrode may be known electrode materials, and examples of the electrode materials include metals such as Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Au, Pt, V, Mn, Ni, Cu, Hf, W, Ir, Zn, In, Pd, Nd, and Ag, or alloys thereof; conductive metal oxide films such as tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), and indium zinc oxide (IZO); organic conductive compounds such as polyaniline, polythiophene, and polypyrrole; and mixtures thereof. The gate electrode, drain electrode, and source electrode can be formed by known means such as vacuum deposition or sputtering.

[0036] The semi-insulating layer 114 may be made of a semi-insulating material, and examples of the semi-insulating material include those containing semi-insulating dopants such as magnesium (Mg), ruthenium (Ru), iron (Fe), beryllium (Be), cesium (Cs), strontium (Sr), and barium (Ba), as well as those that are not doped.

[0037] In the MESFET of FIG. 11, a good depletion layer is formed under the gate electrode, so that the current flowing from the drain electrode to the source electrode can be efficiently controlled.

[0038] (SIT) Fig. 12 shows an example of the semiconductor device of the present invention being an SIT. The SIT in Fig. 12 is － type semiconductor layers 241a,n ＋ The gate electrode 245a, the source electrode 245b and the drain electrode 245c are provided.

[0039] On the drain electrode 245c, for example, a n ＋ The n-type semiconductor layer 241b is formed. ＋ On the n-type semiconductor layer 241b, for example, a 100 nm to 100 μm thick n-type semiconductor layer － The n-type semiconductor layer 241a is formed. － On the n-type semiconductor layer 241a, ＋ The n-type semiconductor layer 241c is formed. ＋ A source electrode 145b is formed on the gate semiconductor layer 241c.

[0040] In addition, the n － The n-type semiconductor layer 241a contains the ＋ The n － A plurality of trenches are formed to a depth that reaches halfway through the semiconductor layer 241a. － A gate electrode 245a is formed on the type semiconductor layer 241a.

[0041] In the on-state of the SIT shown in FIG. 12, when a voltage is applied between the source electrode 245b and the drain electrode 245c and a positive voltage is applied to the gate electrode 245a with respect to the source electrode 245b, the n － A channel layer is formed in the n-type semiconductor layer 241a, and electrons are － The off state is achieved by setting the voltage of the gate electrode to 0 V, which prevents the formation of a channel layer and turns the n-type semiconductor layer 241a on. － The semiconductor layer is filled with a depletion layer, and the device is turned off.

[0042] 13A and 13B show a part of the manufacturing process of the SIT shown in FIG. 12. For example, using a stacked body as shown in FIG. －type semiconductor layer 241a and n ＋ An etching mask is provided in a predetermined region of the n-type semiconductor layer 241c, and anisotropic etching is performed using the etching mask by, for example, reactive ion etching, to remove the n-type semiconductor layer 241c as shown in FIG. 13(b). ＋ The n-type semiconductor layer 241c surface － A trench groove is formed to a depth that reaches halfway through the n-type semiconductor layer 241a. Next, a gate electrode material such as polysilicon is deposited in the trench groove by a method such as CVD, vacuum deposition, or sputtering. － The n-type semiconductor layer 241a is formed to a thickness equal to or less than that of the n-type semiconductor layer 241b. ＋ A source electrode 245b is formed on the n-type semiconductor layer 241c. ＋ The source electrode and the drain electrode may be formed on the semiconductor layer 241b, respectively, to manufacture an SIT. The electrode materials for the source electrode and the drain electrode may be known electrode materials, such as metals such as Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Au, Pt, V, Mn, Ni, Cu, Hf, W, Ir, Zn, In, Pd, Nd, and Ag, or alloys thereof; conductive metal oxide films such as tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), and indium zinc oxide (IZO); organic conductive compounds such as polyaniline, polythiophene, and polypyrrole; and mixtures thereof.

[0043] Although the above example shows an example in which a p-type semiconductor is not used, the present invention is not limited to this and a p-type semiconductor may be used. Note that the p-type semiconductor may be the same material as the n-type semiconductor and contain a p-type dopant, or may be a different p-type semiconductor.

[0044] The crystal thin film can be obtained by a known film-forming means, such as a film-forming means using a Ge-containing atomization raw material solution in a film-forming apparatus as shown in Fig. 1. The atomization raw material solution and film-forming conditions can be appropriately set depending on the substrate, etc.

[0045] The film formation conditions may be set appropriately as long as they do not impede the objectives of the present invention. In the present invention, the film formation temperature is preferably 450°C or higher and 1300°C or lower. The film formation time is not particularly limited, but may be, for example, 1 minute to 20 hours. The dopant introduction method may be a known introduction method, such as a method for injecting impurity ions or a method for producing a crystalline film containing impurities. The ion implantation may be a known ion implantation method. The crystalline film production method may be a known film formation method. The annealing temperature is not particularly limited, but is preferably, for example, 500°C or higher and 1300°C or lower. The annealing time is not particularly limited, but is preferably, for example, 10 seconds to 10 hours. The annealing atmosphere is not particularly limited, but may be, for example, a non-oxygen atmosphere such as nitrogen, forming gas, or argon, or an oxygen atmosphere. The ion implantation angle in the present invention refers to the inclination between the ion beam and a line perpendicular to the surface of the crystal thin film or the crystal substrate. If the ion implantation angle is decreased, the implantation depth becomes deeper, and conversely, if the ion implantation angle is increased, the implantation depth becomes shallower. The ion implantation angle may be set appropriately as long as it does not impede the object of the present invention.

[0046] Example 1 Figure 14 is a diagram showing an example of a typical embodiment of a reaction vessel disposed in a manufacturing apparatus used to produce a crystal substrate according to the present invention. The reaction apparatus 1100 is composed of a lid 1110, a growth vessel 1120, and a raw material 1130. The raw material 1130 is germanium dioxide and lithium carbonate and molybdenum oxide as flux materials, with a chemical composition (molar ratio) of germanium dioxide, lithium carbonate, and molybdenum oxide of 1:10.5:16. The raw material 1130 is added to the growth vessel 1120, and the lid 1110 is closed to produce a bulk crystal by the flux method. Figure 15 is a diagram showing an example of a typical embodiment of a manufacturing apparatus used to produce a crystal substrate according to the present invention. The manufacturing apparatus 1200 is composed of an electric furnace 1210, a reaction vessel 1110, the raw material 1130, and a heater 1220. The reaction vessel 1110 containing the raw material 1130 was placed in the electric furnace 1210, and then heated to a heater temperature of 980°C and held for 2 hours. The reaction vessel 1130 was then removed from the cooled electric furnace 1210, and reacted with ultrapure water to remove the raw material 1130, resulting in the formation of r-GeO ２ A bulk crystal was obtained. ２ The bulk crystal was a tetragonal crystal with a long side of 3.0 mm, a short side of 3.0 mm, and a thickness of 2.0 mm.

[0047] The obtained GeO bulk crystal was measured using an X-ray diffractometer. The XRD diffraction results are shown in Figure 16. As is clear from Figure 16, the obtained bulk crystal is GeO having a tetragonal rutile crystal structure. ２ It is clear that it is a bulk crystal.

[0048] FIG. 1 is a diagram showing an example of a preferred embodiment of a film-forming apparatus according to the present invention. The film-forming apparatus 19 comprises a film-forming sample 20, a sample stage 21, carrier gas sources 22a and 22b, flow control valves 23a and 23b, a film-forming chamber 27, a heater 28, and an atomization device 30. The atomization device 30 comprises a raw material partition wall 24, a raw material solution to be atomized 24a, an ultrasonically-transmitting substrate 24b, a stage 24c, an ultrasonic vibrator 26, a guide partition wall 31, an ultrasonic-transmitting liquid tank 35, and an ultrasonic-transmitting liquid 36. FIG. 2 is a diagram showing another preferred embodiment of a film-forming apparatus when the atomization device according to the present invention is used as a film-forming atomization stage. The atomization device 30 comprises a raw material partition wall 24, a raw material solution to be atomized 24a, an ultrasonically-transmitting substrate 24b, a stage 24c, an ultrasonic vibrator 26, a guide partition wall 31, an ultrasonic-transmitting liquid tank 35, and an ultrasonic-transmitting liquid 36. The sample stage 21 is made of quartz, and the surface on which the film-forming sample 20 is placed is inclined from the horizontal plane. By fabricating both the film-forming chamber 27 and the sample stage 21 from quartz, impurities originating from the device are prevented from being mixed into the crystalline film formed on the film-forming sample 20. The atomization raw material solution 24a is contained in the mist generating source 24. The guide partition 31 is in contact with the ultrasonic-transmitting substrate 38. Figure 3 is a schematic diagram showing a cross-sectional side view of the atomization device used in the present invention. The atomization device 30 in Figure 3 comprises the raw material partition 24, the ultrasonic-transmitting substrate 24b, the base 24c, the ultrasonic vibrator 26, the guide partition 31, and the ultrasonic-transmitting liquid tank 35. The guide partition 31 is in contact with the ultrasonic-transmitting liquid tank 35. The guide partition 31 allows the ultrasonic waves emitted by the ultrasonic vibrator 26 to be more efficiently transmitted to the raw material partition 24.

[0049] Next, as the film-forming sample 20, a GeO film having a rutile crystal structure with a long side of 3.0 mm, a short side of 3.0 mm, and a thickness of 2.0 mm was prepared. ２ The substrate was placed on the sample stage 21, and the heater 28 was operated to raise the temperature inside the film formation chamber 27 to 700° C. Next, the flow rate control valve 23 was opened to supply carrier gas from the carrier gas source 22 into the film formation chamber 27. After the atmosphere inside the film formation chamber 27 was sufficiently replaced with the carrier gas, the flow rate of the carrier gas was adjusted to 1 L / min. Oxygen gas was used as the carrier gas.

[0050] Next, the ultrasonic vibrator 26 was vibrated at 3.0 MHz, and the vibration was propagated to the atomization raw solution 24a through the ultrasonic transmitter 25a, thereby atomizing the atomization raw solution 24a to generate raw material fine particles. These raw material fine particles were introduced into the film formation chamber 27 by the carrier gas, reacted in the film formation chamber 27, and formed GeO having a tetragonal rutile crystal structure on the film formation sample 20 by a CVD reaction on the film formation surface of the film formation sample 20. ２ A crystal film having a thickness of 2.0 μm was formed.

[0051] FIG. 17 shows the obtained GeO ２ 17A and 17B are diagrams showing cross-sectional TEM images of a crystalline film obtained by a transmission electron microscope (TEM). ２ (b) shows a crystalline film, and (b) shows a GeO ２ The bulk crystal is shown in Figure 17. ２ GeO on bulk crystal ２ It can be seen that a crystalline film is formed. ２ Crystalline film and GeO ２ The enlarged cross-sectional view and electron diffraction spot image of the vicinity of the interface with the bulk crystal are shown. ２ film, and Fig. 18(b) shows GeO ２ It is a bulk crystal. From FIG. ２ The crystalline film is GeO ２ It can be seen that the crystal structure is the same as that of the bulk crystal. ２ The dislocation density on the surface of the crystal film was measured by observing the cross-sectional TEM image. ９ / cm ２ and r-GeO with low dislocation density ２ From these results, it is concluded that the GeO film has a rutile-type tetragonal crystal structure. ２ GeO with good crystallinity on bulk crystal ２ A crystalline film was formed.

[0052] (Example 2) Film formation was carried out in the same manner as in Example 1, except that the carrier gas was changed from oxygen gas to nitrogen gas. The cross sections of the obtained bulk crystal and crystal film were measured using a transmission electron microscope (TEM). Figure 20 shows the cross section of the obtained GeO ２ 20(a) shows a cross-sectional TEM image of a crystalline film obtained by a transmission electron microscope (TEM). ２ (b) shows a crystalline film, and (b) shows a GeO ２ The bulk crystal is shown in Figure 20. ２ GeO on bulk crystal ２ It can be seen that a crystalline film is formed. ２ The enlarged cross-sectional view and electron diffraction spot image of the interface between the film and the GeO bulk crystal are shown. ２ film, and Fig. 21(b) is GeO ２ It is a bulk crystal. From FIG. ２ The crystalline film is GeO ２ It can be seen that the crystal structure is the same as that of the bulk crystal. ２ The dislocation density on the surface of the crystal film was measured by observing the cross-sectional TEM image. ９ / cm ２ and r-GeO with low dislocation density ２ As shown in Figure 22, a crystalline film was formed. ２ From these results, it is concluded that the GeO film has a rutile-type tetragonal crystal structure. ２ GeO with good crystallinity on bulk crystal ２ A crystalline film was formed, and the film thickness was 1.3 μm.

[0053] (Comparative Example 1) As Comparative Example 1, GeO ２ TiO with a rutile crystal structure from bulk crystals ２ Film formation was carried out in the same manner as in Example 1, except that the substrate was changed to (001). The cross section of the obtained crystalline film was measured using a transmission electron microscope (TEM). Figure 23 shows the cross section of the obtained GeO ２ The dislocation density on the surface of the crystal film was measured by observing it with a cross-sectional TEM image.２ The dislocation density of the crystalline film is 2.2 × 10 １０ / cm ２ It was.

[0054] From these results, it was found that Examples 1 and 2 had lower dislocation densities and better crystallinity than Comparative Example 1.

[0055] The layered structure and crystal film of the present invention are suitable for use in, for example, semiconductor devices.

[0056] 19 Film-forming apparatus 20 Film-forming sample 21 Sample stage 22a Carrier gas source 22b Dilution gas source 23a Flow rate control valve 23b Flow rate control valve 24 Raw material partition 24a Raw material solution for atomization 24b Ultrasonic transmitting substrate 24c Base 26 Ultrasonic vibrator 27 Film-forming chamber 28 Heater 30 Atomization device 31 Guide partition 33 Dilution gas supply pipe 34 Carrier gas supply pipe 35 Ultrasonic transmitting liquid tank 36 Ultrasonic transmitting liquid 37 Film-forming chamber 101a n － Type semiconductor layer 101b n ＋ n-type semiconductor layer 102 p-type semiconductor layer 103 metal layer 104 insulator layer 105a Schottky electrode 105b ohmic electrode 111a － Type semiconductor layer 111b n ＋ n-type semiconductor layer 114 semi-insulating layer 115a gate electrode 115b source electrode 115c drain electrode 118 buffer layer 121a wide band gap n-type semiconductor layer 121b narrow band gap n-type semiconductor layer 121c n ＋ n-type semiconductor layer 123 p-type semiconductor layer 124 semi-insulating layer 125a gate electrode 125b source electrode 125c drain electrode 128 buffer layer 129 substrate 131a － First n-type semiconductor layer 131b ＋ Second n-type semiconductor layer 131c ＋ n-type semiconductor layer 132 p-type semiconductor layer 134 gate insulating film 135a gate electrode 135b source electrode 135c drain electrode 138 buffer layer 139 semi-insulating layer 141a － First n-type semiconductor layer 141b＋ Second n-type semiconductor layer 141c ＋ P-type semiconductor layer 142 P-type semiconductor layer 145a Gate electrode 145b Source electrode 145c Drain electrode 151 N-type semiconductor layer 151a n － Type semiconductor layer 151b n ＋ n-type semiconductor layer 152 p-type semiconductor layer 154 gate insulating film 155a gate electrode 155b emitter electrode 155c collector electrode 161 n-type semiconductor layer 162 p-type semiconductor layer 163 light-emitting layer 165a first electrode 165b second electrode 167 light-transmitting electrode 169 substrate 1010a n － Type semiconductor 1010b n ＋ 1060 Electrolytic relaxation region 1100 Reactor 1110 Lid 1120 Growth vessel 1130 Raw material 1200 Reactor 1210 Electric furnace 1220 Heater

Claims

1. A laminated structure in which a crystal thin film made of a second crystal is laminated directly or via another layer on a crystal substrate made of a first crystal, and characterized in that both the first crystal and the second crystal contain germanium dioxide or a mixed crystal thereof as a main component.

2. The laminated structure according to claim 1, wherein the first crystal and the second crystal have the same crystal structure.

3. The laminated structure according to claim 1, wherein both the first crystals and the second crystals have a rutile structure.

4. The laminated structure according to claim 1, wherein both the first crystal and the second crystal are semiconductors.

5. The dislocation density of the crystal thin film is 1×10 １０ cm ―２ The laminate structure according to claim 1.

6. The laminated structure according to claim 1, wherein said crystal thin film is a single crystal thin film.

7. The laminated structure according to claim 1, wherein the crystal thin film has a thickness of 1 μm or more.

8. The volume of the crystal substrate is 15 mm ３ The laminate structure according to claim 1, wherein the laminate structure is as described above.

9. The area of ​​the crystal thin film is 5 mm ２ The laminate structure according to claim 1, wherein the laminate structure is as described above.

10. A crystalline thin film containing germanium dioxide or its mixed crystal as the main component, with a dislocation density of 1 x 10 １０ cm ―２ A crystal thin film characterized by the following:

11. A semiconductor device including a laminated structure, characterized in that said laminated structure is the laminated structure according to claim 1.

12. The semiconductor device according to claim 11, which is a power device.

13. The semiconductor device according to claim 11, which is a Schottky barrier diode (SBD), a junction barrier Schottky diode (JBS), a metal semiconductor field effect transistor (MESFET), a static induction transistor (SIT), a high electron mobility transistor (HEMT), a metal oxide semiconductor field effect transistor (MOSFET), a junction field effect transistor (JFET), an insulated gate bipolar transistor (IGBT), or a light emitting diode (LED).

14. An electronic device including a semiconductor device, characterized in that the semiconductor device is the semiconductor device according to claim 11.

15. A system including an electronic device, wherein the electronic device is the electronic device according to claim 14.

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