Machine-learning-aided logic synthesis using do-not-care-based backpropagation

Abstract

Machine-leaming-aided logic synthesis using do-not-care-based backpropagation, including constructing a neural network (NN) model based on a functional specification of a circuit design, training the NN model to perform a function of the circuit design, where nodes of the neural network perform a first Boolean function (e.g., AND), and where the training comprises do-not-care-based backpropagating, which may include explicitly computing target functions at fanins of the nodes. The NN may be converted to a two-input graph having nodes that represent a second Boolean function (e.g., AND). The function of the circuit design may include a multiplier function, and the graph may include an AND-inverter graph (AIG). A Boolean patch may be constructed to correct an error in the graph.

Description

Dkt Ref: SNOP / 4662WO01 (159288)MACHINE-LEARNING-AIDED LOGIC SYNTHESIS USING DO-NOT-CARE-BASED BACKPROPAGATIONTECHNICAL FIELD

[0001] The present disclosure relates to integrated circuit electronic design automation (EDA) and, more particularly, to machine-learning-aided logic synthesis using do-not-care-based backpropagation.BACKGROUND

[0002] In a machine learning (ML)-based neural network, edges (i.e., connections amongst nodes) are associated with weights. During training, the weights are gradually updated based on their partial derivatives, which may be referred to as gradients. Gradients may be determined with respect to error at outputs of the neural network. The neural network may include layers that perform weighted sum operations and apply non-linear functions. In such a situation, gradients may be derived as products of gradients at local outputs and corresponding local partial derivatives. The gradients may be computed in the reverse order of layers of the neural network in a process referred to as backpropagation.

[0003] Machine learning (ML) finds various applications in electronic design automation (EDA) of circuit designs. Combinational logic circuits (e.g., Boolean functions) are considered non-differentiable because their output values are discrete values (either logic 0 or 1) based on a combination of input values that are also discrete values, such that there is no continuous gradient between the output values to determine a derivative. Backpropagation is thus not directly applicable to combinational logic circuits due to their non-differentiability.Dkt Ref: SNOP / 4662WO01 (159288) BRIEF DESCRIPTION OF THE DRAWINGS

[0004] The disclosure will be understood more fully from the detailed description given below and from the accompanying figures of embodiments of the disclosure. The figures are used to provide knowledge and understanding of embodiments of the disclosure and do not limit the scope of the disclosure to these specific embodiments. Furthermore, the figures are not necessarily drawn to scale.

[0005] FIG. 1 depicts a framework or system that includes a model generator, a training system, and a correction and optimization system, according to an embodiment.

[0006] FIG. 2 is a flowchart of a method of machine-learning-aided logic synthesis using do-not-care-based backpropagation, according to an embodiment.

[0007] FIG. 3 depicts pseudo-code for training a template model based on do-not-care-based backpropagation, according to an embodiment.

[0008] FIG. 4 depicts a structure of the template model (i.e., levelized directed acyclic graph), according to an embodiment.

[0009] FIG. 5 depicts forward propagation for an internal node / ?, in a level i of the template model, according to an embodiment.

[0010] FIG. 6A depicts a portion of a neural network (NN), according to an embodiment

[0011] FIG. 6B depicts the NN with node weights,, according to an embodiment.

[0012] FIG. 6C depicts the NN with weight products of fanin edges, according to an embodiment.

[0013] FIG. 6D depicts do-not-care based backpropagation, according to an embodiment.

[0014] FIGS. 7A, 7B, and 7C depict curves of average accuracy, along with the range (min, max), according to an embodiment.

[0015] FIG. 8 depicts a table of results for two objectives: reducing graph nodes and reducing post technology-mapping area, according to an embodiment.Dkt Ref: SNOP / 4662WO01 (159288)

[0016] FIG. 9 depicts a flowchart of various processes used during the design and manufacture of an integrated circuit in accordance with some embodiments of the present disclosure.

[0017] FIG. 10 depicts a diagram of an example computer system in which embodiments of the present disclosure may operate.DETAILED DESCRIPTION

[0018] Aspects of the present disclosure relate to machine-learning-aided logic synthesis using do-not-care-b ased b ackpropagati on.

[0019] Fuzzy logic may be used to make combinational logic (i.e., Boolean operations) differentiable. For example, the AND operation (A) may be converted into a multiplication (•), where it holds the input-output relation such that 0A 0 = 0 0 = 0, 1 A 0 = 1 0 = 0, and 1 A 1 = 1 • 1 = 1. This approach is straight-forward and easily adoptable using common machine learning tools, but this relaxation may still cause a functional discrepancy between the differentiable model and the resulting logic circuit implementation.

[0020] Another technique is a softmax function that converts a vector of K real numbers into a probability distribution of K possible outcomes. The softmax function may be used in a neural network application, particularly in a final output layer of a neural network for a classification problem, to convert the K real numbers into a probability distribution over multiple classes. Since the softmax function is differentiable, the softmax function may be used as an alternative to an argmax function which evaluates to the largest index of a given vector. For a vector v, the softmax function can be expressed as:evsoftmax( ) = j- -

[0021] Disclosed herein is a machine learning (ML)-based logic synthesis framework (also refers to the present system and method herein) to synthesize logic circuits from a design specification (e.g., a hardware description language (HDL) / register transfer level (RTL) basedDkt Ref: SNOP / 4662WO01 (159288)design specification), using a do-not-care-based backpropagation method that makes it possible to learn non-differentiable attributes of logic circuits. The framework enables logic optimization to discover / reach new solutions in a design space. Based on a given template, the framework constructs and trains a ML model of a circuit specification, using the present do-not-care-based backpropagation method. A functionally incorrect model may be addressed with a Boolean patch function that makes the model functionally correct.

[0022] The framework generates circuit designs that have a different structure from those derived from other methods, such as sum-of-products (SOP)-based and binary decision tree diagram (BDD)-based methods. The framework helps logic optimization to reduce structural bias effects, exploring previously unreachable solutions on the design space, resulting in power, performance, and area (PPA) improvements.

[0023] The framework includes a model generation stage, a fitting stage, and a correction stage. A template is provided as a starting structure of the model, which is fed to the fitting stage where the model is trained to implement a target Boolean function. The terms "fitting" and "training" are used interchangeably. During correction, Boolean techniques are applied to correct outputs that do not completely satisfy the specification. During training, a do-not-care-based backpropagation method may be used to improve accuracy and convergence of the model. Instead of relying on fuzzy logic to back propagate the gradients, a target function is explicitly determined / computed at each fanin. Where the target function is incompletely-specified, some patterns may be do-not-care. The do-not-cares may be exploited to improve model convergence and size.

[0024] As disclosed herein, internal nodes of the neural network perform a Boolean function to produce an output value, and target functions are computed in a reverse ordering of layers of the neural network (i.e., backpropagating from a last layer to a first layer), based on the target functions of upper level node fanins that are already computed, and also based on argmaxDkt Ref: SNOP / 4662WO01 (159288)fanin values of the node. The target functions indicate whether fanins of the nodes should be trained toward -1 or 1. For some primary input patterns, the output of a node may be already correct, controlled by one of its fanins, and in such a case, non-controlling fanin of the node may be excluded from a loss function during training, such that training of that controlling fanin can focus on other primary input patterns.

[0025] In examples below, the framework is used to synthesize multiplier circuits. The framework is not, however, limited to multiplier circuits. Multiplier circuits are used in a variety of circuit designs, including microprocessors, digital signal processing (DSP) blocks, and ML-accelerators, which heavily rely on multiply and accumulate (MAC) blocks. ML accelerators often allow for a lower precision, and thus small multipliers are common. Experimental results show that the framework achieves substantial area reduction for 4-bit to 10-bit multiplier circuits (e.g., to 30% reduction, or more). Experimental results further show that the backpropagation method can achieve a higher accuracy than other forms of backpropagation for logic circuit learning. In an example, the framework produces a functionally correct 4-bit multiplier in most situations (e.g., 92% of the time, or more).

[0026] A ML-based logic synthesis framework, as disclosed herein, allows deeper exploration of the solution space, finding new multiplier structures. Do-not-care-based backpropagation enables logic circuit learning to achieve a higher accuracy and converge faster than other methods. Boolean patch functions permits correcting for erroneous outputs.

[0027] The framework disclosed herein generates a technology-independent representation to implement a target function. Examples below use an AND-inverter graph (AIG) as the underlying structure. The framework is not, however, limited to AIGs.

[0028] The framework allows for flexibility by separating the challenge into sub-components for which various approaches may be applied in various combinations. Template and fitting may be integrated to learn the structure of different multipliers in a similar way that ML modelsDkt Ref: SNOP / 4662WO01 (159288)are trained. Do-not-care-based backpropagation broadens the potential of training-based synthesis to functions that are too complex to be fully learned, for tasks where approximation is not allowed. Where training does not achieve 100% accuracy (i.e., exact implementation), the framework performs correction using Boolean techniques. AIG optimization techniques may be used to optimize the AIG derived by the framework. Performance of optimization methods may depend on the DAG structure. Generating designs with different structures may be useful to help escape local minima and to unlock logic optimization to explore new possibilities in the design space.

[0029] Technical advantages of the present disclosure include, but are not limited to, accurately modeling logic circuits for synthesis by training a model using a don’t-care-based backpropagation method, which makes it possible to learn non-differentiable attributes of logic circuits efficiently. Technical advantages further include reduction of numbers of transistors needed to implement a logic circuit, which may reduce area, power, and / or latency of the logic circuit. In an example, a generated multiplier circuit encompasses less area than multiplier circuits generated by other methods, which is good for artificial intelligence (Al) designs that are rich in multipliers. Technical advantages further increased accuracy of generating multipliers that satisfy a circuit design specification, provide increased computing speed, and / or reduce computing resources for generating logic circuits.

[0030] FIG. 1 depicts a framework or system 100 that includes a model generator 110, a training system 112, and a correction and optimization system 114, according to an embodiment. System 100 may include circuitry (e.g., combinational logic and / or sequential logic) that performs various functions disclosed herein. Alternatively, or additionally, system 100 may include a processor (e.g., processing device 902 of FIG. 9) and memory (e.g., main memory 904, data storage device 918 of FIG. 9) configured with instructions / code (e.g., instructions 926, instructions 916 of FIG. 9) to perform one or more of the functions disclosedDkt Ref: SNOP / 4662WO01 (159288)herein. Features of system 100 may be centralized or distributed in one or more of a variety of combinations, without deviating from the scope of the present disclosure. System 100 is described below with reference to FIG. 2.

[0031] FIG. 2 is a flowchart of a method 200 of machine-learning-aided logic synthesis using do-not-care-based backpropagation, according to an embodiment. Method 200 is described below with reference to system 100. Method 200 is not, however, limited to the example of system 100.

[0032] At 202, model generator 110 receives a functional specification 102 of a circuit design (e.g., RTL) and structural information 104 for a machine-learning (ML) model (e.g., a neural network). Functional specification 102 may be represented as a Boolean function. Structural information 104 may include, for example and without limitation, a number of levels, and a number of nodes per level. Structural information 104 may be provided by a user.

[0033] At 204, training system 112 receives training configuration parameters 106 for adjusting fitting (e.g., training criteria). Training configuration parameters 106 may include hyper-parameters 108 and / or a criterion 130 (e.g., a resource criterion and / or a time criterion). Hyper-parameters 108 may include, without limitation, a learning rate and beta (i.e., coefficients used for computing running averages of gradient and its square). Training configuration parameters 106 may be provided by a user. Note that receipt of the functional specification at 202 and receipt of the training configuration parameters may be performed sequentially, in any order, and / or in parallel.

[0034] At 206, model generator 110 constructs / generates a template 122 for a machinelearning (ML) model. Template 122 may include nodes that perform a function (e.g., a Boolean function and / or an end function).Dkt Ref: SNOP / 4662WO01 (159288)

[0035] Training system 112 may further receive input patterns and corresponding output patterns of the circuit design, for training purposes. The output patterns may serve as labels for the input patterns.

[0036] Model generator 110 may use one or more of a variety of strategies to generate template 122. In an example, template 122 includes layers of fully connected nodes. In this example, a user may specify a number of inputs, a number of layers, and / or numbers of nodes per layer. Template 122 may include skip connections in which nodes in non-adjacent levels are to be connected. Alternatively, the user may provide template 122 as a starting point. As described below, system 100 resynthesizes portions of logic to provide new structures to help logic optimization to explore more solutions in the design space.

[0037] At 208, training system 112 trains / fits template 122 to predict / infer the output patterns of functional specification 102 based on the input patterns of functional specification 102. During training, training system 112 gradually adjusts connections of template 120, and adjusts weights of the connections to reduce error. Training system 112 may adjust training hyperparameters 108 to improve accuracy and convergence.

[0038] In neural networks, each connection (i.e., edge) between a pair of nodes is associated with a weight, which gradually updates by the amount of its partial derivative, called a gradient. During training, the gradient is given with respect to the error at the network outputs. Because the network includes layers that perform a weighted sum operation and apply some non-linear functions, gradients may be derived as a product of a gradient at the local output and a local partial derivative. Hence, gradients are computed in the reverse order of layers, and the process is called backpropagation.

[0039] In backpropagation in deep neural networks, parameters of the model are updated according to the gradients propagated from the Pls in respect of the error observed at the POs.Dkt Ref: SNOP / 4662WO01 (159288)As described further above, backpropagation is not directly applicable to combinational logic circuits because combinational logic circuits (i.e., Boolean functions) are non-differentiable.

[0040] As disclosed herein, training system 112 may employ do-not-care-based backpropagation. Do-not-care-based backpropagation explicitly computes the target functions at each fanin. Alternatively, or additionally, training system 112 may use other methods, such as simulated-annealing.

[0041] Do-not-cares are a flexibility in Boolean functions, where the local function can be changed without affecting the global function (i.e., specification 102). Do-not-cares play an important role in logic synthesis as they allow for function simplification. In examples presented herein, do-not-cares arise when one of the node fanins is 0. Where the nodes in the model are ultimately converted to a 2-input AND-gate, regardless of the values of other fanins, the output is determined to be 0. In this situation, by making sure at least one fanin remains 0, the other fanins are called do-not-cares. Do-not-cares are exploited during the fitting stage to help the model converge.

[0042] Training system 112 outputs trained template 122 as a model 124, such as a neural network, in which nodes perform Boolean functions, and edges may be inverted or noninverted.

[0043] At 210, correction and optimization system 114 synthesizes / converts model 124 to a graph 116. In an example, graph 116 includes an AND-Inverter graph (AIG). An AIG is a directed acyclic graph (DAG) in which each node represents a 2-input AND gate, and edges may be inverted. Inputs and outputs of the AIG may be referred to as primary inputs (Pls) and primary outputs (POs), respectively. Pls do not have incoming edges (fanins). POs do not have outgoing edges (fanouts). System 100 is not limited to AND gates or AIGs.

[0044] In an example, a node of model 124 has multiple edges for each fanin, each edge having a corresponding weight, and correction and optimization system 114 represents the node as aDkt Ref: SNOP / 4662WO01 (159288) corresponding vertex of graph 116 (e.g., a learned DAG) having a single edge for each fanin. Correction and optimization system 114 may select the edge of the node of model 124 having the largest weight to serve as the edge of the corresponding vertex of graph 116. Correction and optimization system 114 may modify graph 116 with a corrective patch function 132, such as described further below, and / or may optimize graph 116. Internal vertexes of graph 116 may perform the same functions (e.g., a Boolean function) as the corresponding nodes of model 124.

[0045] Correction and optimization system 114 may include a synthesis engine 126 that performs logic synthesis (e.g., multi-level logic synthesis). Synthesis engine 126 may perform transformations, such as rewriting, re- substitution, and refactoring. As these transformations operate over a DAG, the structure of the graph 116 plays a role on what optimization can achieve. This is known as structural bias. A technique to reduce structural bias during optimization is to interleave optimization with look-up table (LUT) mapping and do-not-care optimization to unlock further simplification. Such transformations may be used during postprocessing to optimize graph 116.

[0046] Synthesis engine 126 may correspond to a synthesis and design for test block 818, described further below with reference to FIG. 8.

[0047] At 212, correction and optimization system 114 determines whether graph 116 satisfies functional specification 102 (e.g., produces the output patterns of the circuit design based on the input patterns of the circuit design). If graph 116 does not fully satisfy functional specification 102, processing proceeds to 214, where correction and optimization system 114 synthesizes a corrective patch function 132, and adds corrective patch function 132 to graph 116. Correction and optimization system 114 may employ a Boolean difference function, such as described below.Dkt Ref: SNOP / 4662WO01 (159288)

[0048] The Boolean difference of two Boolean functions f(xi... Xn) and g(xi... Xn) is defined as = f © g, where © is the XOR operator. Boolean difference is commonly used to indicate if two functions are functionally equivalent. Correction and optimization system 114 may construct corrective patch function 132 based on a Boolean difference.

[0049] Correction and optimization system 114 may employ one or more of a variety of approaches for constructing corrective patch function 132. In an example, correction and optimization system 114 enumerates input patterns for which graph 116 does not match specification 102, and constructs corrective patch function 132 to flip the erroneous output for those patterns with Boolean difference. Such enumeration may be exhaustive (e.g., and the patch may be derived from a truth-table), or may be symbolic by using BDDs (e.g., and the patch may be derived from the BDDs). Other approaches include rewiring, and engineering change orders (ECOs). System 100 may support correction functions to be synthesized with exhaustive and symbolic approaches, and / or or rewiring. A small error rate does not necessarily translates into a small patch function. Thus, a patch function cost estimation may be integrated within the fitting.

[0050] At 216, system 100 outputs a synthesized graph 116 (e.g., an AIG) that implements functional specification 102. In an example, system 100 or another system converts graph 116 to a circuit design.

[0051] Do-not-care-based backpropagation is further described below. Do-not-care situations are an important concept of logic synthesis. Do-not-care-based backpropagation explicitly calculates the target function for each fanin. Do-not-care-based backpropagation resolves the problem of gradients not reflecting the non-differentiable property of logic circuits, and improves the accuracy of the resulting circuit design as well as the training convergence.

[0052] FIG. 3 depicts pseudo-code 300 for training with do-not-care-based backpropagation, according to an embodiment.Dkt Ref: SNOP / 4662WO01 (159288)

[0053] In the example of FIG. 3:wi is the weights of the incoming edges of the nodes in layer z;L is the last layer number;" Input pattern" is a pattern that is fed to the neural network, analogous to a sample image in image classification machine learning;" Output pattern" is a pattern the network should output, analogous to a sample label in image classification machine learning;variable "z" is used to iterate through layers of the neural network;"x" represents output values of nodes in the layers before layer i;" Forward" is a function that concatenates the output values of layers i to x. ai represents argmax fanin values of the nodes in layer i;bi represents softmax fanin values of the nodes in layer i;m represents weight products;" InitializeW eightProducts" is a function that computes the weight products for the last layer, such as described further below;is a target function(s);" Backpropagation" is a function that performs do-not-care based backpropagation; andMinimizeLoss(Z>, f) is a function that computes loss, such as described further below.

[0054] FIG. 4 depicts a structure 400 of a model (i.e., levelized DAG), according to an embodiment. In the example of FIG. 4, each node of structure 400 belongs to a level in the range between 0 and L. For level 0, the number of primary input nodes is given by the number of Pls present in the specification function. For level 0 (L), the number of primary output nodes is given by the number of POs present in the specification function. The nodes in the otherDkt Ref: SNOP / 4662WO01 (159288)levels (between 1 and L-l) are referred to as internal nodes. In FIG. 4, each node of structure 400 is connected to all nodes in lower levels.

[0055] When constructing the model from the structural input, each internal node and primary output node takes as input the outputs of all nodes that belong to the lower levels. As the output of framework is an AIG, after training, each internal node is converted into a 2-input AND-gate (in other examples, the internal nodes may be converted to other types of logic gates). The two fanins of the AND gates are selected among all the inputs available at the node. Inversions and duplication (for buffer) are allowed. For the PO nodes, only one fanin is selected. Similarly to internal nodes, the fanin might be inverted.

[0056] Let the nodes to be indexed from O to N - 1, in the ascending order of levels, where N is the total number of nodes in the model. Ni denotes the number of nodes in level i, and Mi denotes the total number of nodes in the levels lower than i. Mi can be expressed as:, for 1 > 1, and Mo=O.

[0057] The nodes in level i are indexed from Mi to Mi+i~l. For example, the nodes in level 0 are indexed from 0 to No -1. Nodes in level 1 are indexed from No to No+Ni-I, and so on. A node with index p is simply referred to as node p.

[0058] Forward propagation may be used to assess the accuracy of the model. Forward propagation in the model may behave similarly to simulation in logic synthesis. During forward propagation, the output of each internal and PO node is assigned to either -1 (logical zero) or 1. At the beginning of forward propagation, the primary inputs nodes are assigned to the input pattern for which the model is being evaluated (the input pattern to simulate the structure). Each internal node p has two fanins. The first fanin may be represented as wP,i, and the second fanin may be represented as wP,o. The parameter wP,o determines which incoming edge is used for the first fanin. The parameter, wP,i determines which incoming edge is used for the secondDkt Ref: SNOP / 4662WO01 (159288)fanin. The selected incoming edge is fed to the function of the node (e.g., an AND function). For each node in level i, each parameter is a vector of length 2Mi.

[0059] FIG. 5 depicts forward propagation for an internal node 500 (i.e., node p in a level i) according to an embodiment. In FIG. 5, two kinds of values are calculated for each fanin: the argmax fanin value and the softmax fanin value. The argmax fanin value is calculated by taking the argmax of the parameter vector. The argmax fanin value is assigned to the output values for the nodes in the lower levels (which is propagated to the inputs of nodes in the upper levels), whose index is equals to the argmax modulo Mi. For argmax larger than or equal to Mi, the value is negated. Hence, given a node p in the level i, the argmax fanin values aP,o and aP,i for the first and second fanin, respectively, can be expressed as follows:Qp,0=yargmax(lVp,o),Qp,l=y argmax(lVp,l),where x = (xo, xi, xM._x) is the output values of nodes in the previous layers, and y = (yo, yi, y2Mt-i) iscalculated such thaty / c = Xk for k < Mt and yk = — xk-M. for k > Mt.

[0060] The softmax fanin value is calculated by taking the softmax of the parameter vector. This result is assigned to a weighted sum of the output values of the nodes in the lower levels, using the softmax as a weight. The softmax fanin values bP,o and bP,i for the first and second fanin, respectively, can be expressed as follows:bP,o = y • softmax(wp,o),bP,i = y • softmax(wp,i).

[0061] The output of internal node is calculated using the argmax fanin values. Note that this operation does not need to be differentiable, because do-not-care backpropagation does not propagate gradients through it. The output of node p, xP, is expressed as follows:Dkt Ref: SNOP / 4662WO01 (159288)I Isv" 1 A J 1Xzc *» <p~L othewhe

[0062] Each primary output node has only one parameter, which is a vector of length 2 x ML, since each primary output of an AIG has only one driver. In the same way as internal nodes, the argmax fanin value and the softmax fanin value are calculated for each primary output node. The output of primary output node is directly assigned to the argmax fanin value of the node, which is then used as an output of the model.

[0063] Backpropagation is described below.

[0064] FIG. 6A depicts a portion of a neural network (NN) 600, according to an embodiment. A last layer n of NN 600 (i.e., an output layer) includes output nodes 604-5 and 604-6. A next-to-last layer, n-1, includes nodes 604-3 and 604-4. A preceding layer, n-2, includes nodes 604-1 and 604-2. Nodes 604-1 through 604-4 are internal nodes. Nodes 604-5 and 604-6 are output nodes. Nodes 604-1 through 604-6 may be collectively referred to as nodes 604.

[0065] NN 600 further includes edges 602-1 through 602-16 (collectively, edges 602). During training, training system 112 adjusts current weights of edges 602 (e.g., initial randomly-assigned weights or partially-trained weights), to provide desired values at outputs POO and PO1. The desired output is based on a training inputs. Example current weights of edges 602 are provided in Table 1 below.TABLE 1Dkt Ref: SNOP / 4662WO01 (159288)0.2602-60.4602-70.7602-80.2602-90.1602-100.4602-110.8602-120.4602-130.2602-140.3602-150.6602-16

[0066] NN 600 further includes multiplexers 606 that determine the softmax and argmax values during forward propagation, such as described further above with reference to FIG. 5.

[0067] During backpropagation, training system 112 determines internal node weights for nodes of next-to-last layer n-1 (i.e., nodes 604-3 and 604-4) based on current weights of fanout edges of the nodes, such as described below with reference to FIG. 6B.

[0068] FIG. 6B depicts NN 600 with node weights, according to an embodiment. For the examples of FIG. 6B and Table 1, training system 112 determines a node weight for node 604-3 as a sum of the current weights of edges 603-13 and 602-14 (i.e., fanouts of node 604-3) as (0.4 + 0.2) = 0.6, and determines a node weighted for node 604-4 as (0.3 + 0.6) = 0.9.

[0069] For output nodes 604-5 and 604-6 (i.e., of last layer / ?), node weights are the same as the respective weights.

[0070] Training system 112 then determines weight products for fanin edges of the nodes of next-to-last layer n-1 based on the current weights of the fanin edges of the nodes and the node weights, and determines node weights for nodes of preceding layer n-1 based on the weight products of fanout edges of the nodes, such as described below with reference to FIG. 6C. FIG.Dkt Ref: SNOP / 4662WO01 (159288)6C depicts NN 600 with weight products of fanin edges of nodes of next-to-last layer n-1, and node weights for nodes of preceding layer n-2, according to an embodiment. The weight products indicate a likelihood that the respective fanin edges will be used in a corresponding graph or circuit design.

[0071] For node 604-3, training system 112 determines:the weight product for edge 602-1 as (0.6*0.6)=0.6;the weight product for edge 602-7 as (0.6*0.4)=0.24;the weight product for edge 602-2 as (0.6*0.3)=0.18; andthe weight product for edge 602-8 as (0.6*0.7)=0.7.

[0072] For node 604-4, training system 112 determines:the weight product for edge 602-5 as (0.9*0.6)=0.54;the weight product for edge 602-11 as (0.9*0.4)=0.42;the weight product for edge 602-6 as (0.9*0.2)=0.18; andthe weight product for edge 602-12 as (0.9*0.8)=0.72.

[0073] Training system 112 then determines node weights for nodes of preceding layer n-2 (i.e., nodes 604-1 and 604-2). For node 604-1, training system 112 determines the node weight as 0.36+0.18+0.1+0.1+0.54+0.18=1.46. For node 604-2, training system 112 determines the node weight in a similar fashion. The foregoing processes may be backpropagated to any additional preceding layers of NN 600.

[0074] Do-no-care based backpropagation is described below with reference to FIG. 6D. FIG.6D depicts do-not-care-based backpropagation with respect to a node / ?, according to an embodiment.

[0075] In FIGS. 6A through 6C, each fanin (e.g., outputs of multiplexers 606) has a target function. An objective of training is to make the argmax fanin value the same as the targetDkt Ref: SNOP / 4662WO01 (159288)function. In other words, the target functions represent desired values of argmax fanin values. As described below, during backpropagation, the target function may be backpropagated from a fanout such that fanins are trained to implement the target function. Do-not-cares may be considered during the backpropagation when the targets is "-1" or argmax for "other fanin" is "-1," such as described below.

[0076] Do-not-care-based backpropagation (i.e., method 660) may be performed starting from a level L down to level 1, in a descending order of levels. First, target functions of the fanins in level L are set to the target functions of the corresponding primary outputs in the specification. For the lower levels, the target functions are calculated based on looking at the desired functions at the node’s potential fanout edges. Each potential fanout is represented as a tuple (q, co, ci), where q is the node index of the fanout, co is the fanin position, which is either 0 or 1, and corresponds to the first or the second fanin, respectively. Value ci is a Boolean value to indicate the inverter presence. In an example model, a potential fanout node with index q in level i, has an index between Mi+i and N - 1.

[0077] The target function is calculated based on a weighted sum of the target functions of the potential fanouts, where the weight represents their likeliness of being used in a graph or circuit design. A weight product mp q Co Cimay be determined for each node p and each potential fanout (q, co, ci) as the backpropagation proceed. Initially, for each pair containing a node p < ML and a primary output node q, the weight product mP,q,o,o is assigned to the pthelement, and mP,q, 0,1 is assigned to the (p + Mr)thelement of the softmax of the parameter of the primary output node, while mP,q, i,o and mP,q,i,i are assigned to 0. Let sq,o = (sq,o,o, s?,o,i,...,be softmax(wq,o). This assignment may be expressed as:TTlp,g,0,0 = Sq,0,p>mp,qfi,1 = Sq Qp+ML,mP,q,i,o = 0, andDkt Ref: SNOP / 4662WO01 (159288)Tflp, <7,1,1 — 0.

[0078] Training system 112 may perform do-not-care backpropagation for each node p in level i < L, as shown in FIG. 6D, as follows:(1) The weight products are normalized as follows:***** * *~~ *wwhere tf=(2) A weighted sum g of the target functions of the potential fanouts is calculated as follows:where is the desired function at c^th fanin of node h and a is a custom xor~cperator?which flips the sign ofwhen Cj - 1(3) The target functions fp,o and fP,i are calculated as follows:EQ. 1EQ. 2Dkt Ref: SNOP / 4662WO01 (159288)

[0079] In EQ. 1, if g < 0 or if ap,0=l, and if ap,l= -1, then fp,0 is set to 0. Otherwise, fp,0 is set to the weighted sum g of the target functions of the potential fanouts. In EQ. 2, if g < 0 or ap,l=l, and if ap,0= -1, then fp, 1 is set to 0. Otherwise, fp,l is set to the weighted sum g of the target functions of the potential fanouts. In other words, if the weighted sum g is negative, the output of the node should be trained towards -1 (logical 0), whereas, if one of the argmax fanin values is already -1 (logical 0), there is no need to train the other fanin, in which case it’s target function is assigned 0 (logical don't care).(4) For each node r in the lower levels, weight products mr p Co care calculated for all co, ci Go, i as follows:wllCEA a® 0 J, Slid

[0080] Items (1) and (2) above backpropagate the target functions from potential fanouts. Item (3) above augments the target functions with do-not-cares based on the current values of the fanins. Item (4) prepares the weight products for backpropagation to the lower levels. Do-not-care is assigned when the other fanin takes -1 (logical zero), since the nodes correspond to AND gates. On the other hand, if the fanin itself takes -1 and the target function is 1, the do-not-care is not backpropagated. This is because both fanins need to change to evaluate the output to a desired value.

[0081] The objective of training is to get each softmax fanin value closer to the sign of the calculated target function. The sign of f is defined as a function that takes 1 when f > 0, -1Dkt Ref: SNOP / 4662WO01 (159288)when f < 0, and 0 when f = 0. Then, training is formulated as a minimization problem over a sum of the losses calculated at each node p as follows:where i is an arbitrary loss function.

[0082] This formula controls the magnitude using the target function in the coefficients, while the softmax fanin values are oriented towards either -1 or 1, based solely on its sign for the fanins in the care set. Although the softmax fanin values are not directly used to calculate the outputs of nodes, the updated parameters affect the outputs of nodes via the argmax fanin values as in straight-through estimators.

[0083] Experimental results are presented below. The framework disclosed herein (i.e., system 100 / method 200), including do-not-care-based backpropagation, is compared with softmax and gumbel-softmax approaches for making logic circuits differentiable. For these experiments, a model was trained to learn a 4-bit multiplier. The experiment was run 100 times, independently. The same model structure was specified for the backpropagation, softmax, and gumbel-softmax approaches. The model structure includes 20 levels of internal nodes with 20 nodes per level.

[0084] For each approach, mean square error was used as the loss function, and an adaptive moment estimation was used as the optimizer. The hyper parameter (Zr, / ?i, / ?2) was set to (0.3, 0.5, 0.9) for the softmax and gumbel-softmax, and (0.1, 0, 0.9) for the disclosed framework (i.e., system 100 / method 200). The hyper-parameters were selected because they presented the highest accuracy for each of the methods in the experiments.

[0085] FIG. 7A depicts a curve 700 of average accuracy, along with the range (min, max), for Softmax according to an embodiment. FIG. 7B depicts a curve 720 of average accuracy, along with the range (min, max), for Gumbel-Softmax, according to an embodiment. FIG. 7C depicts a curve 740 of average accuracy, along with the range (min, max), for system 100, according to an embodiment.Dkt Ref: SNOP / 4662WO01 (159288)

[0086] The accuracy was evaluated on the function of the converted logic circuit. The result indicates that the framework effectively learned the function as a logic circuit. Notably, 92 runs achieved 100% accuracy (exact implementation) by the framework as shown in FIG. 7C. No runs performed with the softmax and gumbel-softmax approached the level of accuracy of the framework as shown in FIG. 7A and FIG. 7B respectively. This shows the efficiency of the framework, which can learn an exact implementation of a 4-bit multiplier 92% of the time, while other methods fail to derive any functionally correct circuit in a 100 runs.

[0087] Results of using the framework to generate new multipliers structures are presented below. The optimization is performed iteratively: a model is constructed by replacing a part of the circuit with fully connected layers. The training is performed using do-not-care-based backpropagation, and the resulting circuit is corrected when necessary using binary decision diagrams (BDDs). The resulting AIG is used to feed optimization, with an AIG-based optimization flow, similar to a LUT -based optimization approach.

[0088] FIG. 8 depicts a Table 800 of results for two objectives: reducing AIG nodes and reducing post technology-mapping area, according to an embodiment. In Table 800, the generated multipliers (i.e., "proposed") are compared to "baseline" multipliers (e.g., multipliers available in a synthesis flow). As can be seen in Table 800, the generated multipliers greatly reduce the AIG count compared to the baseline multipliers. Table 800 further shows AIG size reduction ranging from 27.6% up to 35%. In Table 800, the baseline multipliers are designed to reduce area rather than to reduce AIG size. Hence, the framework is also run to generate multipliers with small area post technology-mapping. The area gains range from 2.4% up to 32.8%. In the foregoing examples, the focus is on AIG size and area optimization. If timing is tight, the framework may choose other multipliers architectures (e.g., based on cost and / or other considerations).Dkt Ref: SNOP / 4662WO01 (159288)

[0089] To show the benefits of the generated multipliers, three Al accelerator designs were selected, rich in multipliers, and embedded in a synthesis tool to make the selected generated multipliers available for selection by the synthesis tool.

[0090] A framework as disclosed herein, and / or portions thereof, may be implemented on / by a system that includes circuitry that performs various functions disclosed herein. The circuitry may be combined or distributed in one or more of a variety of combinations, without deviating from the scope of the present disclosure. Alternatively, or additionally, the system may include a processor and memory configured with instructions / code to perform one or more of the functions disclosed herein. The system may represent a centralized system and / or a distributed system. Examples are provided below.

[0091] FIG. 9 illustrates an example set of processes 900 used during the design, verification, and fabrication of an article of manufacture such as an integrated circuit to transform and verify design data and instructions that represent the integrated circuit. Each of these processes can be structured and enabled as multiple modules or operations. The term ‘EDA’ signifies the term ‘Electronic Design Automation.’ These processes start with the creation of a product idea 910 with information supplied by a designer, information which is transformed to create an article of manufacture that uses a set of EDA processes 912. When the design is finalized, the design is taped-out 934, which is when artwork (e.g., geometric patterns) for the integrated circuit is sent to a fabrication facility to manufacture the mask set, which is then used to manufacture the integrated circuit. After tape-out, a semiconductor die is fabricated 936 and packaging and assembly processes 938 are performed to produce the finished integrated circuit 940.

[0092] Specifications for a circuit or electronic structure may range from low-level transistor material layouts to high-level description languages. A high-level of representation may be used to design circuits and systems, using a hardware description language (‘HDL’) such asDkt Ref: SNOP / 4662WO01 (159288)VHDL, Verilog, SystemVerilog, SystemC, MyHDL or OpenVera. The HDL description can be transformed to a logic-level register transfer level (‘RTL’) description, a gate-level description, a layout-level description, or a mask-level description. Each lower representation level that is a more detailed description adds more useful detail into the design description, for example, more details for the modules that include the description. The lower levels of representation that are more detailed descriptions can be generated by a computer, derived from a design library, or created by another design automation process. An example of a specification language at a lower level of representation language for specifying more detailed descriptions is SPICE, which is used for detailed descriptions of circuits with many analog components. Descriptions at each level of representation are enabled for use by the corresponding systems of that layer (e.g., a formal verification system). A design process may use a sequence depicted in Fig. 9. The processes described by be enabled by EDA products (or EDA systems).

[0093] During system design 914, functionality of an integrated circuit to be manufactured is specified. The design may be optimized for desired characteristics such as power consumption, performance, area (physical and / or lines of code), and reduction of costs, etc. Partitioning of the design into different types of modules or components can occur at this stage.

[0094] During logic design and functional verification 916, modules or components in the circuit are specified in one or more description languages and the specification is checked for functional accuracy. For example, the components of the circuit may be verified to generate outputs that match the requirements of the specification of the circuit or system being designed. Functional verification may use simulators and other programs such as testbench generators, static HDL checkers, and formal verifiers. In some embodiments, special systems of components referred to as ‘emulators’ or ‘prototyping systems’ are used to speed up the functional verification.Dkt Ref: SNOP / 4662WO01 (159288)

[0095] During synthesis and design for test 918, HDL code is transformed to a netlist. In some embodiments, a netlist may be a graph structure where edges of the graph structure represent components of a circuit and where the nodes of the graph structure represent how the components are interconnected. Both the HDL code and the netlist are hierarchical articles of manufacture that can be used by an EDA product to verify that the integrated circuit, when manufactured, performs according to the specified design. The netlist can be optimized for a target semiconductor manufacturing technology. Additionally, the finished integrated circuit may be tested to verify that the integrated circuit satisfies the requirements of the specification.

[0096] During netlist verification 920, the netlist is checked for compliance with timing constraints and for correspondence with the HDL code. During design planning 922, an overall floor plan for the integrated circuit is constructed and analyzed for timing and top-level routing.

[0097] During layout or physical implementation 924, physical placement (positioning of circuit components such as transistors or capacitors) and routing (connection of the circuit components by multiple conductors) occurs, and the selection of cells from a library to enable specific logic functions can be performed. As used herein, the term ‘cell’ may specify a set of transistors, other components, and interconnections that provides a Boolean logic function (e.g., AND, OR, NOT, XOR) or a storage function (such as a flipflop or latch). As used herein, a circuit ‘block’ may refer to two or more cells. Both a cell and a circuit block can be referred to as a module or component and are enabled as both physical structures and in simulations. Parameters are specified for selected cells (based on ‘standard cells’) such as size and made accessible in a database for use by EDA products.

[0098] During analysis and extraction 926, the circuit function is verified at the layout level, which permits refinement of the layout design. During physical verification 928, the layout design is checked to ensure that manufacturing constraints are correct, such as DRC constraints, electrical constraints, lithographic constraints, and that circuitry function matches the HDLDkt Ref: SNOP / 4662WO01 (159288) design specification. During resolution enhancement 930, the geometry of the layout is transformed to improve how the circuit design is manufactured.

[0099] During tape-out, data is created to be used (after lithographic enhancements are applied if appropriate) for production of lithography masks. During mask data preparation 932, the ‘tape-out’ data is used to produce lithography masks that are used to produce finished integrated circuits.

[0100] A storage subsystem of a computer system (such as computer system 1000 of FIG. 10) may be used to store the programs and data structures that are used by some or all of the EDA products described herein, and products used for development of cells for the library and for physical and logical design that use the library.

[0101] FIG. 10 illustrates an example machine of a computer system 1000 within which a set of instructions, for causing the machine to perform any one or more of the methodologies discussed herein, may be executed. In alternative implementations, the machine may be connected (e.g., networked) to other machines in a LAN, an intranet, an extranet, and / or the Internet. The machine may operate in the capacity of a server or a client machine in clientserver network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

[0102] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a Personal Digital Assistant (PDA), a cellular telephone, a web appliance, a server, a network router, a switch or bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that machine. Further, while a single machine is illustrated, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.Dkt Ref: SNOP / 4662WO01 (159288)

[0103] The example computer system 1000 includes a processing device 1002, a main memory 1004 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM), a static memory 1006 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage device 1018, which communicate with each other via a bus 1030.

[0104] Processing device 1002 represents one or more processors such as a microprocessor, a central processing unit, or the like. More particularly, the processing device may be complex instruction set computing (CISC) microprocessor, reduced instruction set computing (RISC) microprocessor, very long instruction word (VLIW) microprocessor, or a processor implementing other instruction sets, or processors implementing a combination of instruction sets. Processing device 1002 may also be one or more special -purpose processing devices such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), network processor, or the like. The processing device 1002 may be configured to execute instructions 1026 for performing the operations and steps described herein.

[0105] The computer system 1000 may further include a network interface device 1008 to communicate over the network 1020. The computer system 1000 also may include a video display unit 1010 (e.g., a liquid crystal display (LCD) or a cathode ray tube (CRT)), an alphanumeric input device 1012 (e.g., a keyboard), a cursor control device 1014 (e.g., a mouse), a graphics processing unit 1022, a signal generation device 1016 (e.g., a speaker), graphics processing unit 1022, video processing unit 1028, and audio processing unit 1032.

[0106] The data storage device 1018 may include a machine-readable storage medium 1024 (also known as a non-transitory computer-readable medium) on which is stored one or more sets of instructions 1026 or software embodying any one or more of the methodologies or functions described herein. The instructions 1026 may also reside, completely or at leastDkt Ref: SNOP / 4662WO01 (159288) partially, within the main memory 1004 and / or within the processing device 1002 during execution thereof by the computer system 1000, the main memory 1004 and the processing device 1002 also constituting machine-readable storage media.

[0107] In some implementations, the instructions 1026 include instructions to implement functionality corresponding to the present disclosure. While the machine-readable storage medium 1024 is shown in an example implementation to be a single medium, the term "machine-readable storage medium" should be taken to include a single medium or multiple media (e.g., a centralized or distributed database, and / or associated caches and servers) that store the one or more sets of instructions. The term "machine-readable storage medium" shall also be taken to include any medium that is capable of storing or encoding a set of instructions for execution by the machine and that cause the machine and the processing device 1002 to perform any one or more of the methodologies of the present disclosure. The term "machine-readable storage medium" shall accordingly be taken to include, but not be limited to, solid-state memories, optical media, and magnetic media.

[0108] Some portions of the preceding detailed descriptions have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the ways used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm may be a sequence of operations leading to a desired result. The operations are those requiring physical manipulations of physical quantities. Such quantities may take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. Such signals may be referred to as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0109] It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels appliedDkt Ref: SNOP / 4662WO01 (159288)to these quantities. Unless specifically stated otherwise as apparent from the present disclosure, it is appreciated that throughout the description, certain terms refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage devices.

[0110] The present disclosure also relates to an apparatus for performing the operations herein. This apparatus may be specially constructed for the intended purposes, or it may include a computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer readable storage medium, such as, but not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magnetic-optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0111] The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various other systems may be used with programs in accordance with the teachings herein, or it may prove convenient to construct a more specialized apparatus to perform the method. In addition, the present disclosure is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages may be used to implement the teachings of the disclosure as described herein.

[0112] The present disclosure may be provided as a computer program product, or software, that may include a machine-readable medium having stored thereon instructions, which may be used to program a computer system (or other electronic devices) to perform a process according to the present disclosure. A machine-readable medium includes anyDkt Ref: SNOP / 4662WO01 (159288) mechanism for storing information in a form readable by a machine (e.g., a computer). For example, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., a computer) readable storage medium such as a read only memory (" ROM"), random access memory (" RAM"), magnetic disk storage media, optical storage media, flash memory devices, etc.

[0113] In the foregoing disclosure, implementations of the disclosure have been described with reference to specific example implementations thereof. It will be evident that various modifications may be made thereto without departing from the broader spirit and scope of implementations of the disclosure as set forth in the following claims. Where the disclosure refers to some elements in the singular tense, more than one element can be depicted in the figures and like elements are labeled with like numerals. The disclosure and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense.

Claims

Dkt Ref: SNOP / 4662WO01 (159288)THE CLAIMSWhat is claimed is:

1. A method, comprising:constructing a neural network model based on parameters for a circuit design, wherein the neural network model includes a plurality of layers each having a plurality of nodes, wherein nodes in the plurality of nodes are connected;training the neural network model to perform a function of the circuit design to provide a trained neural network model, wherein one or more of the nodes of the trained neural network model performs a Boolean function, and wherein the training includes backpropagating target functions of fanin edges of the nodes using do-not- cares; andconverting the trained neural network model to a graph, wherein internal vertices of the graph represent the Boolean function.

2. The method of claim 1, wherein the backpropagating comprises:computing the target functions of fanins of nodes of each layer of the neural network model, in a reverse order of the layers, including, for each layer other than a last layer of the neural network model, computing the target functions of the fanins of the nodes of the layer based on fanin values of nodes of a subsequent layer of the neural network model and based further on argmax fanin values of the nodes of the layer.

3. The method of claim 1, wherein the target functions indicate whether fanins of the nodes of the neural network model are to be trained toward one of -1 and +1.

4. The method of claim 1, wherein:Dkt Ref: SNOP / 4662WO01 (159288)the backpropagating further comprises determining that at least one of the fanins of a node is zero, and identifying remaining fanins of the node as do-not-care fanins; and the training further comprises exploiting the do-not-care fanins to help the neural network model converge.

5. The method of claim 1, wherein:the backpropagating further comprises determining that an output of a node of the neural network model is correct and that the output of the node is controlled by one of multiple fanins of the node; andthe training further comprises excluding remaining ones of the fanins of the node from a loss function.

6. The method of claim 1, wherein the converting comprises:converting nodes of the trained neural network model to 2-input AND-gates of corresponding vertices of the graph based on weights of the trained neural network model; andfor each node of the trained neural network model having multiple fanins, selecting one of the fanins having a largest weight as an edge of a corresponding vertex of the graph.

7. The method of claim 1, further comprising:enumerating input patterns for which the neural network model does not meet a specification of the circuit design; andapplying a Boolean patch to flip erroneous outputs of the input patterns based on Boolean difference.

8. The method of claim 7, wherein the enumerating comprises enumerating all input patterns for which the neural network model does not meet the specification of the circuit design,Dkt Ref: SNOP / 4662WO01 (159288)and wherein the method further comprises deriving the Boolean patch based on one or more of a truth-table and a Binary Decision Diagram (BDD).

9. The method of claim 1, wherein the converting comprises:converting the neural network model to an AND-inverter graph (AIG).

10. The method of claim 1, wherein:the function of the circuit design comprises a multiplier function.

11. The method of claim 1, wherein:vertices of the graph represent NAND functions.

12. The method of claim 1, further comprising:converting the graph to a netlist of cells, wherein the netlist of cells occupies less area than a netlist of the circuit design.

13. A system comprising:a memory storing instructions; anda processor, coupled with the memory and to execute the instructions, the instructions when executed cause the processor to:construct a neural network model based on parameters for a circuit design, wherein the neural network model includes a plurality of layers each having a plurality of nodes, wherein nodes in the plurality of nodes are connected; train the neural network model to perform a function of the circuit design to provide a trained neural network model, including to backpropagate target functions of fanin edges of the nodes using do-not-cares, wherein one or more of the nodes of the neural network model performs a Boolean function; andDkt Ref: SNOP / 4662WO01 (159288)convert the trained neural network model to a graph, wherein internal vertices of the graph represent the Boolean function.

14. The system of claim 13, wherein the instructions, when executed, further cause the processor to backpropagate the target functions by:computing the target functions of the fanins of nodes of each layer of the neural network model, in a reverse order of the layers, including, for each layer other than a last layer of the neural network model, computing the target functions of the fanins of the nodes of the layer based on fanin values of nodes of a subsequent layer of the neural network model and based further on argmax fanin values of the nodes of the layer.

15. The system of claim 13, wherein the instructions, when executed, further cause the processor to:backpropagate the target functions by determining that at least one of the fanins of a node is zero, and identifying remaining fanins of the node as do-not-care fanins; and train the neural network model by exploiting the not-care fanins to help the neural network model converge.

16. The system of claim 13, wherein the instructions, when executed, further cause the processor to:backpropagate the target functions by determining that an output of a node of the neural network model is correct and that the output of the node is controlled by one of multiple fanins of the node; andtrain the neural network model by excluding remaining ones of the fanins of the node from a loss function.

17. The system of claim 13, wherein the instructions, when executed, further cause the processor to convert the trained neural network model to a graph by:Dkt Ref: SNOP / 4662WO01 (159288)converting nodes of the trained neural network model to 2-input AND-gates of corresponding vertices of the graph based on weights of the trained neural network model; andfor each node of the trained neural network model having multiple fanins, selecting one of the fanins having a largest weight as an edge of a corresponding vertex of the graph.

18. The system of claim 13, wherein the instructions, when executed, further cause the processor to:enumerate input patterns for which the neural network model does not meet a specification of the circuit design; andapply a Boolean patch to flip erroneous outputs of the input patterns based on Boolean difference.

19. A non-transitory computer readable medium comprising stored instructions, which when executed by a processor, cause the processor to:construct a neural network model based on parameters for a circuit design, wherein the neural network model includes a plurality of layers each having a plurality of nodes, wherein nodes in the plurality of nodes are connected;train the neural network model to perform a function of the circuit design to provide a trained neural network model, including to backpropagate target functions of fanin edges of the nodes using do-not-cares, wherein one or more of the nodes of the neural network model performs a Boolean function; andconvert the trained neural network model to a graph, wherein internal vertices of the graph represent the Boolean function.

20. The non-transitory computer readable medium of claim 19, wherein the stored instructions, when executed by a processor, further cause the processor to:Dkt Ref: SNOP / 4662WO01 (159288) backpropagate the target functions by determining that at least one of the fanins of a node is zero, and identifying remaining fanins of the node as do-not-care fanins; and train the neural network model by exploiting the not-care fanins to help the neural network model converge.

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