Array substrate and display panel

Abstract

Provided are an array substrate and a display panel. The array substrate comprises a base, a first conductive layer, a second conductive layer and a third conductive layer, wherein the first conductive layer comprises a plurality of signal lines that are spaced apart in a first direction; the second conductive layer comprises a plurality of common electrodes; the third conductive layer comprises a plurality of pixel electrodes; the second conductive layer further comprises a first gap, which is located between at least two adjacent common electrodes in the first direction, and the orthographic projections of the signal lines on the base at least partially overlap with the orthographic projection of the first gap on the base; and the third conductive layer further comprises a shielding electrode, which is connected to a fixed voltage signal, the orthographic projection of the shielding electrode on the base at least partially overlaps with the orthographic projections of the signal lines on the base, and the orthographic projection of the shielding electrode on the base at least partially overlaps with the orthographic projection of the first gap on the base.

Description

Array substrate and display panel TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of display, and particularly relates to an array substrate and a display panel. BACKGROUND

[0002] With the continuous development of display technology, liquid crystal display (LCD) panels with touch function are widely applied in fields such as mobile phones, tablets, notebook computers and vehicle displays. The touch function in the LCD panel can be realized by dividing the common electrode into blocks. After the common electrode is divided into blocks, the capacitances at different positions of the LCD panel can be detected to locate the touch position, but the common electrode after being divided into blocks will cause crosstalk problems.

[0003] The above information disclosed in this section is only for understanding the background of the inventive concept of the present disclosure, and therefore, the above information can contain information that does not constitute the prior art. SUMMARY

[0004] In one aspect, an array substrate is provided, comprising a substrate, a first conductive layer, a second conductive layer and a third conductive layer; the first conductive layer is located on one side of the substrate, and the first conductive layer comprises a plurality of signal lines arranged at intervals along a first direction; the second conductive layer is located on a side of the first conductive layer away from the substrate, and the second conductive layer comprises a plurality of common electrodes; the third conductive layer is located on a side of the second conductive layer away from the substrate, and the third conductive layer comprises a plurality of pixel electrodes; wherein the second conductive layer further comprises a first gap, the first gap is located between at least two adjacent common electrodes in the first direction, and the orthogonal projection of the signal line on the substrate at least partially overlaps with the orthogonal projection of the first gap on the substrate; the third conductive layer further comprises a shielding electrode, the shielding electrode is connected to a fixed voltage signal, the orthogonal projection of the shielding electrode on the substrate at least partially overlaps with the orthogonal projection of the signal line on the substrate, and the orthogonal projection of the shielding electrode on the substrate at least partially overlaps with the orthogonal projection of first gap on the substrate.

[0005] According to some exemplary embodiments, the array substrate further comprises at least one first insulating layer between the second conductive layer and the third conductive layer, the at least one first insulating layer comprises a first via, and the shielding electrode is electrically connected to the common electrode through the first via.

[0006] According to some exemplary embodiments, the plurality of common electrodes comprises a first common electrode and a second common electrode, the first common electrode and the second common electrode are respectively located on two sides of the first slit in the first direction; the first common electrode comprises a first electrode main body part and a first protruding part, the second common electrode comprises a second electrode main body part and a first recess, the first protruding part protrudes from the first electrode main body part in a direction towards the second common electrode, the first recess is recessed from the second electrode main body part in a direction away from the first common electrode; and a projection of the shielding electrode on the substrate at least partially overlaps with a projection of the first protruding part on the substrate.

[0007] According to some exemplary embodiments, a projection of the first protruding part on the substrate covers a projection of the first via on the substrate.

[0008] According to some exemplary embodiments, the plurality of pixel electrodes are arranged in an array along the first direction and the second direction to form a plurality of pixel electrode rows arranged at intervals in the second direction and a plurality of pixel electrode columns arranged at intervals in the first direction, the first direction and the second direction intersect; the third conductive layer comprises a second slit extending along the first direction, the second slit is located between two adjacent pixel electrode rows; the third conductive layer comprises a plurality of third slits, the plurality of third slits are respectively located between two adjacent pixel electrode columns; and a projection of the first via on the substrate is located within a projection on the substrate of an intersection region of the second slit and the third slit.

[0009] According to some exemplary embodiments, the first slit comprises a first sub-slit and a second sub-slit, the first sub-slit is a part of the first slit located in the intersection region, the second sub-slit is a part of the first slit located between two pixel electrodes adjacent in the first direction; and a projection of the shielding electrode on the first conductive layer at least partially overlaps with a first part of the signal line, the first part of the signal line is located within a projection on the first conductive layer of the first sub-slit, and / or a projection of the shielding electrode on the first conductive layer covers a second part of the signal line, the second part of the signal line is located within a projection on the first conductive layer of the second sub-slit.

[0010] According to some exemplary embodiments, the third conductive layer comprises at least one first aperture group, the first aperture group comprises at least one third aperture; and in the region where each third aperture of the first aperture group is located, the first aperture on the substrate is at least partially overlapped with the third aperture of the first aperture group on the substrate, and the shielding electrode on the substrate is at least partially overlapped with the third aperture of the first aperture group on substrate.

[0011] According to some exemplary embodiments, the third conductive layer comprises at least one second aperture group, the second aperture group comprises at least one third aperture; and in the region where each third aperture of the second aperture group is located, the common electrode on the substrate is at least partially overlapped with the signal line on the substrate; and / or, the first aperture on the substrate and the third aperture of the second aperture group on the substrate are arranged in the first direction, and the shielding electrode on the substrate and the third aperture of the second aperture group on the substrate are arranged in the first direction.

[0012] According to some exemplary embodiments, the third conductive layer comprises at least one third aperture group, the third aperture group comprises at least one third aperture; and in the region where each third aperture of the third aperture group is located, the common electrode on the substrate is at least partially overlapped with the signal line on the substrate; and / or, the first aperture on the substrate and the third aperture of the third aperture group on the substrate are arranged in the first direction, and the shielding electrode on the substrate and the third aperture of the third aperture group on the substrate are at least partially overlapped.

[0013] According to some exemplary embodiments, the third conductive layer comprises a plurality of shielding electrodes, and a plurality of pixel electrode columns and a plurality of shielding electrodes are arranged alternately in the first direction.

[0014] According to some exemplary embodiments, in the first direction, at least one shielding electrode is arranged every at least one pixel electrode column; and / or, in the first direction, at least one first aperture is arranged every at least one pixel electrode column.

[0015] According to some exemplary embodiments, the plurality of pixel electrodes comprises a first pixel electrode and a second pixel electrode, the first pixel electrode and the second pixel electrode are located in adjacent pixel electrode rows respectively, the first pixel electrode extends along a third direction, the second pixel electrode extends along a fourth direction, the third direction intersects the first direction and the second direction respectively, and the fourth direction intersects the first direction, the second direction and the third direction respectively; a portion of the shielding electrode adjacent to the first pixel electrode extends along the third direction, and a portion of the shielding electrode adjacent to the second pixel electrode extends along the fourth direction; or, the pixel electrode comprises a first electrode portion, a second electrode portion and a connecting portion, the first electrode portion extends along a third direction, the second electrode portion extends along a fourth direction, the third direction intersects the fourth direction, and the connecting portion is used to connect the first electrode portion and the second electrode portion; a portion of the shielding electrode adjacent to the first electrode portion extends along the third direction, a portion of the shielding electrode adjacent to the second electrode portion extends along the fourth direction, and in the first direction, a portion of the shielding electrode adjacent to the connecting portion protrudes towards the same side as the connecting portion.

[0016] According to some exemplary embodiments, in the first direction, the spacing between the shielding electrode and two adjacent pixel electrodes is equal.

[0017] According to some exemplary embodiments, the pixel electrode comprises a pixel electrode main portion and a second protruding portion, the shielding electrode comprises a shielding electrode main portion and a second recess, the second protruding portion protrudes from the pixel electrode main portion in a direction towards the shielding electrode, the second recess is recessed from the shielding electrode main portion in a direction away from the second protruding portion; and the protruding directions of the second protruding portions in the same pixel electrode row are the same, and the protruding directions of the second protruding portions in two adjacent pixel electrode rows are opposite.

[0018] According to some exemplary embodiments, the common electrode is multiplexed as a touch electrode; the first conductive layer further comprises a plurality of touch wires arranged at intervals along the first direction, the touch wires are electrically connected with the common electrode; and the orthogonal projection of the touch wire on the substrate at least partially overlaps with the orthogonal projection of the pixel electrode on the substrate, or the orthogonal projection of the touch wire on the substrate at least partially overlaps with the orthogonal projection of shielding electrode on the substrate.

[0019] According to some exemplary embodiments, the common electrode is multiplexed as a touch electrode; the array substrate further comprises a fourth conductive layer, the fourth conductive layer is located between the first conductive layer and the second conductive layer, the fourth conductive layer comprises a plurality of touch wires arranged at intervals along the first direction, the touch wires are electrically connected with the common electrode; and a projection of the touch wire on the substrate at least partially overlaps with a projection of the signal line on the substrate; and / or, a projection of the touch wire on the substrate at least partially overlaps with a projection of the shielding electrode on the substrate; and / or, a projection of the touch wire on the substrate at least partially overlaps with a projection of the first gap on the substrate.

[0020] According to some exemplary embodiments, the array substrate comprises a first insulating layer and a second insulating layer, the first insulating layer is located between the second conductive layer and the third conductive layer, the second insulating layer is located between the second conductive layer and the fourth conductive layer; the array substrate comprises a first via and a second via, the first via penetrates through the first insulating layer, the second via penetrates through the first insulating layer and the second insulating layer; and the shielding electrode is electrically connected with the common electrode through the first via, and the shielding electrode is electrically connected with the touch wire through the second via.

[0021] In another aspect, a display panel is provided, comprising the array substrate as described above. BRIEF DESCRIPTION OF DRAWINGS

[0022] Other objects and advantages of the present disclosure will be apparent to those skilled in the art from the following description of the present disclosure, which is to be taken in conjunction with the appended drawings.

[0023] FIG. 1 is a schematic diagram of a partial structure of an array substrate in the related art.

[0024] FIG. 2 is an enlarged view of the P1 region in FIG. 1.

[0025] FIG. 3 is a schematic diagram of a principle of generating crosstalk in the related art.

[0026] FIG. 4 is a schematic diagram of a partial structure of an array substrate according to some embodiments of the present disclosure.

[0027] FIG. 5 is an enlarged view of the P2 region in FIG. 4.

[0028] FIG. 6 is a schematic diagram of a principle of improving crosstalk in embodiments of the present disclosure.

[0029] FIG. 7 is a schematic diagram of a film layer stack of an array substrate according to some embodiments of the present disclosure.

[0030] Figure 8 is a partial structural schematic diagram of the first common electrode and the second common electrode according to some embodiments of the present disclosure.

[0031] Figure 9 is a schematic diagram of the distribution area of ​​the first sub-gap and the second sub-gap according to some embodiments of the present disclosure.

[0032] Figure 10 is a schematic diagram of the distribution area of ​​the third gap according to some embodiments of the present disclosure.

[0033] Figure 11 is a partial structural schematic diagram of an array substrate according to some embodiments of the present disclosure.

[0034] Figure 12 is a partial structural schematic diagram of an array substrate according to some embodiments of the present disclosure.

[0035] Figure 13 is a partial structural schematic diagram of an array substrate according to some embodiments of the present disclosure.

[0036] Figure 14 is a partial structural schematic diagram of an array substrate according to some embodiments of the present disclosure.

[0037] Figure 15 is an enlarged view of region P3 in Figure 14.

[0038] Figure 16 is a partial structural schematic diagram of an array substrate according to some embodiments of the present disclosure.

[0039] Figure 17 is an enlarged view of region P4 in Figure 16.

[0040] Figure 18 is a partial structural schematic diagram of an array substrate according to some embodiments of the present disclosure.

[0041] Figure 19 is an enlarged view of region P5 in Figure 18.

[0042] Figure 20 is a cross-sectional view along the A-A' direction in Figure 19.

[0043] Figure 21 is a schematic diagram of film layer stacking of an array substrate according to some embodiments of the present disclosure. Detailed Implementation

[0044] In the following description, numerous specific details are set forth for illustrative purposes to provide a comprehensive understanding of various exemplary embodiments. However, it will be apparent that various exemplary embodiments may be implemented without these specific details or with one or more equivalent arrangements. Furthermore, the various exemplary embodiments may be different, but not necessarily exclusive. For example, specific shapes, configurations, and characteristics of exemplary embodiments may be used or implemented in another exemplary embodiment without departing from the inventive concept.

[0045] In the drawings, the size and relative sizes of the elements and the relative sizes of the regions can be exaggerated for clarity and / or descriptive purposes. As such, the sizes and relative sizes of the various elements in the drawings can not be to scale. Also, like reference numerals designate like elements throughout the specification.

[0046] When an element is described as being "on" another element, "connected to" another element, or "coupled to" another element, it can be directly on, directly connected to, or directly coupled to the other element or intervening elements can be present. However, when an element is described as being "directly on," "directly connected to," or "directly coupled to" another element, there are no intervening elements present. Other terms and / or expressions used herein to describe relationships between elements should be construed in a like fashion, e.g., "between," "directly between," "adjacent," "directly adjacent," or "on" versus "directly on" and the like.

[0047] It will be understood that, although the terms first, second, etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of example embodiments.

[0048] FIG. 1 is a schematic diagram of a partial structure of an array substrate in the related art. FIG. 2 is an enlarged view of a P1 region in FIG. 1. FIG. 3 is a schematic diagram of a principle of generating crosstalk in the related art.

[0049] Referring to FIGS. 1 to 3, in the related art, the array substrate includes a substrate, a first conductive layer 20, a second conductive layer 30, and a third conductive layer 40. The first conductive layer 20 includes a plurality of signal lines 201 (e.g., data lines Data for transmitting data signals) disposed at intervals along a first direction X1, the second conductive layer 30 includes a plurality of common electrodes 301, and the third conductive layer 40 includes a plurality of pixel electrodes 401. A liquid crystal molecule can be driven to deflect by controlling a horizontal electric field formed between the pixel electrode 401 and the common electrode 301, to achieve a display effect of different gray scales. The second conductive layer 30 further includes a first slit S1 between at least two adjacent common electrodes 301 in the first direction X1, and a normal projection of the signal line 201 on the substrate at least partially overlaps a normal projection of the first slit S1 on the substrate, i.e., there is a signal line 201 in a region where the first slit S1 between the adjacent two common electrodes 301 is located (as shown in FIG. 2).

[0050] It should be noted that in the field of flat panel display, cross talk refers to a display abnormal phenomenon that the display of a certain area of the screen is affected by another area, causing picture distortion. The causes of cross talk include capacitive coupling. For example, as shown in FIG. 3, due to the capacitive coupling between the signal line 201 and the pixel electrode 401 (for example, there is an electric field directed from the signal line 201 to the pixel electrode 401), when the voltage on the signal line 201 changes, it will affect the voltage of the pixel electrode 401, making the actual voltage of the pixel electrode 401 different from the set voltage, thereby causing brightness deviation (i.e. cross talk). Therefore, in order to solve at least one aspect of the above technical problem, the embodiments of the present disclosure provide an array substrate and a display panel, which are beneficial to improve the cross talk problem between the signal line 201 and the pixel electrode 401.

[0051] In some embodiments, as shown in FIG. 3, the pixel electrode 401 is also provided with a color film layer 2 away from one side of the common electrode 301, and the color film layer 2 can include a first filter part 21 and a second filter part 22 to realize color display. Among them, the first filter part 21 is a blue light filter part for example, and the second filter part 22 is a red light filter part for example. The color film layer 2 can also include a green light filter part.

[0052] FIG. 4 is a schematic diagram of a partial structure of an array substrate according to some embodiments of the present disclosure. FIG. 5 is an enlarged view of the P2 area in FIG. 4. FIG. 6 is a schematic diagram of the principle of improving cross talk in embodiments of the present disclosure. FIG. 7 is a schematic diagram of the film layer stack of an array substrate according to some embodiments of the present disclosure. FIG. 8 is a schematic diagram of the partial structure of the first common electrode 31 and the second common electrode 32 according to some embodiments of the present disclosure. FIG. 9 is a schematic diagram of the distribution area of the first sub-slit S11 and the second sub-slit S12 according to some embodiments of the present disclosure. FIG. 10 is a schematic diagram of the distribution area of the third slit S3 according to some embodiments of the present disclosure.

[0053] Referring to FIGS. 4-10, the array substrate includes a substrate 10 (see FIG. 7), a first conductive layer 20, a second conductive layer 30, and a third conductive layer 40. The first conductive layer 20 is located on a side of the substrate 10, and includes a plurality of signal lines 201 (e.g., data lines Data for transmitting data signals) arranged at intervals along a first direction X1. The second conductive layer 30 is located on a side of the first conductive layer 20 away from the substrate 10, and includes a plurality of common electrodes 301. The third conductive layer 40 is located on a side of the second conductive layer 30 away from the substrate 10, and includes a plurality of pixel electrodes 401. The second conductive layer 30 further includes a first slit S1 between at least two adjacent common electrodes 301 in the first direction X1, and a normal projection of the signal line 201 on the substrate 10 at least partially overlaps a normal projection of the first slit S1 on the substrate 10, i.e., the signal line 201 is located in a region of the first slit S1 between the two adjacent common electrodes 301 (as shown in FIG. 5). The third conductive layer 40 further includes a shielding electrode 402, i.e., the shielding electrode 402 is arranged in the same layer as the pixel electrode 401. The shielding electrode 402 is connected to a fixed voltage signal (e.g., ground voltage GND), a normal projection of the shielding electrode 402 on the substrate 10 at least partially overlaps a normal projection of the signal line 201 on the substrate 10, and a normal projection of the shielding electrode 402 on the substrate 10 at least partially overlaps a

[0054] It should be noted that, in the present embodiment, by dividing the second conductive layer 30 into a plurality of common electrode blocks, the common electrodes 301 can be multiplexed as touch electrodes to realize touch functions in multiple regions, thereby reducing the thickness of the panel and improving the integration of display and touch functions. Specifically, in the display phase, the common electrodes 301 receive a display voltage signal (e.g., a reference voltage VCOM); in the touch phase, the common electrodes 301 are used as touch electrodes to receive a touch voltage signal, and by detecting the change in capacitance between the common electrodes 301 and GND when a finger or a stylus touches and when there is no touch, the touch position is identified.

[0055] In some embodiments of the present disclosure, as shown in FIG. 4, the first conductive layer 20 further includes a plurality of touch wires 202 arranged at intervals along the first direction X1, i.e., the touch wires 202 can be arranged in the same layer as the signal lines 201. The touch wires 202 are electrically connected to the common electrodes 301, i.e., the plurality of common electrodes 301 are respectively electrically connected to the driving chip through the touch wires 202. A normal projection of the touch wire 202 on the substrate 10 at least partially overlaps a normal projection of the pixel electrode 401 on the substrate 10, i.e., the touch wire 202 can be arranged in a pixel opening region (i.e., a region of the pixel electrode 401).

[0056] In some embodiments of the present disclosure, as shown in FIG. 4, the first conductive layer 20 further comprises a source / drain 203, i.e., the source / drain 203 is arranged in the same layer as the signal line 201. The pixel electrode 401 is electrically connected to the source / drain 203 through a connection hole 2031 (refer to FIG. 7), so that the pixel electrode 401 is provided with a driving voltage through the source / drain 203.

[0057] It can be understood that, in the present embodiment, by arranging the shielding electrode 402 and connecting the shielding electrode 402 to a fixed voltage signal, the coupling electric field between the signal line 201 and the pixel electrode 401 can be interrupted. Specifically, as shown in FIG. 6, after the shielding electrode 402 is added, an electric field of the signal line 201 pointing to the shielding electrode 402 and an electric field of the pixel electrode 401 pointing to the shielding electrode 402 can be formed respectively, so that the electric field formed between the pixel electrode 401 and the shielding electrode 402 is not affected by the signal line 201, and thus the crosstalk problem between the signal line 201 and the pixel electrode 401 can be improved, and the electric field formed between the pixel electrode 401 and the shielding electrode 402 can also enhance the horizontal electric field formed between the pixel electrode 401 and the common electrode 301.

[0058] In some embodiments of the present disclosure, the array substrate further comprises at least one first insulating layer 50 (refer to FIG. 7) between the second conductive layer 30 and the third conductive layer 40, and the at least one first insulating layer 50 comprises a first via hole 501 (refer to FIG. 5), and the shielding electrode 402 is electrically connected to the common electrode 301 through the first via hole 501. That is, the shielding electrode 402 is connected to the voltage of the common electrode 301, and thus the fixed voltage signal does not need to be introduced additionally.

[0059] In some embodiments of the present disclosure, referring to FIGS. 4, 5 and 8, the plurality of common electrodes 301 comprises a first common electrode 31 and a second common electrode 32, and the first common electrode 31 and the second common electrode 32 are respectively located on two sides of the first slit S1 in the first direction X1. Specifically, in FIG. 5, the first common electrode 31 is located on the left side of the first slit S1, and the second common electrode 32 is located on the right side of the first slit S1; in FIG. 8, the first common electrode 31 is located on the right side of the first slit S1, and the second common electrode 32 is located on the left side of the first slit S1. The first common electrode 31 comprises a first electrode main body part 311 and a first protruding part 312, and the second common electrode 32 comprises a second electrode main body part 321 and a first recess 322, the first protruding part 312 protrudes from the first electrode main body part 311 in a direction towards the second common electrode 32, and the first recess 322 is recessed from the second electrode main body part 321 in a direction away from the first common electrode 31. The orthogonal projection of the shielding electrode 402 on the substrate 10 at least partially overlaps the orthogonal projection of the first protruding part 312 on the substrate 10.

[0060] It can be understood that, in the embodiment, by causing the first common electrode 31 to include the first protruding portion 312 and causing the second common electrode 32 to include the first recess 322 (i.e., the avoiding structure corresponding to the first protruding portion 312), the shielding electrode 402 located above the signal line 201 in the region where the first gap S1 is located can be electrically connected to the first protruding portion 312 through the first via 501, so that the shielding electrode 402 is connected to the voltage of the common electrode 301. In some embodiments of the present disclosure, the orthogonal projection of the first protruding portion 312 on the substrate 10 covers the orthogonal projection of the first via 501 on the substrate 10. That is, the first via 501 specifically refers to the via located in the region of the first protruding portion 312 and connecting the first protruding portion 312 and the shielding electrode 402.

[0061] It should be noted that, in the first direction X1, the width of the first gap S1 can be less than the width of the signal line 201, or can be greater than or equal to the width of the signal line 201. In FIGS. 5 and 8, the width of the first gap S1 is less than the width of the signal line 201 as an example.

[0062] In some embodiments of the present disclosure, referring to FIGS. 4, 5 and 8, the plurality of pixel electrodes 401 are arranged in the first direction X1 and the second direction X2 to form a plurality of pixel electrode rows H1 spaced in the second direction X2 and a plurality of pixel electrode columns L1 spaced in the first direction X1, and the first direction X1 and the second direction X2 intersect. The third conductive layer 40 includes a second gap S2 extending in the first direction X1, and the second gap S2 is located between two adjacent pixel electrode rows H1. The third conductive layer 40 includes a plurality of third gaps S3, and each of the plurality of third gaps S3 is located between two adjacent pixel electrode columns L1. The orthogonal projection of the first via 501 on the substrate 10 is located in the orthogonal projection on the substrate 10 of the intersection region of the second gap S2 and the third gap S3. That is, the first via 501 can be located at the gap (i.e., the top corner of the pixel electrode 401) between the four pixel electrodes 401 of the adjacent two rows and two columns, and the gap at this position is larger than the gap between the adjacent two pixel electrodes 401, so that a first via 501 with a larger size can be formed or a plurality of first vias 501 can be formed to realize the electrical connection between the shielding electrode 402 and the common electrode 301. In other embodiments, the first via 501 can also be arranged at the gap (i.e., the edge of the pixel electrode 401) between the two adjacent pixel electrodes 401 in the first direction X1, and the embodiments of the present disclosure are not limited thereto.

[0063] It should be noted that only 1 common electrode 301 corresponding to 2 rows of 3 columns of pixel electrodes 401 (i.e. 6 pixel electrodes 401) is illustrated in FIG. 4 as an example. Further, 1 common electrode 301 can correspond to n rows of m columns of pixel electrodes 401 (i.e. n*m pixel electrodes 401), n and m are positive integers. When n is greater than or equal to 2, in the region between two adjacent common electrodes 301 in the first direction X1, one shielding electrode 402 or a plurality of shielding electrodes 402 arranged along the direction of the pixel electrode column L1 can be arranged. That is, one column of pixel electrodes 401 in the region of one common electrode 301 can correspond to one shielding electrode 402 with a long extension distance (for example, the extension distance is y1), or a plurality of shielding electrodes 402 with a short extension distance (for example, the extension distance is y2, y2

[0064] Referring to FIG. 7, in some embodiments of the present disclosure, the array substrate further comprises a light shielding metal layer 11, a buffer layer 12, an active layer 13, a gate insulating layer 14, a fifth conductive layer 15, an interlayer insulating layer 16, a planarization layer 17 and an alignment layer 18. The light shielding metal layer 11 is located between the substrate 10 and the first conductive layer 20, and is used to shield light for the channel region of the active layer 13. The buffer layer 12 is located between the light shielding metal layer 11 and the first conductive layer 20. The active layer 13 is located between the buffer layer 12 and the first conductive layer 20, and the active layer 13 comprises a first pole contact region, a second pole contact region and a channel region located between the first pole contact region and the second pole contact region. The active layer 13 further comprises a first shallow doped region located between the channel region and the first pole contact region, and a second shallow doped region located between the channel region and the second pole contact region. The material of the active layer 13 can be polysilicon. The gate insulating layer 14 is located between the active layer 13 and the first conductive layer 20. The fifth conductive layer 15 is located between the gate insulating layer 14 and the first conductive layer 20, and the fifth conductive layer 15 comprises a first gate 151 and a second gate 152, that is, the array substrate comprises two series-connected thin film transistors. The thin film transistor close to the left side (for example, the first thin film transistor) comprises the first gate 151, and the thin film transistor close to the right side (for example, the second thin film transistor) comprises the second gate 152. The first pole contact region of the first thin film transistor is electrically connected with the signal line 201 through a via, the second pole contact region of the first thin film transistor is connected with the first pole contact region of the second thin film transistor, and the second pole contact region of the second thin film transistor is electrically connected with the source / drain 203 through a via.

[0065] In some embodiments, the second electrode contact region of the second thin-film transistor, for example, the drain contact region, can be provided with a second shallow doped region between the channel region and the drain contact region, so as to reduce the electric field intensity between the drain and the source, and avoid the drain induced barrier lowering (DIBL) effect.

[0066] With continued reference to FIG. 7, the interlayer insulating layer 16 is located between the fifth conductive layer 15 and the first conductive layer 20. The planarization layer 17 is located between the first conductive layer 20 and the second conductive layer 30. The alignment layer 18 is located on the side of the third conductive layer 40 away from the substrate 10, and can be a polyimide film (PI film) for guiding the liquid crystal molecules to arrange in a specific direction, so as to achieve the ordered rotation and orientation effect of the liquid crystal material.

[0067] With reference to FIGS. 4 and 9, in some embodiments of the present disclosure, the first slit S1 includes a first sub-slit S11 and a second sub-slit S12. The first sub-slit S11 is the portion of the first slit S1 located in the intersection region of the second slit S2 and the third slit S3 (i.e., at the top corner of the pixel electrode 401), and the second sub-slit S12 is the portion of the first slit S1 located between two adjacent pixel electrodes 401 in the first direction X1 (i.e., at the edge of the pixel electrode 401). The orthogonal projection of the shielding electrode 402 on the first conductive layer 20 at least partially overlaps the first portion of the signal line 201, and the first portion of the signal line 201 is located within the orthogonal projection of the first sub-slit S11 on the first conductive layer 20, i.e., within the region where the first sub-slit S11 is located, and the shielding electrode 402 at least covers part of the signal line 201; and / or, the orthogonal projection of the shielding electrode 402 on the first conductive layer 20 covers the second portion of the signal line 201, and the second portion of the signal line 201 is located within the orthogonal projection of the second sub-slit S12 on the first conductive layer 20, i.e., within the region where the second sub-slit S12 is located, and the shielding electrode 402 covers the entire signal line 201.

[0068] It can be understood that, since the signal line 201 located in the region of the first sub-slit S11 does not affect the light emission, in the region of the first sub-slit S11, the shielding electrode 402 can only cover part of the signal line 201, or can also cover all the signal lines 201. However, the signal line 201 located in the region of the second sub-slit S12 will cause crosstalk with the pixel electrode 401, so in the region of the second sub-slit S12, the shielding electrode 402 needs to cover all the signal lines 201, so as to reduce the capacitive coupling between the signal line 201 and the pixel electrode 401, and reduce the risk of crosstalk.

[0069] Referring to FIGS. 4 and 10, in some embodiments of the present disclosure, the orthogonal projections of the plurality of signal lines 201 on the substrate 10 at least partially overlap with the orthogonal projections of the plurality of third slits S3 on the substrate 10, i.e., the signal lines 201 are located in the region between two adjacent pixel electrode columns L1 in the first direction X1. The third conductive layer 40 includes at least one first slit group G1 (as shown in FIG. 10), and the first slit group G1 includes at least one third slit S3. In the region of each third slit S3 of the first slit group G1, the orthogonal projection of the first slit S1 on the substrate 10 at least partially overlaps with the orthogonal projection of the third slit S3 in the first slit group G1 on the substrate 10, and the orthogonal projection of the shielding electrode 402 on the substrate 10 at least partially overlaps with the orthogonal projection of the third slit S3 of the first slit group G1 on the substrate 10, i.e., the third slits S3 that overlap with the orthogonal projection of the first slit S1 on the third conductive layer 40 form the first slit group G1, and the orthogonal projection of the third slit S3 in the first slit group G1 on the substrate

[0070] Continuing to refer to FIGS. 4 and 10, in some embodiments of the present disclosure, the third conductive layer 40 includes at least one second slit group G2, and the second slit group G2 includes at least one third slit S3. In the region of each third slit S3 of a second slit group G2, the orthogonal projection of the common electrode 301 on the substrate 10 at least partially overlaps with the orthogonal projection of the signal line 201 on the substrate 10, i.e., the third slits S3 that overlap with the signal lines 201 in the region of one common electrode 301 form the second slit group G2; and / or, the orthogonal projection of the first slit S1 on the substrate 10 and the orthogonal projection of the third slit S3 in the second slit group G2 on the substrate 10 are arranged in the first direction X1, and the orthogonal projection of the shielding electrode 402 on the substrate 10 and the orthogonal projection of the third slit S3 in the second slit

[0071] With reference back to FIG. 4, in some embodiments of the present disclosure, the plurality of pixel electrodes 401 includes a first pixel electrode 41 and a second pixel electrode 42, the first pixel electrode 41 and the second pixel electrode 42 are located in adjacent pixel electrode rows H1 respectively, the first pixel electrode 41 extends along a third direction X3, the second pixel electrode 42 extends along a fourth direction X4, the third direction X3 intersects the first direction X1 and the second direction X2 respectively, the fourth direction X4 intersects the first direction X1, the second direction X2 and the third direction X3 respectively; a portion of the shielding electrode 402 adjacent to the first pixel electrode 41 extends along the third direction X3, a portion of the shielding electrode 402 adjacent to the second pixel electrode 42 extends along the fourth direction X4.

[0072] FIG. 11 is a schematic diagram of a partial structure of an array substrate according to some embodiments of the present disclosure.

[0073] With reference to FIG. 11, in some embodiments of the present disclosure, the third conductive layer 40 includes at least one third slit group G3, the third slit group G3 includes at least one third slit S3. In the area where each third slit S3 of the third slit group G3 is located, the orthographic projection of the common electrode 301 on the substrate 10 at least partially overlaps the orthographic projection of the signal line 201 on the substrate 10, i.e. the third slit S3 which has an overlap with the orthographic projection of the signal line 201 on the third conductive layer 40 in the area where one common electrode 301 is located constitutes the third slit group G3; and / or, the orthographic projection of the first slit S1 on the substrate 10 and the orthographic projection of the third slit S3 in the third slit group G3 on the substrate 10 are arranged in the first direction X1 with a spacing, the orthographic projection of the shielding electrode 402 on the substrate 10 and the orthographic projection of the third slit S3 in the third slit group G3 on the substrate 10 at least partially overlap, i.e. the shielding electrode 402 is arranged in the area where the third slit S3 in the third slit group G3 is located.

[0074] It should be noted that, in combination with referring to FIG. 4 and FIG. 11, the three pixel electrodes 401 arranged in sequence along the first direction X1 correspond to three sub-pixels, for example, a red sub-pixel, a green sub-pixel and a blue sub-pixel respectively. The red sub-pixel, the green sub-pixel and the blue sub-pixel combine to form a pixel, and the two pixels above and below share one common electrode 301. The embodiments of the present disclosure are not limited thereto. In FIG. 4, the shielding electrode 402 is only arranged between the adjacent pixels in the first direction X1, specifically, between the red sub-pixel and the blue sub-pixel. Compared with FIG. 11, the number of shielding electrodes 402 is reduced, the transmittance is greater, and the risk of short circuit or open circuit of the shielding electrode 402 is also reduced. In FIG. 11, the shielding electrode 402 is arranged between the adjacent sub-pixels in the first direction X1. Compared with FIG. 4, it can avoid that the shielding electrode 402 is only arranged between the red sub-pixel and the blue sub-pixel, and avoid that the luminous brightness between the sub-pixels is different due to the size difference between the conductive part of the red sub-pixel and the blue sub-pixel region and the conductive part of the green sub-pixel region.

[0075] It should be noted that, in FIG. 11, the third gap group G3 is illustrated by taking an example of including two third gaps S3. In other embodiments, the third gap group G3 can also include only one third gap S3, that is, the third gap group G3 includes only the third gap S3 located between the adjacent red sub-pixel and green sub-pixel in the first direction X1 or between the adjacent green sub-pixel and blue sub-pixel in the first direction X1. Compared with the structure of FIG. 4, the luminance uniformity is better. Compared with the structure of FIG. 11, the transmittance is greater.

[0076] It should be noted that the shielding electrode 402 located between the two common electrodes 301 adjacent in the first direction X1 is electrically connected to the first protruding part 312 of the first common electrode 31 through the first via hole 501 (as shown in FIG. 5), and the shielding electrode 402 located in the region of the common electrode 301 is directly electrically connected to the first electrode main part 311 or the second electrode main part 321 through the via hole on the first insulating layer 50 (as shown in FIG. 11).

[0077] In some embodiments of the present disclosure, in the first direction X1, at least one shielding electrode 402 is arranged every interval of at least one pixel electrode column L1. For example, as shown in FIG. 11, the third conductive layer 40 includes a plurality of shielding electrodes 402, and the plurality of shielding electrodes 402 and the plurality of pixel electrode columns L1 are arranged alternately in the first direction X1, that is, at least one shielding electrode 402 is arranged every interval of one pixel electrode column L1. The embodiments of the present disclosure are not limited thereto.

[0078] FIG. 12 is a schematic diagram of a partial structure of an array substrate according to some embodiments of the present disclosure.

[0079] With reference to FIGS. 11 and 12, in some embodiments of the present disclosure, a first slit S1 is arranged every at least one pixel electrode column L1 in the first direction X1. Specifically, as shown in FIG. 11, a first slit S1 is arranged every three pixel electrode columns L1; as shown in FIG. 12, a first slit S1 is arranged every one pixel electrode column L1. That is, six sub-pixels in FIG. 11 share one common electrode 301, and two sub-pixels in FIG. 12 share one common electrode 301.

[0080] It can be understood that the common electrode blocks of the second conductive layer 30 in FIG. 11 are less than those in FIG. 12, and thus fewer touch wires 202 can be arranged. In FIG. 12, a first slit S1 is further arranged between every two adjacent sub-pixels in the first direction X1, so that the surrounding environment of each sub-pixel is completely the same and completely symmetrical, further improving the brightness uniformity between the sub-pixels, and reducing the crosstalk degree and other differences in electrical or optical characteristics between different sub-pixels.

[0081] FIG. 13 is a schematic diagram of a partial structure of an array substrate according to some embodiments of the present disclosure.

[0082] With reference to FIG. 13, the pixel electrode 401 includes a first electrode part 4011, a second electrode part 4012, and a connecting part 4013, the first electrode part 4011 extends along a third direction X3, the second electrode part 4012 extends along a fourth direction X4, the third direction X3 intersects the fourth direction X4, and the connecting part 4013 is used to connect the first electrode part 4011 and the second electrode part 4012. The part of the shielding electrode 402 adjacent to the first electrode part 4011 extends along the third direction X3, and the part of the shielding electrode 402 adjacent to the second electrode part 4012 extends along the fourth direction X4. In the first direction X1, the part of the shielding electrode 402 adjacent to the connecting part 4013 protrudes to the same side as the connecting part 4013. For example, as shown in FIG. 13, the part of the shielding electrode 402 adjacent to the connecting part 4013 and the connecting part 4013 both protrude to the left side (i.e., the opposite direction of the first direction X1), and in other embodiments, the part of the shielding electrode 402 adjacent to the connecting part 4013 and the connecting part 4013 both protrude to the right side (i.e., the first direction X1).

[0083] It should be noted that the third direction X3 and the fourth direction X4 have a preset included angle, and the preset included angle is configured to enable the first electrode part 4011 and the common electrode 301 to form a first domain electric field, and the second electrode part 4012 and the common electrode 301 to form a second domain electric field, and the directions of the first domain electric field and the second domain electric field are different. In embodiments of the present disclosure, the preset included angle can be determined according to actual needs, which is not limited herein.

[0084] It can be understood that, in the embodiments of the present disclosure, by arranging the connecting portion 4013 between the first electrode portion 4011 and the second electrode portion 4012, the pixel electrode 401 can be better bent, and the electrical performance at the bending position of the pixel electrode 401 can be avoided from being affected.

[0085] In some embodiments of the present disclosure, in the first direction X1, the distance between the shielding electrode 402 and the two adjacent pixel electrodes 401 is equal. For example, as shown in FIG. 13, the distance d1 between the shielding electrode 402 and the pixel electrode 401 on the left side (i.e., the pixel electrode 401 adjacent in the opposite direction of the first direction X1) is equal to the distance d2 between the shielding electrode 402 and the pixel electrode 401 on the right side (i.e., the pixel electrode 401 adjacent in the first direction X1).

[0086] FIG. 14 is a schematic diagram of a partial structure of an array substrate according to some embodiments of the present disclosure. FIG. 15 is an enlarged view of the P3 region in FIG. 14.

[0087] Referring to FIGS. 14 and 15, in some embodiments of the present disclosure, the pixel electrode 401 includes a pixel electrode main portion 431 and a second protruding portion 432, and the shielding electrode 402 includes a shielding electrode main portion 4021 and a second recess 4022 (i.e., a structure for avoiding the second protruding portion 432), the second protruding portion 432 protrudes from the pixel electrode main portion 431 in a direction toward the shielding electrode 402, and the second recess 4022 is recessed from the shielding electrode main portion 4021 in a direction away from the second protruding portion 432. The protruding directions of the second protruding portions 432 in the same pixel electrode row H1 are the same, and the protruding directions of the second protruding portions 432 in the two adjacent pixel electrode rows H1 are opposite, and the embodiments of the present disclosure are not limited thereto.

[0088] It should be noted that, in the related art, the phenomenon of uneven brightness on the LCD panel caused by pressing or sliding is called Trace Mura, which is manifested as a dark trace left at the pressing position. The main principle of its generation is that the liquid crystal molecules are deformed when pressed or slid under high gray voltage, resulting in uneven arrangement of the liquid crystal molecules, thereby forming uneven brightness traces on the LCD panel. In the present embodiment, by arranging the pixel electrode 401 to include the second protruding portion 432, the size of the transverse electric field weakening region between the pixel electrode 401 and the common electrode 301 is effectively reduced, the orientation ability of the liquid crystal molecules to the transverse electric field is strengthened, the electric field distribution in the pixel opening region can be made more orderly, which is conducive to improving the Trace Mura and improving the display effect of the LCD panel.

[0089] In some embodiments, the spacing between the second protrusion 432 and the shielding electrode 402 in the first direction X1 is greater than or equal to 2 microns and less than or equal to 3 microns, which can avoid short circuit between the second protrusion 432 and the shielding electrode 402. In some embodiments, the width of the portion of the shielding electrode 402 in which the second groove 4022 is arranged in the first direction X1 is greater than or equal to 2 microns and less than or equal to 3 microns, which can avoid open circuit of the shielding electrode 402. In the present embodiment, the portion of the shielding electrode 402 in which the second groove 4022 is not arranged can be electrically connected to the common electrode 301 through the first via 501, so as to realize the capacitive coupling between the shielding signal line 201 and the pixel electrode 401 in the case of avoiding the second protrusion 432 of the pixel electrode 401.

[0090] FIG. 16 is a schematic diagram of a partial structure of an array substrate according to some embodiments of the present disclosure. FIG. 17 is an enlarged view of a P4 region in FIG. 16.

[0091] Referring to FIGS. 16 and 17, in some embodiments of the present disclosure, the common electrode 301 is multiplexed as a touch electrode. The first conductive layer 20 further includes a plurality of touch wires 202 arranged at intervals in the first direction X1, i.e., the touch wires 202 can be arranged in the same layer as the signal lines 201. The touch wires 202 are electrically connected to the common electrodes 301, i.e., the plurality of common electrodes 301 are respectively electrically connected to the driving chip through the touch wires 202. The orthogonal projection of the touch wire 202 on the substrate 10 at least partially overlaps the orthogonal projection of the shielding electrode 402 on the substrate 10, i.e., the touch wire 202 can be arranged in the region between two adjacent pixel electrodes 401 in the first direction X1.

[0092] FIG. 18 is a schematic diagram of a partial structure of an array substrate according to some embodiments of the present disclosure. FIG. 19 is an enlarged view of a P5 region in FIG. 18. FIG. 20 is a cross-sectional view along the A-A’ direction in FIG. 19. FIG. 21 is a schematic diagram of a film layer stack of an array substrate according to some embodiments of the present disclosure.

[0093] Referring to FIGS. 18 to 21, in some embodiments of the present disclosure, the common electrode 301 is multiplexed as a touch electrode. The array substrate further includes a fourth conductive layer 60 located between the first conductive layer 20 and the second conductive layer 30, and the fourth conductive layer 60 includes a plurality of touch wires 202 arranged at intervals in the first direction X1, and the touch wires 202 are electrically connected to the common electrodes 301. The orthogonal projection of the touch wire 202 on the substrate 10 at least partially overlaps the orthogonal projection of the signal line 201 on the substrate 10; and / or, the orthogonal projection of the touch wire 202 on the substrate 10 at least partially overlaps the orthogonal projection of the shielding electrode 402 on the substrate 10; and / or, the orthogonal projection of the touch wire 202 on the

[0094] It can be understood that, in the embodiment, the touch wire 202 is arranged in a layer different from the signal line 201, and an additional mask is needed to separately manufacture the pattern of the touch wire 202. By making the orthographic projection of the touch wire 202 on the substrate 10 at least partially overlap the orthographic projection of the signal line 201 on the substrate 10, the aperture ratio of the pixel can be improved.

[0095] In some embodiments, in the first direction X1, the width of the touch wire 202 is smaller than the width of the signal line 201, and thus the touch wire 202 cannot completely shield the signal line 201. In the embodiment, by arranging the shielding electrode 402 above the touch wire 202 (i.e., away from the side of the signal line 201), the capacitive coupling between the signal line 201 and the pixel electrode 401 can be better shielded, and the risk of crosstalk can be reduced. In other embodiments, the width of the touch wire 202 can be made larger than the width of the signal line 201, so as to completely shield the signal line 201 and shield the capacitive coupling between the signal line 201 and the pixel electrode 401, but the aperture ratio of the pixel will be reduced. In the embodiment, the shielding electrode 402 can be made of a transparent material, so as to avoid affecting the aperture ratio of the pixel.

[0096] In some embodiments of the present disclosure, referring to FIGS. 20 and 21, the array substrate includes a first insulating layer 50 and a second insulating layer 70, the first insulating layer 50 is located between the second conductive layer 30 and the third conductive layer 40, and the second insulating layer 70 is located between the second conductive layer 30 and the fourth conductive layer 60. The array substrate includes a first via 501 and a second via 701, the first via 501 penetrates the first insulating layer 50, and the second via 701 penetrates the first insulating layer 50 and the second insulating layer 70. The shielding electrode 402 is electrically connected to the common electrode 301 through the first via 501, and the shielding electrode 402 is electrically connected to the touch wire 202 through the second via 701. That is, the touch wire 202 is electrically connected to the shielding electrode 402, and the shielding electrode 402 is electrically connected to the common electrode 301. In the embodiment, the first via 501 and the second via 701 can be formed by the same etching process, so as to save process steps.

[0097] The embodiments of the present disclosure also provide a display panel including the array substrate as above, and the specific structure of the array substrate is described with reference to FIGS. 4 to 21 and the related description, which will not be repeated here.

[0098] Although some embodiments according to the general inventive concept of the present disclosure have been illustrated and described, it will be appreciated by those skilled in the art that changes can be made to these embodiments without departing from the principles and spirit of the general inventive concept of the present disclosure, and the scope of the present disclosure is defined by the claims and their equivalents.

Claims

1. An array substrate, wherein, The array substrate includes: Substrate; A first conductive layer is located on one side of the substrate, and the first conductive layer includes a plurality of signal lines spaced apart along a first direction; A second conductive layer is located on the side of the first conductive layer away from the substrate, and the second conductive layer includes a plurality of common electrodes; and A third conductive layer is located on the side of the second conductive layer away from the substrate, and the third conductive layer includes a plurality of pixel electrodes; The second conductive layer further includes a first gap, which is located between at least two adjacent common electrodes in the first direction, and the orthographic projection of the signal line on the substrate at least partially overlaps with the orthographic projection of the first gap on the substrate. The third conductive layer further includes a shielding electrode, which is connected to a fixed voltage signal. The orthographic projection of the shielding electrode on the substrate at least partially overlaps with the orthographic projection of the signal line on the substrate, and the orthographic projection of the shielding electrode on the substrate at least partially overlaps with the orthographic projection of the first gap on the substrate.

2. The array substrate according to claim 1, wherein, The array substrate further includes at least one first insulating layer located between the second conductive layer and the third conductive layer, the at least one first insulating layer including a first via, and the shielding electrode being electrically connected to the common electrode through the first via.

3. The array substrate according to claim 2, wherein, The plurality of common electrodes includes a first common electrode and a second common electrode, wherein the first common electrode and the second common electrode are respectively located on both sides of the first gap in the first direction; The first common electrode includes a first electrode body portion and a first protrusion portion, and the second common electrode includes a second electrode body portion and a first groove. The first protrusion portion protrudes from the first electrode body portion in a direction toward the second common electrode, and the first groove recesses from the second electrode body portion in a direction away from the first common electrode. as well as The orthographic projection of the shielding electrode on the substrate at least partially overlaps with the orthographic projection of the first protrusion on the substrate.

4. The array substrate according to claim 3, wherein, The orthographic projection of the first protrusion on the substrate covers the orthographic projection of the first via on the substrate.

5. The array substrate according to claim 4, wherein, The plurality of pixel electrodes are arranged in an array along the first direction and the second direction to form a plurality of pixel electrode rows spaced apart in the second direction and a plurality of pixel electrode columns spaced apart in the first direction, wherein the first direction and the second direction intersect. The third conductive layer includes a second slit extending along the first direction, the second slit being located between two adjacent rows of pixel electrodes; The third conductive layer includes a plurality of third gaps, which are respectively located between two adjacent pixel electrode columns; as well as The orthographic projection of the first via on the substrate is located within the orthographic projection of the intersection region of the second and third gaps on the substrate.

6. The array substrate according to claim 5, wherein, The first gap includes a first sub-gap and a second sub-gap, wherein the first sub-gap is the portion of the first gap located in the intersection region, and the second sub-gap is the portion of the first gap located between two adjacent pixel electrodes in the first direction; as well as The orthographic projection of the shielding electrode on the first conductive layer at least partially overlaps with a first portion of the signal line, the first portion of the signal line being located within the orthographic projection of the first sub-slit on the first conductive layer, and / or, the orthographic projection of the shielding electrode on the first conductive layer covers a second portion of the signal line, the second portion of the signal line being located within the orthographic projection of the second sub-slit on the first conductive layer.

7. The array substrate according to claim 5, wherein, The orthographic projections of the plurality of signal lines on the substrate at least partially overlap with the orthographic projections of the plurality of third gaps on the substrate; Wherein, the third conductive layer includes at least one first gap group, and the first gap group includes at least one of the third gaps; and In the regions where the third gaps of the first gap group are located, the orthographic projection of the first gap on the substrate at least partially overlaps with the orthographic projection of the third gap in the first gap group on the substrate, and the orthographic projection of the shielding electrode on the substrate at least partially overlaps with the orthographic projection of the third gap in the first gap group on the substrate.

8. The array substrate according to claim 7, wherein, The third conductive layer includes at least one second gap group, and the second gap group includes at least one of the third gaps; as well as In the regions where the third slits of the second slit group are located, the orthographic projection of the common electrode on the substrate at least partially overlaps with the orthographic projection of the signal line on the substrate; And / or, the orthographic projection of the first slot on the substrate and the orthographic projection of the third slot in the second slot group on the substrate are spaced apart in the first direction, and the orthographic projection of the shielding electrode on the substrate and the orthographic projection of the third slot in the second slot group on the substrate are spaced apart in the first direction.

9. The array substrate according to claim 7, wherein, The third conductive layer includes at least one third gap group, and the third gap group includes at least one of the third gaps; as well as In the region where each of the third slits in the third slit group is located, the orthographic projection of the common electrode on the substrate at least partially overlaps with the orthographic projection of the signal line on the substrate; And / or, the orthographic projection of the first slot on the substrate and the orthographic projection of the third slot in the third slot group on the substrate are spaced apart in the first direction, and the orthographic projection of the shielding electrode on the substrate at least partially overlaps with the orthographic projection of the third slot in the third slot group on the substrate.

10. The array substrate according to claim 5, wherein, The third conductive layer includes a plurality of shielding electrodes, and the plurality of shielding electrodes and the plurality of pixel electrode columns are alternately arranged in the first direction.

11. The array substrate according to claim 5, wherein, In the first direction, a shielding electrode is provided at every interval of at least one of the pixel electrode columns; and / or In the first direction, a first slit is provided at every interval of at least one of the pixel electrode columns.

12. The array substrate according to claim 5, wherein, The plurality of pixel electrodes include a first pixel electrode and a second pixel electrode, the first pixel electrode and the second pixel electrode being located in adjacent rows of pixel electrodes respectively, the first pixel electrode extending along a third direction, the second pixel electrode extending along a fourth direction, the third direction intersecting with the first direction and the second direction respectively, and the fourth direction intersecting with the first direction, the second direction and the third direction respectively; The portion of the shielding electrode adjacent to the first pixel electrode extends along the third direction, and the portion of the shielding electrode adjacent to the second pixel electrode extends along the fourth direction; or The pixel electrode includes a first electrode portion, a second electrode portion, and a connecting portion. The first electrode portion extends along a third direction, and the second electrode portion extends along a fourth direction. The third direction intersects with the fourth direction. The connecting portion is used to connect the first electrode portion and the second electrode portion. The portion of the shielding electrode adjacent to the first electrode portion extends along the third direction, and the portion of the shielding electrode adjacent to the second electrode portion extends along the fourth direction. In the first direction, the portion of the shielding electrode adjacent to the connecting portion protrudes to the same side as the connecting portion.

13. The array substrate according to claim 12, wherein, In the first direction, the spacing between the shielding electrode and the two adjacent pixel electrodes is equal.

14. The array substrate according to claim 5, wherein, The pixel electrode includes a pixel electrode body and a second protrusion, and the shielding electrode includes a shielding electrode body and a second groove. The second protrusion protrudes from the pixel electrode body in a direction toward the shielding electrode, and the second groove is recessed from the shielding electrode body in a direction away from the second protrusion. as well as The second protrusions located in the same row of pixel electrodes have the same protrusion direction, while the second protrusions located in two adjacent rows of pixel electrodes have opposite protrusion directions.

15. The array substrate according to claim 1, wherein, The common electrode is reused as a touch electrode; the first conductive layer further includes a plurality of touch traces spaced apart along the first direction, the touch traces being electrically connected to the common electrode; and The orthographic projection of the touch trace on the substrate at least partially overlaps with the orthographic projection of the pixel electrode on the substrate, or the orthographic projection of the touch trace on the substrate at least partially overlaps with the orthographic projection of the shielding electrode on the substrate.

16. The array substrate according to claim 1, wherein, The common electrode is reused as a touch electrode; the array substrate further includes a fourth conductive layer, which is located between the first conductive layer and the second conductive layer, and includes a plurality of touch traces spaced apart along the first direction, the touch traces being electrically connected to the common electrode; and The orthographic projection of the touch trace on the substrate at least partially overlaps with the orthographic projection of the signal line on the substrate; And / or, the orthographic projection of the touch trace on the substrate at least partially overlaps with the orthographic projection of the shielding electrode on the substrate; And / or, the orthographic projection of the touch trace on the substrate at least partially overlaps with the orthographic projection of the first gap on the substrate.

17. The array substrate according to claim 16, wherein, The array substrate includes a first insulating layer and a second insulating layer, wherein the first insulating layer is located between the second conductive layer and the third conductive layer, and the second insulating layer is located between the second conductive layer and the fourth conductive layer; The array substrate includes a first via and a second via, wherein the first via penetrates the first insulating layer and the second via penetrates both the first insulating layer and the second insulating layer; as well as The shielding electrode is electrically connected to the common electrode through the first via, and the shielding electrode is electrically connected to the touch trace through the second via.

18. A display panel, wherein, The display panel includes an array substrate according to any one of claims 1-17.

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