1results about How to "Resistance minimization" patented technology

This application proposes a PAD structure layout and its design method. The PAD structure layout includes: an ESD ring, comprising a VSS ring and a VDD ring, for ESD discharge; a POWER ring, composed of multiple layers of metal connected in parallel, for providing power to the logic control circuit; multiple N-type ESD protection transistors, including a first N-type ESD protection transistor and a second N-type ESD protection transistor; multiple P-type ESD protection transistors, including a first P-type ESD protection transistor and a second P-type ESD protection transistor; multiple signal window access points, located between the VSS ring and the VDD ring, configured to connect signals to the N-type ESD protection transistors and the P-type ESD protection transistors respectively; a first window and a second window; a logic control circuit located below the POWER ring; and a metal trace structure, including M1 in a first direction and M2 and M3 connected in parallel in a second direction. This application can reduce the layout area and chip perimeter, while improving the layout of windows and ESD protection transistors, utilizing space redundancy to reduce latch-up risk and save chip space.