2results about How to "Resistance minimization" patented technology

This invention provides a battery and a current collector for use in the battery, a battery pack including the current collector, and an automobile. The battery includes: an electrode assembly having a first electrode, a second electrode, and a separator membrane between them wound around a winding shaft to define a core and an outer peripheral surface; the first electrode having a first uncoated portion at its long side end along the winding direction, the first uncoated portion being exposed to the outside of the separator membrane, at least a portion of the first uncoated portion itself serving as an electrode tab; a housing having an opening on one side through which the electrode assembly is received; a first current collector including: an edge portion disposed on the upper part of the electrode assembly; a first uncoated portion bonding portion extending inward from the edge portion and bonding with the first uncoated portion; a terminal bonding portion disposed separately from the first uncoated portion bonding portion; and a terminal bonding portion bonded to the terminal bonding portion.

This application proposes a PAD structure layout and its design method. The PAD structure layout includes: an ESD ring, comprising a VSS ring and a VDD ring, for ESD discharge; a POWER ring, composed of multiple layers of metal connected in parallel, for providing power to the logic control circuit; multiple N-type ESD protection transistors, including a first N-type ESD protection transistor and a second N-type ESD protection transistor; multiple P-type ESD protection transistors, including a first P-type ESD protection transistor and a second P-type ESD protection transistor; multiple signal window access points, located between the VSS ring and the VDD ring, configured to connect signals to the N-type ESD protection transistors and the P-type ESD protection transistors respectively; a first window and a second window; a logic control circuit located below the POWER ring; and a metal trace structure, including M1 in a first direction and M2 and M3 connected in parallel in a second direction. This application can reduce the layout area and chip perimeter, while improving the layout of windows and ESD protection transistors, utilizing space redundancy to reduce latch-up risk and save chip space.