Data processing node, system and method

Abstract

A data processing node, system and method is disclosed by the embodiments of the present invention which relates to the computer field and enables the flexible extension of the computer system. Said data processing node includes multiple Central Processing Units (CPUs), each CPU including multiple interconnect interfaces. Said CPUs are fully connected through the interconnect interfaces to form a CPU module. At least one interconnect interface is reserved in said CPU module to connect with the inner interconnect interface of an interconnect board. The interconnect board includes at least one outer interconnect interface which is used for connecting with the outer interconnect interfaces of the interconnect boards of other data processing nodes. The invention can be applied in the computer field.

Description

technical field [0001] The present invention relates to a computer system, in particular to a data processing node, system and method. Background technique [0002] A data processing node can include multiple CPUs. In a system where there are multiple data processing nodes and the nodes contain multiple CPUs, how to access each other between CPUs of different nodes is a core technology, that is, the interconnection between CPUs is The core technology of the system. At present, data processing nodes can be interconnected in a fully interconnected manner to realize the interconnection between CPUs, and the interconnection between CPUs can also be realized in the form of interconnection modules. [0003] As shown in Figure 1(a), when the full interconnection method is used to realize the interconnection between CPUs, any two nodes in the system need to be directly connected through a high-speed interconnection interface, and the control function module must be integrated insid...

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Problems solved by technology

[0005] When using the full interconnection method shown in Figure 1(a) to realize the interconnection between CPUs, due to the need to integrate control function modules in the node, the cost of each node is relatively high, and due to the high-speed interconnection interface The number is limited, the scalability of the system is poor, and the flexibility is low;

[0006] When the interconnection between CPUs is realized in the form of interconnection modules as shown in Figure 1(b), although the expansion of the system can be realized, the access between nodes in the system needs to be selectively interconnected through the interconnection modules, resulting in The access delay between nodes is large, which affects the operating efficiency of the system

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