23results about How to "Interconnection" patented technology

The invention relates to a preparation method of a multi-chip interconnection packaging structure and the multi-chip interconnection packaging structure. The preparation method of the multi-chip interconnection packaging structure comprises the following steps: providing a packaging substrate and a plurality of chips; a substrate circuit is arranged in the packaging substrate; providing an interconnection chip; a chip interconnection circuit is arranged in the interconnection chip; forming a plurality of grooves in one side of the packaging substrate; mounting interconnection chips in the plurality of grooves in a one-to-one correspondence manner, wherein the thickness of the interconnection chips is smaller than or equal to the depth of the grooves; a plurality of chips are inversely arranged on the side, where the interconnection chips are exposed, of the packaging substrate, the interconnection chips are connected with at least two chips at the same time, and meanwhile the chips are connected with the substrate circuits respectively. According to the preparation method of the multi-chip interconnection packaging structure, the height of the packaging structure can be reduced, the process can be simplified, the reliability and the yield of the packaging structure can be improved, the test cost can be reduced, and the parasitic effect between the chips can be reduced.

The invention discloses a chip packaging structure, a preparation method and electronic equipment, and the chip packaging structure comprises a first substrate which is provided with a plurality of first pins; the electric supporting piece is arranged on the first substrate, and the electric supporting piece is electrically connected with the first pin; the second substrate and the first substrate are arranged in parallel in a spaced mode, the first substrate and the second substrate are connected in a supported mode through an electric supporting piece, a plurality of second pins are arranged on the second substrate, part of the second pins are electrically connected with the electric supporting piece, and the other part of the second pins are used for being led out to be connected with external components; and the plastic package part is used for respectively carrying out plastic package on the two opposite sides of the first substrate so as to form the chip package structure. One-time plastic packaging can be carried out on the two faces of the first substrate, overall plastic packaging of the chip packaging structure is achieved, two-time plastic packaging does not need to be carried out on the two faces of the first substrate, the plastic packaging efficiency is high, two sets of plastic packaging molds do not need to be used, and the cost is reduced.

The present application provides a method for preparing a semiconductor structure, a semiconductor structure and a semiconductor device, the method comprising: providing a substrate formed with a fin structure; wherein the fin structure comprises a device region and a field region arranged in a first direction; removing a first portion of the fin structure located in the field region and retaining a second portion of the field region; forming a first semiconductor structure based on an upper portion of the fin structure, the first semiconductor structure comprising a first source-drain structure, a first source-drain metal and a first interlayer dielectric layer; flipping and removing the substrate to expose a lower portion of the fin structure; removing the second portion of the field region to expose the first interlayer dielectric layer; forming a second semiconductor structure based on the lower portion of the fin structure, the second semiconductor structure comprising a second source-drain structure, a second source-drain metal and a second interlayer dielectric layer; forming an interconnection through-hole structure in the first interlayer dielectric layer and the second interlayer dielectric layer; and connecting the interconnection through-hole structure to the first source-drain metal and the second source-drain metal.

The invention discloses a thermocompression bonding and reflow soldering packaging method, a flip-chip bonding structure and a chip structure, and relates to the technical field of chips. Comprising the following steps: preparing a plurality of welding spots on one side of a substrate to obtain a first welding plate; preparing a plurality of gold bumps on one side of the chip to obtain a second welding plate; the side, with the solder, of the first welding plate is welded to the side, with the gold bumps, of the second welding plate, and a packaged chip is obtained; wherein the welding pressure is 20-25g per gold bump. By directly welding the side, with the solder, of the first welding plate and the side, with the gold bumps, of the second welding plate, the step of flattening the gold bumps in traditional flip reflow soldering is omitted, preparation of the first welding plate and preparation of the second welding plate can be conducted at the same time, flip bonding between a chip and a substrate is achieved on the same production line, and the production efficiency is improved. And electrical signal interconnection is realized. The gold bump leveling process link is reduced, the complexity of the process flow is reduced, the yield is improved, the manufacturing cost is reduced, and the production and manufacturing efficiency is improved.

The invention provides a method and device for casting a metallized ceramic matrix and the metallized ceramic matrix, and relates to the field of electronic ceramic surface metallization. The method comprises the following steps: pre-punching ceramic substrates, carrying out surface treatment, and fixing a plurality of ceramic substrates in a mold cavity; then pressing the liquid metal into a mold cavity provided with the ceramic matrix through pressure, and cooling the mold cavity and an internal contained object to room temperature under the protection atmosphere of inert gas; and finally, after the mold is removed, the required multi-layer interconnected metallized ceramic matrix can be prepared. Compared with the prior art, the process is simple and convenient, the multiple layers of ceramic matrixes and the metal layers are integrally cast through the casting technology, interconnection of any layers of the multiple layers of ceramic matrixes is achieved by pressing in the liquid metal, and the metallized ceramic matrixes of any three-dimensional structure which are interconnected in a three-dimensional mode are obtained through the liquid metal.

The embodiment of the invention provides a rich media message transmission method, electronic equipment, a storage medium and a program product. The method comprises the following steps: the rich media information system receives a rich message sending request sent by a client, and sends the rich message sending request to a second message center through a first message center; the second message center issues the rich message request to a user side; the first WAP gateway receives a rich message extraction request sent by the user side; the first WAP gateway sends the rich message extraction request to a rich media information system; the rich media information system sends a corresponding rich message to the first WAP gateway based on the rich message extraction request; and the first WAP gateway issues the rich message to the user side. According to the method, interaction of rich media information among different core networks is realized, and cross-region and cross-network transmission of the rich media information is realized.

The embodiment of the utility model provides a processor mainboard and computer equipment, the processor mainboard comprises a plurality of calculation acceleration entities, the calculation acceleration entities are standardized entity units at least used for integrating calculation units, and each calculation acceleration entity comprises a calculation unit and a first connector; each computing unit comprises a plurality of first ports, the first ports are respectively connected to a bottom plate of the processor mainboard through the first connectors, and the first ports support a memory interconnection bus between the computing units; the backplane comprises a plurality of first interconnection channels, one first interconnection channel is in butt joint with one first port of each of the two computing acceleration entities, and the plurality of first interconnection channels cover interconnection among the plurality of computing acceleration entities. The processor mainboard provided by the embodiment of the utility model can provide a basis for data transmission among a plurality of computing units.

The invention discloses a deep groove layout design method of an image sensor, which comprises the following steps of: providing a mask plate which comprises a plurality of deep groove patterns which are mutually crossed and encircled to form pixel areas which are arranged in an array; the intersections between the deep groove patterns are disconnected to form connecting structures for connecting the adjacent pixels; wherein the four corners of any pixel correspond to the four connecting structures, the two diagonal connecting structures in the four connecting structures are parallel to each other, and the two adjacent connecting structures in the four connecting structures are perpendicular to each other. According to the layout design, deep groove patterns with consistent sizes can be obtained, interconnection between any adjacent pixels can be realized, the etching loading effect can be reduced, a deep groove structure with relatively good etching depth consistency can be obtained, the subsequent process difficulty is reduced, and the performance and the yield of the image sensor are improved.

The embodiment of the invention provides an electric connector and an interconnection system. The electric connector comprises a first matching interface, a second matching interface and a third matching interface which extend along the longitudinal direction and are parallel to each other; and a mounting interface extending in a vertical direction perpendicular to the longitudinal direction. According to the electric connector provided by the embodiment of the invention, the first matching interface, the second matching interface, the third matching interface and the mounting interface are arranged, so that the electric connector can be connected with more than or equal to three circuit boards at the same time, and interconnection of a plurality of circuit boards is realized. When the electric connector is applied to an interconnection system, the number of the electric connectors of the interconnection system can be reduced, the space utilization rate of the interconnection system can be improved, and miniaturization of products is achieved.

The application discloses a high-current-density vertical power supply and distribution module and a packaging process thereof, and belongs to the technical field of microelectronic packaging. The module and the packaging process solve the problems of large size, low current density, high buried chip packaging thermal resistance, difficult heat dissipation and excessively high junction temperature of the prior art. In the module, a bottom electrode, a packaging substrate, a power device and a top electrode are stacked. Integrated circuit chips and passive devices are embedded in the packaging substrate and stacked in the vertical direction. The packaging process comprises embedding the integrated circuit chips in a first core plate, embedding the passive devices in a second core plate, and pressing to form the packaging substrate; drilling, hole wall metallization and hole plugging are performed on the packaging substrate to obtain a whole to be packaged; and the whole to be packaged is subjected to pouring, grinding and surface metallization. The module and the packaging process can effectively improve the current density.

The invention discloses an offshore oilfield power load ultra-short-term prediction method and system. The method comprises the following steps: obtaining related data of an offshore oilfield in real time; preprocessing the related data of the offshore oilfield; according to a preset sliding window, dividing the preprocessed offshore oilfield related data into multiple segments of time series data; constructing a time sequence diagram based on the multiple segments of time sequence data; and inputting the time sequence diagram into the mobile pooling graph neural network, and outputting an offshore oilfield power load prediction value. According to the method, the time features of the related data of the offshore oilfield are extracted, the spatial dependency among different variables is captured through the graph neural network, the prediction performance of the model is remarkably improved through the multi-level feature extraction method, and complex dynamic changes can be better dealt with.

This invention relates to a radiator grid structure and its forming process, belonging to the field of welding technology. It solves the problem that existing technologies lack suitable grid structures for radiator products, making it impossible to form open areas and thus hindering the lightweighting of radiator products. The radiator grid structure includes grid plates and baffles, with the baffles sequentially connected to form a closed loop. The grid plates are inserted into the internal space formed by the baffles to form open areas, and the ends of the grid plates are fixedly connected to the baffles. This invention achieves lightweighting of products in the aerospace field.

The present invention proposes a device and method for CPU interconnection interrupt forwarding, the device includes: multiple clusters and several signal forwarding modules; each cluster includes multiple interconnected central processing units, and each central processing unit is connected to the nearest signal forwarding module; when it is determined that the main central processing unit and the slave central processing unit are located in different clusters, and the main central processing unit wants to send an interrupt signal to the slave central processing unit, the interrupt signal received by the interrupt controller is forwarded to the slave central processing unit according to the address signal sent by the main central processing unit. Based on the device, a method for CPU interconnection interrupt forwarding is also proposed. The method runs on the signal forwarding module, firstly determines whether the main central processing unit and the slave central processing unit are located in the same cluster, and then performs corresponding operations according to the positions of the two central processing units. The present invention is an interrupt forwarding mechanism between CPUs in multi-chip interconnection, and successfully realizes multi-chip interconnection in the case where the interrupt forwarding address is insufficient.

This application provides a method for increasing winding density using longitudinal slots in a spacer layer, comprising: Step 1, providing a substrate and forming an interlayer dielectric layer on the substrate; Step 2, performing a first etching to form a first trench in the interlayer dielectric layer for filling an M1 metal layer; Step 3, performing a second etching to form a second trench in the interlayer dielectric layer for filling a spacer layer that blocks the M1 metal layer and a third trench for achieving interconnection between portions of the M1 metal layers; Step 4, depositing a spacer layer in the second and third trenches, forming a longitudinal slot in the spacer layer located in the third trench; Step 5, filling the first trench and the longitudinal slot with an M1 metal layer. The longitudinal slots formed by the spacer layer deposition enable interconnection between metal lines in the same layer, replacing traditional upper metal layers and vias, saving traces for back-end layout and wiring, reducing process costs, reducing parasitic capacitance and resistance, and improving chip performance.

The invention discloses a gold bump preparation method for thermal ultrasonic spherical gold wire bonding, a flip-chip bonding structure and a chip, and relates to the field of chips. According to the mass fraction, the method comprises the following steps that a plurality of gold protruding points are formed on a flip-chip bonding pad through hot ultrasonic spherical gold wire bonding, and the width of the flip-chip bonding pad is larger than or equal to 150 micrometers. A plurality of gold bumps are formed through thermal ultrasonic spherical gold wire bonding, so that the plurality of gold bumps can support a flip-chip bonding pad with the width greater than or equal to 150 [mu] m for a large-size chip. Based on the specific requirements of gold wires with different diameters and the sizes of the bonding pads, combined preparation of various gold bumps is performed, the contact area of the bonding pads on the flip chip and the bonding pads on the substrate is increased, electrical signal interconnection between the bonding pads is completed, the gold bump process replaces micro gold bumps and copper columns which are high in cost and complex in process, the cost can be reduced, and the production efficiency is improved. The efficiency is improved.

The invention discloses a multi-plane intelligent computing center optical interconnection architecture based on a multi-wavelength tunable emitter and a communication method. The architecture comprises an optical switching plane formed by modularization interconnection of a plurality of small-port array waveguide gratings, and a communication node array comprising a plurality of communication nodes. Each communication node is equipped with a plurality of optical transmitting modules and optical receiving modules, and the optical transmitting modules are integrated with multi-wavelength tunable transmitters and can simultaneously generate and independently tune a plurality of optical signals with different wavelengths. Through wavelength tuning and the cyclic wavelength routing characteristic of the array waveguide grating, an optical link with variable capacity can be dynamically established between any source node and any destination node, and one-to-many fan-out communication is supported. According to the method, nanosecond reconstruction delay, fine-grained bandwidth flexible adjustment and high-energy-efficiency interconnection with large-scale nodes are realized, dynamic, burst and skew communication loads of an intelligent calculation center are effectively adapted, and the network performance and energy efficiency are improved.

The invention relates to the field of semiconductors, in particular to a multilayer stacked FPGA (Field Programmable Gate Array) architecture based on TSV (Through Silicon Via) vertical interconnection. According to the multi-layer stacked FPGA architecture based on TSV vertical interconnection, interconnection of multiple layers of tube cores in the vertical direction can be achieved, a 3D packaging FPGA chip with more logic resources is stacked, and due to the fact that vertical interconnection signals are directly transmitted to other tube cores through the TSV holes, the vertical interconnection signals can be directly transmitted to other tube cores through the TSV holes; compared with a 2.5 D packaging FPGA chip based on silicon interposer long overline interconnection, the area, the power consumption and the time delay are reduced in the aspect of signal data transmission.

This invention relates to a method, equipment, apparatus, system, and production line for processing blind vias in multilayer glass substrates. The method includes: controlling a first laser focusing spot to enter and focus inside the glass layer from a predetermined position on the upper surface of the glass layer, thereby modifying or micro-exploding the glass layer to form loose blind vias; chemically etching the multilayer glass substrate with the loose blind vias to form second blind vias; and controlling a second laser cleaning spot to laser-process the insulating layer at the bottom of the second blind vias to form third blind vias. This invention uses a first laser focusing spot to process loose blind vias on the glass layer, making the glass in this area porous, increasing the contact area with the chemical etching solution, and thus accelerating the etching speed. Simultaneously, the first laser focusing spot modifies or micro-explodes the glass layer, and the glass within the loose blind vias is annealed by heat, further improving the etching efficiency.

The invention relates to a gas sensor based on a silicon through hole technology and a preparation method, and belongs to the technical field of gas sensors. The conductive material grows from bottom to top on the premise that the seed layer grows at the bottom and the growth area of the seed layer is limited, electrical interconnection of the front face and the back face of the device is achieved, the sensor packaging structure has the highest space utilization arrangement mode, and the highest stacking density of the device in the vertical direction can be achieved. The integration level of the gas sensor is improved, electrodes are led out from the back of the sensor, and a basis is provided for vertical interconnection of intelligent gas sensors.

The invention relates to a connection method of a silicon optical integrated chip and a high-frequency transition substrate and an interconnection device, and the method comprises the following steps: calculating the geometric dimension of the interconnection device through electromagnetic field simulation analysis software, and enabling the impedance of the interconnection device, the silicon optical integrated chip and the transition transmission substrate to be matched; the interconnection substrate of the interconnection device is sucked in a vacuum mode, so that the salient points on the interconnection substrate are adjusted to be aligned with the bonding pad of the silicon optical integrated chip and the bonding pad mark of the transition transmission substrate; welding the salient points and the bonding pads after mark alignment to realize electrical connection of the interconnection device, the silicon optical integrated chip and the transition transmission substrate; and a control signal is loaded to the silicon optical integrated chip, so that the silicon optical integrated chip is actively coupled and aligned, and finally photoelectric integrated packaging of the silicon optical integrated chip is completed. The coupling alignment of the optical fiber and the optical waveguide structure of the silicon optical integrated chip is realized, meanwhile, the interconnection performance between the silicon optical integrated chip and the transition transmission substrate can be improved, the problem of impedance mismatching is avoided, and the signal transmission rate is improved.

The invention discloses a grounding stacking integrated radio frequency front-end chip stacking structure and a preparation method thereof, and belongs to the technical field of radio frequency microsystems. Based on silicon-based packaging, radio frequency front-end chips including a power divider, a low-noise amplifier and a multifunctional chip are subjected to function division, and four-channel radio frequency chips are respectively subjected to silicon-based embedded packaging and are led out through silicon through holes (TSV). An upper layer chip packaging module and a lower layer chip packaging module which are used for packaging two channel radio frequency chips respectively are bonded and integrated in a back-to-back mode, and the radio frequency chips which are packaged differently on the upper layer and the lower layer are connected through TSV via holes. Fanout lead-out is carried out in a bottom layer radio frequency chip, so that high-density integrated stacking is realized. By the adoption of the integrated stacking structure, the packaging size can be greatly reduced, and compared with a traditional silicon-based embedded fan-out structure, the size can be further reduced, and the packaging weight is reduced.

The invention relates to the technical field of metal sintering interconnection, and discloses a sintering device and method for metal foil abutted seam interconnection, and the sintering device comprises a heating platform, a multi-degree-of-freedom direct writing mechanical arm, a shielding gas device and a high-temperature thermal imager. The sintering device can be suitable for metal foil samples of different shapes and sizes, large-area uniform heating is achieved, the sintered samples are heated uniformly, and the interconnection quality of the sintered samples is improved. A multi-layer gradient sintering method is used in the sintering process, and the curing effect of each time of soldering paste coating and the metallurgical bonding strength between different layers can be guaranteed. By means of the gradient sintering method, the service performance of the sintered metal foil can be guaranteed, it is guaranteed that the resistivity of a sintered interconnection area is lower while the sintering interconnection strength is guaranteed, better heat conduction and electric conduction effects are achieved, and meanwhile the interconnection reliability is improved.

The invention relates to the technical field of chip packaging, and provides a multi-chip three-dimensional packaging structure and a packaging method. The packaging structure comprises a plurality of molding dielectric layers and a plurality of chip sets, the plurality of chip sets are respectively plastically packaged in the plurality of molding dielectric layers, and the plurality of chip sets are interconnected through plastically packaged through holes in the molding dielectric layers; the plurality of chips of the two adjacent chip sets are inversely arranged on the rewiring layer between the two adjacent molding dielectric layers; at least one of the two adjacent chip groups comprises a plurality of chips with high-speed interfaces and low-speed interfaces, the high-speed interfaces of the plurality of chips of the chip group are connected through an interconnection bridge, and the low-speed interfaces of the chips of the two adjacent chip groups are led out to the plastic package through hole through a rewiring layer between the two adjacent molding dielectric layers. According to the multi-chip three-dimensional packaging method, the interconnection bridge is adopted, and the packaging technology combining the plastic package through hole (TMV) and the rewiring layer (RDL) is used, so that the technical difficulty and the manufacturing cost of multi-chip three-dimensional packaging are reduced.