9results about How to "Interconnection" patented technology

The invention provides a method and device for casting a metallized ceramic matrix and the metallized ceramic matrix, and relates to the field of electronic ceramic surface metallization. The method comprises the following steps: pre-punching ceramic substrates, carrying out surface treatment, and fixing a plurality of ceramic substrates in a mold cavity; then pressing the liquid metal into a mold cavity provided with the ceramic matrix through pressure, and cooling the mold cavity and an internal contained object to room temperature under the protection atmosphere of inert gas; and finally, after the mold is removed, the required multi-layer interconnected metallized ceramic matrix can be prepared. Compared with the prior art, the process is simple and convenient, the multiple layers of ceramic matrixes and the metal layers are integrally cast through the casting technology, interconnection of any layers of the multiple layers of ceramic matrixes is achieved by pressing in the liquid metal, and the metallized ceramic matrixes of any three-dimensional structure which are interconnected in a three-dimensional mode are obtained through the liquid metal.

The embodiment of the utility model provides a processor mainboard and computer equipment, the processor mainboard comprises a plurality of calculation acceleration entities, the calculation acceleration entities are standardized entity units at least used for integrating calculation units, and each calculation acceleration entity comprises a calculation unit and a first connector; each computing unit comprises a plurality of first ports, the first ports are respectively connected to a bottom plate of the processor mainboard through the first connectors, and the first ports support a memory interconnection bus between the computing units; the backplane comprises a plurality of first interconnection channels, one first interconnection channel is in butt joint with one first port of each of the two computing acceleration entities, and the plurality of first interconnection channels cover interconnection among the plurality of computing acceleration entities. The processor mainboard provided by the embodiment of the utility model can provide a basis for data transmission among a plurality of computing units.

The application discloses a high-current-density vertical power supply and distribution module and a packaging process thereof, and belongs to the technical field of microelectronic packaging. The module and the packaging process solve the problems of large size, low current density, high buried chip packaging thermal resistance, difficult heat dissipation and excessively high junction temperature of the prior art. In the module, a bottom electrode, a packaging substrate, a power device and a top electrode are stacked. Integrated circuit chips and passive devices are embedded in the packaging substrate and stacked in the vertical direction. The packaging process comprises embedding the integrated circuit chips in a first core plate, embedding the passive devices in a second core plate, and pressing to form the packaging substrate; drilling, hole wall metallization and hole plugging are performed on the packaging substrate to obtain a whole to be packaged; and the whole to be packaged is subjected to pouring, grinding and surface metallization. The module and the packaging process can effectively improve the current density.

This invention relates to a radiator grid structure and its forming process, belonging to the field of welding technology. It solves the problem that existing technologies lack suitable grid structures for radiator products, making it impossible to form open areas and thus hindering the lightweighting of radiator products. The radiator grid structure includes grid plates and baffles, with the baffles sequentially connected to form a closed loop. The grid plates are inserted into the internal space formed by the baffles to form open areas, and the ends of the grid plates are fixedly connected to the baffles. This invention achieves lightweighting of products in the aerospace field.

This application provides a method for increasing winding density using longitudinal slots in a spacer layer, comprising: Step 1, providing a substrate and forming an interlayer dielectric layer on the substrate; Step 2, performing a first etching to form a first trench in the interlayer dielectric layer for filling an M1 metal layer; Step 3, performing a second etching to form a second trench in the interlayer dielectric layer for filling a spacer layer that blocks the M1 metal layer and a third trench for achieving interconnection between portions of the M1 metal layers; Step 4, depositing a spacer layer in the second and third trenches, forming a longitudinal slot in the spacer layer located in the third trench; Step 5, filling the first trench and the longitudinal slot with an M1 metal layer. The longitudinal slots formed by the spacer layer deposition enable interconnection between metal lines in the same layer, replacing traditional upper metal layers and vias, saving traces for back-end layout and wiring, reducing process costs, reducing parasitic capacitance and resistance, and improving chip performance.

The invention discloses a multi-plane intelligent computing center optical interconnection architecture based on a multi-wavelength tunable emitter and a communication method. The architecture comprises an optical switching plane formed by modularization interconnection of a plurality of small-port array waveguide gratings, and a communication node array comprising a plurality of communication nodes. Each communication node is equipped with a plurality of optical transmitting modules and optical receiving modules, and the optical transmitting modules are integrated with multi-wavelength tunable transmitters and can simultaneously generate and independently tune a plurality of optical signals with different wavelengths. Through wavelength tuning and the cyclic wavelength routing characteristic of the array waveguide grating, an optical link with variable capacity can be dynamically established between any source node and any destination node, and one-to-many fan-out communication is supported. According to the method, nanosecond reconstruction delay, fine-grained bandwidth flexible adjustment and high-energy-efficiency interconnection with large-scale nodes are realized, dynamic, burst and skew communication loads of an intelligent calculation center are effectively adapted, and the network performance and energy efficiency are improved.

The invention relates to the field of semiconductors, in particular to a multilayer stacked FPGA (Field Programmable Gate Array) architecture based on TSV (Through Silicon Via) vertical interconnection. According to the multi-layer stacked FPGA architecture based on TSV vertical interconnection, interconnection of multiple layers of tube cores in the vertical direction can be achieved, a 3D packaging FPGA chip with more logic resources is stacked, and due to the fact that vertical interconnection signals are directly transmitted to other tube cores through the TSV holes, the vertical interconnection signals can be directly transmitted to other tube cores through the TSV holes; compared with a 2.5 D packaging FPGA chip based on silicon interposer long overline interconnection, the area, the power consumption and the time delay are reduced in the aspect of signal data transmission.

This invention relates to a method, equipment, apparatus, system, and production line for processing blind vias in multilayer glass substrates. The method includes: controlling a first laser focusing spot to enter and focus inside the glass layer from a predetermined position on the upper surface of the glass layer, thereby modifying or micro-exploding the glass layer to form loose blind vias; chemically etching the multilayer glass substrate with the loose blind vias to form second blind vias; and controlling a second laser cleaning spot to laser-process the insulating layer at the bottom of the second blind vias to form third blind vias. This invention uses a first laser focusing spot to process loose blind vias on the glass layer, making the glass in this area porous, increasing the contact area with the chemical etching solution, and thus accelerating the etching speed. Simultaneously, the first laser focusing spot modifies or micro-explodes the glass layer, and the glass within the loose blind vias is annealed by heat, further improving the etching efficiency.

The invention discloses a grounding stacking integrated radio frequency front-end chip stacking structure and a preparation method thereof, and belongs to the technical field of radio frequency microsystems. Based on silicon-based packaging, radio frequency front-end chips including a power divider, a low-noise amplifier and a multifunctional chip are subjected to function division, and four-channel radio frequency chips are respectively subjected to silicon-based embedded packaging and are led out through silicon through holes (TSV). An upper layer chip packaging module and a lower layer chip packaging module which are used for packaging two channel radio frequency chips respectively are bonded and integrated in a back-to-back mode, and the radio frequency chips which are packaged differently on the upper layer and the lower layer are connected through TSV via holes. Fanout lead-out is carried out in a bottom layer radio frequency chip, so that high-density integrated stacking is realized. By the adoption of the integrated stacking structure, the packaging size can be greatly reduced, and compared with a traditional silicon-based embedded fan-out structure, the size can be further reduced, and the packaging weight is reduced.