Packaging method of fan-out type chip, and packaging structure

An encapsulation method and encapsulation structure technology, which are applied in the manufacturing of electrical components, electrical solid-state devices, and semiconductor/solid-state devices, etc., can solve the problem of low packaging quality of semiconductor chips, and achieve the effects of improving yield, wide application prospects and performance.

Inactive Publication Date: 2016-04-13
SJ SEMICON JIANGYIN CORP
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0006] In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a method for packa

Method used

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  • Packaging method of fan-out type chip, and packaging structure
  • Packaging method of fan-out type chip, and packaging structure
  • Packaging method of fan-out type chip, and packaging structure

Examples

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Embodiment Construction

[0042] Embodiments of the present invention are described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation modes, and various modifications or changes can be made to the details in this specification based on different viewpoints and applications without departing from the spirit of the present invention.

[0043] see Figure 2 to Figure 9 . It should be noted that the diagrams provided in this embodiment are only schematically illustrating the basic idea of ​​the present invention, so that only the components related to the present invention are shown in the diagrams rather than the number, shape and Dimensional drawing, the type, quantity and proportion of each component can be changed arbitrarily during actual implementation, and the...

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Abstract

The invention provides a packaging method of a fan-out type chip, and a packaging structure. The packaging structure comprises chips with projections, wherein a dielectric layer is formed on the surfaces of the chips, and the projections are exposed from the surfaces; a plastic packaging material filled among the chips with the projections, wherein the height of the plastic packaging material is not higher than that of each projection so as to enable the projections to be exposed from the surface of the plastic packaging material; a rewiring layer formed on the chips with the projections and realizing interconnection among the chips; and projection lower metal layers and dimpling points. According to the invention, the dielectric layer exposing the projections is formed on the surfaces of the chips with the projections, the projections are protected, the subsequent interconnection among the chips is realized, and damaged or broken conditions of the projections caused by thermal expansion in the subsequent processes for manufacturing the rewiring layer of solder dimpling points are avoided, so that the packaging performance is substantially improved, and the yield is simultaneously improved.

Description

technical field [0001] The invention relates to a packaging method and a packaging structure of a semiconductor chip, in particular to a packaging method and a packaging structure of a fan-out chip. Background technique [0002] With the rapid development of the integrated circuit manufacturing industry, people's requirements for the packaging technology of integrated circuits are also increasing. The existing packaging technologies include ball grid array packaging (BGA), chip size packaging (CSP), wafer level packaging (WLP) ), three-dimensional packaging (3D) and system in package (SiP), etc. Among them, wafer-level packaging (WLP) is gradually adopted by most semiconductor manufacturers due to its outstanding advantages. All or most of its process steps are completed on silicon wafers that have completed the previous process, and finally the wafer Direct dicing into separate individual devices. Wafer-level packaging (WLP) has its unique advantages: ① high packaging pro...

Claims

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Application Information

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IPC IPC(8): H01L21/60H01L21/56H01L23/52H01L23/31
CPCH01L21/56H01L23/31H01L23/52H01L24/10H01L24/12H01L2224/10H01L2224/12H01L21/568H01L24/96H01L2224/04105H01L2224/12105H01L2224/19H01L2924/18162H01L2924/00012
Inventor 仇月东林正忠
Owner SJ SEMICON JIANGYIN CORP
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