Multi-FPGA chip accelerator card

An accelerator card and chip technology, which is applied in the direction of instruments, electrical digital data processing, etc., can solve the problem of disproportionate power consumption and cost, and achieve the effect of computing acceleration

Active Publication Date: 2015-12-23
INSPUR BEIJING ELECTRONICS INFORMATION IND
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0003] At present, only through the expansion of the number, the improvement of computing power in many computing application scenarios is far out of proportion to the increase in power consumption and cost

Method used

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  • Multi-FPGA chip accelerator card

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Embodiment Construction

[0014] In order to make the purpose, technical solution and advantages of the present invention more clear, the embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings. It should be noted that, in the case of no conflict, the embodiments in the present application and the features in the embodiments can be combined arbitrarily with each other.

[0015] The steps shown in the flowcharts of the figures may be performed in a computer system, such as a set of computer-executable instructions. Also, although a logical order is shown in the flowcharts, in some cases the steps shown or described may be performed in an order different from that shown or described herein.

[0016] Aiming at the problem in the existing technology that the increase in computing power in many computing application scenarios is far out of proportion to the increase in power consumption and cost only through the expansion of quantity, the emergenc...

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Abstract

The invention discloses a multi-FPGA chip accelerator card. The chip accelerator card comprises a PCIE switch chip, a PCIE bus and FPGA chips, wherein the PCIE switch chip is connected to the at least one FPGA chip through the PCIE bus; the FPGA chips are connected to SODIMM slot connectors; the PCIE switch chip is further connected to a gold finger and an IO Bridge chip through the PCIE bus; an IO Bus and IO connectors are arranged on the IO Bridge chip, and the IO Bridge chip is connected to the at least one IO connector through the IO Bus; and a power switch is connected to the gold finger, and a power connector and a power conversion circuit are connected to two ends of the power switch respectively . Through the multi-FPGA chip accelerator card disclosed by the invention, the computing capacity of a system is greatly improved when same system resources are occupied.

Description

technical field [0001] The invention relates to the technical field of chip design, in particular to a multi-field-programmable gate array (FPGA, Field-Programmable Gate Array) chip acceleration card. Background technique [0002] With the rise of concepts such as cloud computing and deep learning, a new revolution has emerged in the computing field, usually through the expansion of the number of central processing units (CPU, Central Processing Unit) and graphics processing units (GPU, Graphics Processing Unit) to achieve computing power. The typical task of traditional CPU+GPU heterogeneous parallel processing is graphics real-time rendering. The CPU is responsible for highly logical transactional calculations, and the GPU is responsible for highly computationally intensive graphics rendering. The design goal of the CPU is to enable the execution unit to obtain data and instructions with a very low delay, so complex control logic and branch prediction, as well as a large ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F13/40
CPCG06F13/4027G06F2213/0024
Inventor 张斌
Owner INSPUR BEIJING ELECTRONICS INFORMATION IND
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