Sense amplifier clamping circuit with feedback function

Abstract

The invention discloses a sense amplifier clamping circuit with a feedback function. The sense amplifier clamping circuit is characterized by comprising three PMOSs, three NMOSs and a comparator, wherein the source electrode of the first PMOS is connected with a power supply; the drain electrode of the first PMOS is connected with the drain electrode of the first NMOS and a positive input end of the comparator; the reverse input end of the comparator is connected with reference voltage, and the source electrode of the first NMOS is connected with a storage unit; the grid electrode of the first PMOS is connected with a pre-charging signal; the second PMOS is in series connected with the second NMOS, the third PMOS is in series connected with the third NMOS, the source electrode of the second PMOS and the source electrode of the third PMOS are connected with the power supply; the drain electrode of the second NMOS and the drain electrode of the third NMOS are grounded; the grid electrode of the second PMOS and the grid electrode of the second NMOS are connected with the source electrode of the first NMOS; the grid electrode of the first NMOS is connected with the drain electrode of the second PMOS; the grid electrode of the third PMOS is in parallel connection with the grid electrode of the third NMOS, and then is in short connection with the drain electrode of the third PMOS; and the comparator is used for outputting a comparing signal. Two PMOSs and two NMOSs are additionally arranged on the basis of the conventional sense amplifier clamping circuit to form a self-feedback structure, so that more stable clamping voltage is provided.

Description

technical field [0001] The invention relates to the field of semiconductors, in particular to a sense amplifier clamping circuit with a feedback function. Background technique [0002] Traditional charge transfer sense amplifiers such as figure 1 Shown, including a PMOS P0 and a NMOS N0, and a comparator. While it works: [0003] Phase 1: The precharge signal voltage PRCHGB is low, VD is charged to VDD voltage, and BL is charged to VCLAMP+Vgs_n0; [0004] Phase 2: The precharge signal voltage PRCHGB is high, and p0 is turned off; [0005] Thanks to U VD *C VD =U BL *C BL , when the cell has current U BL decrease, and the cell capacitance on BL is larger, C BL >C VD . So U VD The change will start to drop from the VDD voltage, and when it is lower than VREF, the data will be read out through the comparator. [0006] However, because the cell needs to read the current normally, the BL voltage should not be too low, otherwise the current will fail to be read bec...

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