LED chip and manufacturing method thereof

Abstract

The present invention discloses an LED chip and a manufacturing method thereof, comprising a substrate, a first semiconductor layer, an active layer, a second semiconductor layer, a first electrode and a second electrode sequentially arranged on the substrate, and also comprising an exposed area and n holes, n≥2, the n holes forming a stepped structure, the diameter of the first hole to the diameter of the nth hole decreasing in sequence, the first electrode being arranged on the exposed first semiconductor layer and extending into the n holes, and the second electrode being arranged on the second semiconductor layer. The present invention increases the contact area between the first electrode and the first semiconductor layer through the n holes, so that the first electrode and the first semiconductor layer are more firmly combined, thereby improving the reliability of subsequent packaging and wiring, and improving the current expansion capability of the chip.

Description

Technical Field

[0001] The present invention relates to the technical field of light emitting diodes, and in particular to an LED chip and a manufacturing method thereof. Background Art

[0002] LED (Light Emitting Diode) is a semiconductor device that uses energy released when carriers recombine to generate light. LED chips have many advantages such as low power consumption, pure color, long life, small size, fast response time, energy saving and environmental protection.

[0003] Light-emitting diodes have now developed into a universal lighting, and the requirements for product characteristics are becoming higher and higher. The general requirements are high brightness, low voltage, and high reliability.

[0004] Figure 1 It is a schematic diagram of the structure of an existing LED chip. In an existing LED chip, the epitaxial layer is generally etched to the N-type GaN layer 23 to form an exposed area 24, and then an N electrode 31 is formed on the exposed N-type GaN layer 23. Among them, the contact surface between the N electrode 31 and the N-type GaN layer 23 is a plane, and the contact area is relatively small, which is not conducive to the expansion of current. In addition, in the subsequent packaging wire bonding, the N electrode 31 is prone to electrode drop, and the reliability is low. Summary of the invention

[0005] The technical problem to be solved by the present invention is to provide an LED chip and a manufacturing method thereof, increase the electrode contact area and bonding force, improve the current expansion capability of the chip, reduce the chip voltage, and improve the reliability of the chip.

[0006] In order to solve the above technical problems, the present invention provides an LED chip, including a substrate, a first semiconductor layer, an active layer, a second semiconductor layer, a first electrode and a second electrode arranged on the substrate in sequence, and also including an exposed area and n holes, n≥2, the exposed area is etched from the second semiconductor layer to the first semiconductor layer to expose the first semiconductor layer, the n holes are all located in the first semiconductor layer, the first hole is located below the exposed area and is connected to the exposed area, the nth hole is located below the (n-1)th hole and is connected to the (n-1)th hole, the n holes form a stepped structure, the diameters of the first hole to the nth hole decrease in sequence, the first electrode is arranged on the exposed first semiconductor layer and extends into the n holes, and the second electrode is arranged on the second semiconductor layer.

[0007] As an improvement of the above solution, the total depth of the exposed area and the n holes is 0.7-1.5 μm.

[0008] As an improvement of the above solution, the depth of the first hole is (0.06-0.1)*nμm, the depth of the second hole is (0.06-0.1)*(n-1)μm, and the depth of the nth hole is (0.06-0.1)*1μm.

[0009] As an improvement of the above solution, the depth of the first hole is 0.08*nμm, the depth of the second hole is 0.08*(n-1)μm, and the depth of the nth hole is 0.08*1μm.

[0010] As an improvement of the above solution, the side wall and the bottom of the hole form an inclined angle, and the inclined angle is 120 to 150 degrees.

[0011] As an improvement of the above scheme, the first electrode includes a first metal layer and a second metal layer, the first metal layer is arranged on the first semiconductor layer and filled in the hole, the second metal layer covers the first metal layer and wraps the exposed part of the first metal layer, and the wettability of the first metal layer is less than that of the second metal layer.

[0012] As an improvement of the above solution, the first metal layer also includes one or more metals selected from the group consisting of Cr, Al and Pt.

[0013] Accordingly, the present invention also provides a method for manufacturing an LED chip, comprising:

[0014] forming an epitaxial layer on a substrate, wherein the epitaxial layer comprises a first semiconductor layer, an active layer and a second semiconductor layer sequentially arranged on the substrate;

[0015] Etching the epitaxial layer to the first semiconductor layer to form an exposed area;

[0016] Etching the exposed first semiconductor layer to form a first hole;

[0017] Continue etching along the first hole to form the second hole;

[0018] Continue etching along the (n-1)th hole to form the nth hole, wherein the diameters of the first hole to the nth hole decrease in sequence, and the n holes form a step structure;

[0019] A first electrode is formed on the exposed first semiconductor and in the n holes, and a second electrode is formed on the second semiconductor layer.

[0020] As an improvement of the above solution, yellow light patterning and chemical etching are used to etch the epitaxial layer to form an exposed area and n holes.

[0021] As an improvement of the above solution, the chemical agent is KOH or H3PO4 solution, wherein the epitaxial layer is immersed in the etching solution at 80-90°C for 20-40 minutes.

[0022] The implementation of the present invention has the following beneficial effects:

[0023] The present invention provides an LED chip, comprising a substrate, a first semiconductor layer, an active layer, a second semiconductor layer, a first electrode and a second electrode sequentially arranged on the substrate, and also comprising an exposed area and n holes, n≥2. The first electrode of the present invention is not only combined with the exposed surface of the first semiconductor layer, but also extends into the first semiconductor layer through n holes of a stepped structure, and is combined with the interior of the first semiconductor layer.

[0024] The present invention increases the contact area between the first electrode and the first semiconductor layer by using n holes, so that the first electrode and the first semiconductor layer are more firmly combined, thereby improving the reliability of subsequent packaging wire bonding. In addition, since the contact area between the first electrode and the first semiconductor layer is increased, the current expansion performance between the two is also increased accordingly, thereby improving the current expansion performance of the entire chip, reducing the voltage of the chip, and improving the light efficiency.

[0025] The invention specially designs the structure of the first electrode to match the shape and size of the hole, so as to ensure that the first electrode can be formed in the first hole and enhance the bonding force between the two. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 It is a schematic diagram of the structure of an existing LED chip;

[0027] Figure 2 This is a schematic diagram of the structure of the LED chip of the first solution of the present invention;

[0028] Figure 3 This is a schematic diagram of the structure of the LED chip of the second solution of the present invention;

[0029] Figure 4a This is a schematic diagram of the structure of the LED chip of the first solution of the present invention after the epitaxial layer is formed;

[0030] Figure 4b This is a schematic diagram of the structure of the LED chip of the first solution of the present invention after the exposed area is formed;

[0031] Figure 4c is a schematic diagram of the structure of the LED chip of the first solution of the present invention after the first hole is formed;

[0032] Figure 4d is a schematic diagram of the structure of the LED chip of the first solution of the present invention after the second hole is formed;

[0033] Figure 4e It is a schematic diagram of the structure of the LED chip of the first solution of the present invention after the third hole is formed. DETAILED DESCRIPTION

[0034] In order to make the objectives, technical solutions and advantages of the present invention more clear, the present invention will be further described in detail below with reference to the accompanying drawings.

[0035] See also Figure 2 The present invention provides an LED chip, comprising a substrate 10, a first semiconductor layer 20, an active layer 30, a second semiconductor layer 40, a first electrode 51, a second electrode 52, an exposed area 61 and a hole 62 which are sequentially arranged on the substrate 10.

[0036] The exposed area 61 of the present invention is etched from the second semiconductor layer 40 to the first semiconductor layer 20 to expose the first semiconductor layer 20. The exposed area 61 is a preset area of ​​the first electrode 51. The existing first electrode 51 is disposed on the exposed first semiconductor layer 20.

[0037] The number of holes 62 of the present invention is n, where n≥2. The n holes 62 are all located in the first semiconductor layer 20 , that is, the holes 62 do not penetrate the first semiconductor layer 20 .

[0038] Specifically, the first hole 62 is located below the exposed area 61 and is connected to the exposed area 61. That is, the first hole 62 continues to etch the first semiconductor layer 20 along the exposed area 61. The nth hole 62 is located below the (n-1)th hole 62 and is connected to the (n-1)th hole 62. That is, the latter hole 62 continues to etch the first semiconductor layer 20 along the former hole 62.

[0039] The n holes 62 of the present invention form a stepped structure. Preferably, the diameters of the first hole 62 to the nth hole 62 decrease in sequence.

[0040] The first electrode 51 of the present invention is disposed on the exposed first semiconductor layer 20 and extends into the n holes 62 . The second electrode 52 of the present invention is disposed on the second semiconductor layer 40 .

[0041] Compared with the prior art, the first electrode of the present invention is not only combined with the exposed surface of the first semiconductor layer, but also extends into the first semiconductor layer through the holes of the n step-shaped structure and is combined with the interior of the first semiconductor layer.

[0042] The present invention increases the contact area between the first electrode and the first semiconductor layer by using n holes, so that the first electrode and the first semiconductor layer are more firmly combined, thereby improving the reliability of subsequent packaging wire bonding. In addition, since the contact area between the first electrode and the first semiconductor layer is increased, the current expansion performance between the two is also increased accordingly, thereby improving the current expansion performance of the entire chip, reducing the voltage of the chip, and improving the light efficiency.

[0043] It should be noted that the etching depth of the exposed area and the n holes has an important influence on the overall optoelectronic performance of the chip, which is related to the thickness of the first semiconductor layer, the active layer and the second semiconductor layer. Preferably, the total depth of the exposed area and the n holes is 0.7-1.5 μm.

[0044] The etching depth of each hole of the present invention is different. Preferably, the depth of the first hole is (0.06-0.1)*nμm, the depth of the second hole is (0.06-0.1)*(n-1)μm, and the depth of the nth hole is (0.06-0.1)*1μm. The etching depths of the n holes of the present invention decrease successively because the diameters of the n holes decrease successively, which facilitates etching to form holes. In addition, the closer the hole diameter and depth of the present invention are to the substrate, the smaller it is, which can avoid damage to the substrate during etching, prevent the substrate from separating from the first semiconductor layer and cracks from occurring, and ensure the overall quality of the chip.

[0045] Preferably, the depth of the first hole is 0.08*n μm, the depth of the second hole is 0.08*(n-1) μm, and the depth of the nth hole is 0.08*1 μm.

[0046] More preferably, the depth of the first hole is 0.24 μm, the depth of the second hole is 0.16 μm, and the depth of the third hole is 0.08 μm.

[0047] See also Figure 3 , Figure 3 It is a structural schematic diagram of an LED chip of another preferred embodiment of the present invention. In order to further increase the contact area between the first electrode and the first semiconductor layer, the side wall and the bottom of each hole of the present invention form an inclination angle θ. Preferably, the inclination angle θ is 120 to 150 degrees.

[0048] Since the first electrode of the present invention needs to extend into the first electrode to increase the structural strength of the two, the present invention has specially designed the structure of the first electrode to match the shape and size of the hole to ensure that the first electrode can be formed in the first hole and enhance the bonding strength of the two. Specifically, the first electrode 51 of the present invention includes a first metal layer 511 and a second metal layer 512, wherein the first metal layer 511 is disposed on the first semiconductor layer 20 and filled in the hole 62, and the second metal layer 512 covers the first metal layer 511 and wraps the exposed portion of the first metal layer 511. The wettability of the first metal layer 511 is less than that of the second metal layer 522.

[0049] Wettability is one of the important properties of the material surface, which is characterized by the static contact angle. The factors affecting wettability are mainly the chemical composition and microstructure of the material surface. The wettability of the material surface is mainly changed by surface modification and surface micro-modeling. Specifically, the metal with high wettability is not easy to shrink under high temperature, ultrasound or vacuum state; while the metal with low wettability is easy to shrink under high temperature, ultrasound or vacuum state, and metal migration occurs. Among them, when the metal with high wettability encounters the metal with low wettability during migration, it will agglomerate on the metal with low wettability, undergo secondary growth, and increase the thickness of its metal layer.

[0050] Preferably, the first metal layer 511 includes at least one or more metals selected from the group consisting of Cu, Co, Fe and Zn, which are metals with low wettability or metals without wettability. The second metal layer 512 includes at least one or more metals selected from the group consisting of Ni, Au, Ti and In, which are metals with high wettability.

[0051] When the first electrode of the present invention is under high temperature, ultrasonic or vacuum conditions, the metal of the second metal layer will migrate to the first metal layer, thereby agglomerating and undergoing secondary growth. Since the second metal layer wraps the first metal layer, the bonding force between the first metal layer and the first semiconductor layer can be strengthened when the metal agglomerates, further reducing the probability of electrode falling off and improving the reliability of the chip.

[0052] In order to further improve the current spreading performance between the first electrode and the first semiconductor layer, the first metal layer of the present invention further includes one or more metals selected from Cr, Al and Pt.

[0053] Preferably, the structure of the first metal layer is Cr / Cu / Co / Zn / Pt, Cr is used as the bottom layer, and its function is to make other metal layers better adhere to the first semiconductor layer to prevent the electrode from falling off. Pt is used as the top layer to protect the entire electrode.

[0054] The present invention further improves the bonding force between the first electrode and the first semiconductor layer by coordinating the structure of the first electrode with the structure of the n holes, thereby improving the current expansion capability of the chip.

[0055] Accordingly, the present invention also provides a method for manufacturing an LED chip, comprising the following steps:

[0056] 1. See Figure 4a , forming an epitaxial layer on the substrate 10, wherein the epitaxial layer includes a first semiconductor layer 20, an active layer 30 and a second semiconductor layer 40 which are sequentially arranged on the substrate 10;

[0057] 2. See Figure 4b , etching the epitaxial layer to the first semiconductor layer 20 to form an exposed area 61, exposing part of the first semiconductor layer 20;

[0058] 3. See also Figure 4c , etching the exposed first semiconductor layer 20 to form a first hole 62;

[0059] IV. See Figure 4d , continue etching along the first hole 62 to form the second hole 63;

[0060] 5. See Figure 4e , continue etching along the second hole 63 to form a third hole 64;

[0061] VI. See Figure 2 A first electrode 51 is formed on the exposed first semiconductor layer 20 and in the three holes, and a second electrode 52 is formed on the second semiconductor layer 40 .

[0062] It should be noted that the diameter of the first hole 62 is greater than the diameter of the second hole 63 and greater than the diameter of the third hole 64. In this embodiment, the diameters of the three holes decrease in sequence, and the three holes form a stepped structure;

[0063] Specifically, the epitaxial layer is etched by using yellow light patterning and chemical etching to form an exposed area and three holes.

[0064] In order to improve the etching speed and etching accuracy, the chemical agent of the present invention is KOH or H3PO4 solution, wherein the epitaxial layer is immersed in the etching solution at 80-90°C for 20-40 minutes.

[0065] It should be noted that the present invention can also form exposed areas and holes by an ICP etching method.

[0066] The method for manufacturing the LED chip of the present invention is simple to operate and does not require additional equipment and reagents.

[0067] The above disclosure is only a preferred embodiment of the present invention, which certainly cannot be used to limit the scope of the present invention. Therefore, equivalent changes made according to the claims of the present invention are still within the scope of the present invention.

Claims

1. An LED chip, comprising a substrate, a first semiconductor layer, an active layer, a second semiconductor layer, a first electrode and a second electrode sequentially arranged on the substrate, characterized in that: It also includes an exposed area and n holes, n≥2, the exposed area is etched from the second semiconductor layer to the first semiconductor layer to expose the first semiconductor layer, the n holes are all located in the first semiconductor layer, the first hole is located below the exposed area and is connected to the exposed area, the nth hole is located below the (n-1)th hole and is connected to the (n-1)th hole, the n holes form a step structure, the diameters of the first hole to the nth hole decrease in sequence, the first electrode is arranged on the exposed first semiconductor layer and extends into the n holes, and the second electrode is arranged on the second semiconductor layer; The first electrode includes a first metal layer and a second metal layer, the first metal layer is disposed on the first semiconductor layer and filled in the hole, the second metal layer covers the first metal layer and wraps the exposed portion of the first metal layer, and the wettability of the first metal layer is less than that of the second metal layer; The structure of the first metal layer is Cr / Cu / Co / Zn / Pt, wherein Cr is used as the bottom layer and Pt is used as the top layer; The second metal layer includes at least one or more metals selected from the group consisting of Ni, Au, Ti and In.

2. The LED chip according to claim 1, characterized in that: The total depth of the exposed area and the n holes is 0.7~1.5μm.

3. The LED chip according to claim 2, characterized in that: The depth of the first hole is (0.06~0.1)*n μm, the depth of the second hole is (0.06~0.1)*(n-1) μm, and the depth of the nth hole is (0.06~0.1)*1 μm.

4. The LED chip according to claim 3, characterized in that: The depth of the first hole is 0.08*n μm, the depth of the second hole is 0.08*(n-1) μm, and the depth of the nth hole is 0.08*1 μm.

5. The LED chip according to claim 1, characterized in that: The side wall and the bottom of the hole form an inclined angle, and the inclined angle is 120-150 degrees.

6. A method for manufacturing an LED chip according to any one of claims 1 to 5, characterized in that: include: forming an epitaxial layer on a substrate, wherein the epitaxial layer comprises a first semiconductor layer, an active layer and a second semiconductor layer sequentially arranged on the substrate; Etching the epitaxial layer to the first semiconductor layer to form an exposed area; Etching the exposed first semiconductor layer to form a first hole; Continue etching along the first hole to form the second hole; Continue etching along the (n-1)th hole to form the nth hole, wherein the diameters of the first hole to the nth hole decrease in sequence, and the n holes form a step structure; A first electrode is formed on the exposed first semiconductor and in the n holes, and a second electrode is formed on the second semiconductor layer.

7. The method for manufacturing an LED chip according to claim 6, wherein: The epitaxial layer is etched by photolithography and chemical etching to form exposed areas and n holes.

8. The method for manufacturing an LED chip according to claim 7, wherein: The chemical agent is KOH or H3PO4 solution, wherein the epitaxial layer is immersed in the corrosion solution at 80-90°C for 20-40 minutes.

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