Uplink delay adjustment method, device, base station and storage medium

Abstract

The present application relates to an uplink delay adjustment method, device, base station and storage medium. The base station receives the uplink signal sent by the user equipment UE within the current adjustment period; then, adjusts the uplink signal according to the preset processing delay calibration value Delay; wherein, the processing delay calibration value is obtained according to the historical UE timing advance TA monitored in the last adjustment period. Using the above method can reduce the fluctuation of the uplink delay of the uplink signal in the direction of negative delay, which is beneficial to improve the receiving performance of the base station, make the debugging of the base station more smooth, and reduce the debugging time and research and development costs.

Description

technical field [0001] The present application relates to the technical field of communications, and in particular to a method, device, base station and storage medium for adjusting uplink delay. Background technique [0002] At present, communication technologies based on long term evolution (long term evolution, LTE for short) or new radio (new radio, NR for short) all adopt the orthogonal multiple access technology. In order to control the time when uplink signals of different terminals (User Equipment, referred to as UE) arrive at the base station, the baseband processing unit in the base station can set the timing advance (TimingAdvance, referred to as TA) of the UE, and control the UE to send the uplink signal in advance according to the TA, so that After the uplink signal is transmitted, it arrives at the baseband processing unit at a specified time. [0003] In the actual transmission process, the uplink signal sent by the UE based on the TA will cause a propagation...

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Problems solved by technology

[0004] However, due to the difference in the consistency of the hardware boards of different base stations, there is a difference in hardware processing delay, or the processing delay and power-on delay jitter of the programmable integrated circuit (Field Programmable Gate Array, FPGA) in the fronthaul unit will cause There are fluctuations in the receiving boundary of the uplink signal, which affects the integrity of the data block, thereby degrading the demodulation and decoding performance of the data, affecting the normal reception of the uplink signal, and increasing the debugging time and R&D cost

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