Method for generating multi-fan-out clock signal facing superconducting RSFQ circuit

Abstract

The invention provides a method for generating a multi-fan-out clock signal for a superconducting RSFQ circuit, and the method comprises the steps: building an SPL tree with the height P being 1, with the SPL tree with the height P being 1 comprises a single node, an SPL2 and an SPL3, and storing the single node, the SPL2 and the SPL3 into a set R; calculating the maximum height Pmax of the SPL tree according to the N; establishing the SPL tree layer by layer, and increasing 1 to P in each iteration until P is larger than Pmax; wherein the tree with the height being P is composed of sub-trees with the height smaller than P in the set R, when the SPL tree is established every time, according to an objective function, the objective function value of the established SPL tree is compared with that of the SPL trees with the same height and the same leaf node number in the set R, and only the tree with the minimum objective function value is stored in the set R, selecting a tree with N leaf nodes in the set R to form an optimal solution; and determining a branch path formed by the SPL of the multi-fan-out clock signal according to the optimal solution.

Description

technical field [0001] The invention relates to a clock tree topology optimization method for a superconducting rapid single flux quantum (Rapid Single Flux Quantum, RSFQ) circuit, in particular to a method for generating multi-fan-out clock signals oriented to a superconducting RSFQ circuit. Background technique [0002] Superconducting single flux quantum (Single Flux Quantum, SFQ) circuit technology is listed by ITRS as a promising next-generation integrated circuit technology. Superconducting RSFQ circuit is a kind of SFQ circuit, which has ultra-high speed and ultra-low power consumption. Research has confirmed that a simple RSFQ circuit manufactured with submicron Josephson Junction (JJ) technology can work at a frequency of up to 770 GHz, which is beyond the reach of semiconductor integrated circuits. Under the same process conditions, the logic gate delay and bit operation power consumption in the RSFQ circuit are two orders of magnitude lower than that of the corre...

AI Technical Summary

Problems solved by technology

Although there have been some studies on superconducting clock tree structure optimization methods, these works generally use binary tree clock network structure, with the single optimization goal of minimizing the deviation; or can only generate clock trees with equal depth of leaf nodes, without considering all Possible Clock Tree Structures

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