OLED display panel and manufacturing method thereof

Abstract

The embodiment of the present application provides an OLED display panel and a manufacturing method thereof. The OLED display panel provided by the embodiment of the present application is provided by providing a first auxiliary electrode and a second auxiliary electrode spaced apart in a source-drain electrode layer, and providing a third auxiliary electrode above the first auxiliary electrode and the second auxiliary electrode, and using the third auxiliary electrode to cover and connect the first auxiliary electrode and the second auxiliary electrode. Since the second cathode contacts the third auxiliary electrode and the first cathode is connected to the second cathode, electrical connection between the first cathode and the first auxiliary electrode, the second auxiliary electrode, and the third auxiliary electrode can be achieved, and the problem of uneven display brightness in different areas on the OLED display panel caused by the large impedance of the first cathode can be improved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an OLED display panel and a manufacturing method thereof. Background Art

[0002] With the development of semiconductor technology, OLED (Organic Light-Emitting Diode) display panels have been widely used due to their advantages such as high brightness, low power consumption, fast response, high clarity and high luminous efficiency.

[0003] However, when a large-sized top-emitting OLED display panel is in operation, different voltage drops (IR drops) are generated at different positions of the OLED display panel because the cathode thereof has a large resistance, resulting in uneven display brightness in different areas of the OLED display panel. Summary of the invention

[0004] The embodiments of the present application provide an OLED display panel and a method for manufacturing the same, which can improve the problem of uneven display brightness in different areas of the OLED display panel caused by a large impedance of the cathode.

[0005] In a first aspect, an embodiment of the present application provides an OLED display panel, comprising:

[0006] A TFT backplane, wherein the topmost structural layer of the TFT backplane is a source-drain electrode layer, and the source-drain electrode layer includes a source electrode, a drain electrode, a first auxiliary electrode, and a second auxiliary electrode arranged at intervals;

[0007] A first conductive layer, disposed on the TFT backplane, the first conductive layer comprising a third auxiliary electrode, the third auxiliary electrode covers the first auxiliary electrode and the second auxiliary electrode, and electrically connects the first auxiliary electrode to the second auxiliary electrode;

[0008] a passivation layer, disposed on the TFT backplane and covering the source-drain electrode layer and the first conductive layer, the passivation layer being provided with a first through hole and a second through hole, the first through hole being provided corresponding to the spacing region between the first auxiliary electrode and the second auxiliary electrode, and the second through hole being provided corresponding to the source electrode;

[0009] a planar layer, disposed on a side of the passivation layer away from the TFT backplane, wherein a third through hole and a fourth through hole are disposed on the planar layer, wherein the third through hole and the first through hole are mutually interpenetrating, and the fourth through hole and the second through hole are mutually interpenetrating, and in a direction from the first auxiliary electrode to the second auxiliary electrode, a width of at least one end of the first through hole close to the third auxiliary electrode is greater than a width of the third through hole;

[0010] an anode, disposed on the planar layer, the anode being electrically connected to the source electrode via the fourth through hole and the second through hole;

[0011] A pixel definition layer, disposed on the planar layer, the pixel definition layer is provided with an opening and a sixth through hole, the sixth through hole is arranged corresponding to the third through hole, and the opening exposes the anode;

[0012] A first light-emitting layer is disposed on the pixel definition layer, and a portion of the first light-emitting layer corresponding to the opening covers the anode;

[0013] A second light-emitting layer is disposed on the third auxiliary electrode;

[0014] A first cathode, disposed on the first light-emitting layer;

[0015] The second cathode is disposed on the second light-emitting layer, the first cathode is connected to the second cathode, and the second cathode covers the second light-emitting layer and contacts the third auxiliary electrode.

[0016] In some embodiments, the first auxiliary electrode and the second auxiliary electrode are parallel to each other.

[0017] In some embodiments, a cross-sectional area of ​​the sixth through hole is greater than a cross-sectional area of ​​the third through hole.

[0018] In some embodiments, the first conductive layer further includes a protection layer spaced apart from the third auxiliary electrode, the protection layer is disposed above the source electrode, and two sides of the protection layer are electrically connected to the source electrode and the anode electrode, respectively.

[0019] In some embodiments, the TFT backplane includes a substrate, a buffer layer, a semiconductor layer, a gate insulating layer, a gate, an interlayer dielectric layer and a source and drain layer stacked in sequence, wherein the semiconductor layer includes an active layer, the active layer is arranged corresponding to the gate, the active layer includes a channel region and a source contact region and a drain contact region arranged on both sides of the channel region, a seventh through hole and an eighth through hole are provided on the interlayer dielectric layer, the source is connected to the source contact region of the active layer via the seventh through hole, and the drain is connected to the drain contact region of the active layer via the eighth through hole.

[0020] In some embodiments, the semiconductor layer also includes a first storage capacitor electrode spaced apart from the active layer; a shading layer is provided between the base substrate and the buffer layer, the shading layer is arranged corresponding to the active layer and the first storage capacitor electrode, and a storage capacitor is formed between the shading layer and the first storage capacitor electrode.

[0021] In some embodiments, a driving TFT area, a light-emitting area and an auxiliary electrode area are defined on the OLED display panel, wherein the source electrode, the drain electrode, the gate electrode, and the active layer are all arranged in the driving TFT area, the opening on the pixel definition layer and the first storage capacitor electrode are all arranged in the light-emitting area, and the first auxiliary electrode, the second auxiliary electrode and the third auxiliary electrode are all arranged in the auxiliary electrode area.

[0022] In a second aspect, an embodiment of the present application provides a method for manufacturing an OLED display panel, comprising:

[0023] Providing a TFT backplane, wherein the topmost structural layer of the TFT backplane is a source-drain electrode layer, and the source-drain electrode layer includes a source electrode, a drain electrode, a first auxiliary electrode, and a second auxiliary electrode that are spaced apart;

[0024] A first conductive layer is disposed on the TFT backplane, wherein the first conductive layer includes a third auxiliary electrode, the third auxiliary electrode covers the first auxiliary electrode and the second auxiliary electrode, and the first auxiliary electrode is electrically connected to the second auxiliary electrode;

[0025] A passivation layer covering the source-drain electrode layer and the first conductive layer is provided on the TFT backplane, and a first through hole and a second through hole are formed on the passivation layer, wherein the first through hole is provided corresponding to the spacing area between the first auxiliary electrode and the second auxiliary electrode, and the second through hole is provided corresponding to the source electrode;

[0026] A planar layer is provided on a side of the passivation layer away from the TFT back plate, and a third through hole and a fourth through hole are formed on the planar layer, wherein the third through hole is interconnected with the first through hole, and the fourth through hole is interconnected with the second through hole;

[0027] Disposing a photoresist layer on the flat layer, forming a fifth through hole on the photoresist layer, wherein the fifth through hole and the third through hole are interconnected;

[0028] Allowing etching liquid to enter the first through hole through the fifth through hole and the third through hole to etch a portion of the passivation layer located around the first through hole, so that the aperture of at least one end of the first through hole close to the third auxiliary electrode is enlarged, and in a direction from the first auxiliary electrode to the second auxiliary electrode, the width of at least one end of the first through hole close to the third auxiliary electrode is greater than the width of the third through hole;

[0029] removing the photoresist layer, and disposing an anode on the planar layer, wherein the anode is electrically connected to the source electrode via the fourth through hole and the second through hole;

[0030] A pixel definition layer covering the anode is arranged on the planar layer, an opening and a sixth through hole are formed on the pixel definition layer, the sixth through hole is arranged corresponding to the third through hole, and the opening exposes the anode;

[0031] A light-emitting material is deposited on one side of the pixel definition layer on the TFT backplane, the light-emitting material deposited on the pixel definition layer forms a first light-emitting layer, and the light-emitting material deposited on the third auxiliary electrode through the sixth through hole and the third through hole forms a second light-emitting layer, wherein a portion of the first light-emitting layer corresponding to the opening covers the anode;

[0032] A conductive material is deposited on one side of the first light-emitting layer on the TFT backplane, the conductive material deposited on the first light-emitting layer forms a first cathode, the conductive material deposited on the second light-emitting layer forms a second cathode, the first cathode is connected to the second cathode, the second cathode covers the second light-emitting layer and is in contact with the third auxiliary electrode.

[0033] In some embodiments, the first auxiliary electrode and the second auxiliary electrode are parallel to each other.

[0034] In some embodiments, a cross-sectional area of ​​the sixth through hole is greater than a cross-sectional area of ​​the third through hole.

[0035] In some embodiments, the first conductive layer further includes a protection layer spaced apart from the third auxiliary electrode, the protection layer is disposed above the source electrode, and two sides of the protection layer are electrically connected to the source electrode and the anode electrode, respectively.

[0036] In some embodiments, the first conductive layer further includes a protective layer spaced apart from the third auxiliary electrode, the protective layer is disposed above the source electrode, and the protective layer is electrically connected to the source electrode;

[0037] After the anode is disposed on the planar layer, the anode is electrically connected to a side of the protection layer away from the source electrode.

[0038] The OLED display panel provided by the embodiment of the present application is provided with a first auxiliary electrode and a second auxiliary electrode arranged at intervals in the source-drain layer, and a third auxiliary electrode is provided above the first auxiliary electrode and the second auxiliary electrode, and the first auxiliary electrode and the second auxiliary electrode are covered and connected by the third auxiliary electrode. Since the second cathode is in contact with the third auxiliary electrode and the first cathode is connected with the second cathode, the electrical connection between the first cathode and the first auxiliary electrode, the second auxiliary electrode and the third auxiliary electrode can be achieved, and the problem of uneven display brightness in different areas of the OLED display panel caused by the large impedance of the first cathode can be improved; the OLED display panel of the embodiment of the present application does not need to use a mask when preparing the first light-emitting layer and the second light-emitting layer, so the production cost of the OLED display panel can be reduced; the embodiment of the present application is provided with a first auxiliary electrode and a second auxiliary electrode arranged at intervals and a third auxiliary electrode covering the first auxiliary electrode and the second auxiliary electrode, so as to When etching is partially performed, the maximum expansion range of the first through hole in width and depth is limited, forming an undercut structure with a controllable etching range, thereby avoiding the collapse of the passivation layer caused by etching too deep or too wide; since the aperture of at least one end of the first through hole close to the third auxiliary electrode is enlarged after etching, when depositing a conductive material to prepare the first cathode and the second cathode, the conductive material can be diffused in the part of the first through hole with the enlarged aperture, so that the prepared second cathode covers the second light-emitting layer and contacts the third auxiliary electrode, thereby realizing the electrical connection between the second cathode and the third auxiliary electrode; it can be understood that since the first auxiliary electrode and the second auxiliary electrode are arranged at intervals, in the interval area between the first auxiliary electrode and the second auxiliary electrode, since there are no obstacles at both ends of the interval area, the etching of the hole wall of the first through hole will not cause undercutting, and after etching, the hole walls on the opposite sides of the first through hole facing the two ends of the interval area respectively present a slope shape, so that the second cathode can extend along the slope to connect with the first cathode. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application, and those skilled in the art can obtain other drawings based on these drawings without creative work.

[0040] Figure 1 A schematic diagram of step 100 of a method for manufacturing an OLED display panel provided in an embodiment of the present application.

[0041] Figure 2 A schematic top view of a first auxiliary electrode and a second auxiliary electrode provided in an embodiment of the present application.

[0042] Figure 3 A schematic diagram of step 200 of a method for manufacturing an OLED display panel provided in an embodiment of the present application.

[0043] Figure 4 A schematic diagram of step 300 of the method for manufacturing an OLED display panel provided in an embodiment of the present application.

[0044] Figure 5 A schematic diagram of step 400 of the method for manufacturing an OLED display panel provided in an embodiment of the present application.

[0045] Figure 6 A schematic diagram of step 500 of a method for manufacturing an OLED display panel provided in an embodiment of the present application.

[0046] Figure 7 A schematic diagram of step 600 of the method for manufacturing an OLED display panel provided in an embodiment of the present application.

[0047] Figure 8 A schematic diagram of step 700 of the method for manufacturing an OLED display panel provided in an embodiment of the present application.

[0048] Fig. 9 A schematic diagram of step 800 of a method for manufacturing an OLED display panel provided in an embodiment of the present application.

[0049] Fig.10 A schematic diagram of step 900 of a method for manufacturing an OLED display panel provided in an embodiment of the present application.

[0050] Fig.11 A schematic top view of an OLED display panel provided in an embodiment of the present application.

[0051] Fig.12 for Fig.11 The cross-sectional schematic diagram of the OLED display panel shown is along the AA direction.

[0052] Fig.13 for Fig.11 The cross-sectional schematic diagram of the OLED display panel shown in the BB direction. DETAILED DESCRIPTION

[0053] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0054] See also Figures 1 to 13 The present application provides a method for manufacturing an OLED display panel, comprising:

[0055] S100, see Figure 1 , providing a TFT backplane 200 , wherein the topmost structural layer in the TFT backplane 200 is a source-drain electrode layer, and the source-drain electrode layer includes a source electrode 71 , a drain electrode 72 , a first auxiliary electrode 73 and a second auxiliary electrode 74 which are arranged at intervals.

[0056] See also Figure 2 , Figure 2 The schematic top view of the first auxiliary electrode and the second auxiliary electrode provided in the embodiment of the present application. The first auxiliary electrode 73 and the second auxiliary electrode 74 may be parallel to each other. In some other embodiments, the first auxiliary electrode 73 and the second auxiliary electrode 74 may also be non-parallel.

[0057] Exemplarily, the first auxiliary electrode 73 and the second auxiliary electrode 74 may each independently be in a straight line shape, a curved line shape, a folded line shape, an irregular shape, or the like.

[0058] Please combine Figure 1 The TFT backplane 200 may include a base substrate 10, a buffer layer 20, a semiconductor layer, a gate insulating layer 40, a gate 50, an interlayer dielectric layer 60 and a source-drain layer stacked in sequence, wherein the semiconductor layer includes an active layer 31, the active layer 31 is arranged corresponding to the gate 50, the active layer 31 includes a channel region 312 and a source contact region 311 and a drain contact region 313 arranged on both sides of the channel region 312, a seventh through hole 67 and an eighth through hole 68 are provided on the interlayer dielectric layer 60, the source electrode 71 is connected to the source contact region 311 of the active layer 31 via the seventh through hole 67, and the drain electrode 72 is connected to the drain contact region 313 of the active layer 31 via the eighth through hole 68.

[0059] like Figure 1 As shown, in some embodiments, the TFT (Thin Film Transistor) in the TFT backplane 200 may be a top-gate TFT. It is understandable that in other embodiments, the TFT in the TFT backplane 200 may also be a bottom-gate TFT.

[0060] Please combine Figure 1 The semiconductor layer may further include a first storage capacitor electrode 32 spaced apart from the active layer 31; a light shielding layer 80 is provided between the base substrate 10 and the buffer layer 20, and the light shielding layer 80 is provided corresponding to the active layer 31 and the first storage capacitor electrode 32, and a storage capacitor is formed between the light shielding layer 80 and the first storage capacitor electrode 32.

[0061] Exemplarily, the base substrate 10 may be a rigid substrate or a flexible substrate. The material of the rigid substrate may be glass, and the material of the flexible substrate may be a polymer (eg, polyimide, etc.).

[0062] For example, the material of the buffer layer 20, the material of the gate insulating layer 40, and the material of the interlayer dielectric layer 60 can be independently selected from silicon nitride (SiN x ), silicon oxide (SiO x ) and silicon oxynitride (SiO x N y )

[0063] In some embodiments, the material of the semiconductor layer may be an oxide semiconductor material, such as indium zinc oxide (IZO), indium gallium oxide (IGO), indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), indium gallium zinc tin oxide (IGZTO), etc. In other embodiments, the material of the semiconductor layer may also be amorphous silicon, single crystal silicon, low temperature polysilicon, etc.

[0064] Exemplarily, the source contact region 311 , the drain contact region 313 and the first storage capacitor electrode 32 of the active layer 31 are all ion-doped regions with conductor properties; the channel region 312 is a non-doped region with semiconductor properties.

[0065] Exemplarily, the material of the gate 50 and the material of the source and drain layers can be independently selected from one or more of metals, alloys and metal nitrides, such as aluminum (Al), silver (Ag), tungsten (W), copper (Cu), nickel (Ni), chromium (Cr), molybdenum (Mo), titanium (Ti), platinum (Pt), tantalum (Ta) and neodymium (Nd) and other metals, alloys or nitrides of the above metals, and these materials can be used alone or in combination.

[0066] S200, see Figure 3 A first conductive layer is disposed on the TFT backplane 200 , and the first conductive layer includes a third auxiliary electrode 110 . The third auxiliary electrode 110 covers the first auxiliary electrode 73 and the second auxiliary electrode 74 , and electrically connects the first auxiliary electrode 73 and the second auxiliary electrode 74 .

[0067] Please combine Figure 3 The first conductive layer may further include a protective layer 120 spaced apart from the third auxiliary electrode 110. The protective layer 120 is disposed above the source electrode 71, and the protective layer 120 is electrically connected to the source electrode 71. By providing the protective layer 120, the corrosion resistance of the source electrode 71 can be improved, thereby preventing the surface of the source electrode 71 from being corroded during the subsequent etching process of forming the second through hole 132 on the passivation layer 130.

[0068] Exemplarily, the material of the first conductive layer can be selected from one or more of metals, alloys and metal nitrides, such as metals such as aluminum (Al), silver (Ag), tungsten (W), copper (Cu), nickel (Ni), chromium (Cr), molybdenum (Mo), titanium (Ti), platinum (Pt), tantalum (Ta) and neodymium (Nd), alloys or nitrides of the above metals, and these materials can be used alone or in combination.

[0069] S300, see Figure 4 A passivation layer 130 covering the source and drain electrode layers and the first conductive layer is disposed on the TFT backplane 200 , and a first through hole 131 and a second through hole 132 are formed on the passivation layer 130 . The first through hole 131 is disposed corresponding to the spacing area between the first auxiliary electrode 73 and the second auxiliary electrode 74 , and the second through hole 132 is disposed corresponding to the source electrode 71 .

[0070] For example, the material of the passivation layer 130 may be selected from silicon nitride (SiN x ), silicon oxide (SiO x ) and silicon oxynitride (SiO x N y )

[0071] S400, see Figure 5 A planar layer 140 is disposed on the side of the passivation layer 130 away from the TFT back plate 200 , and a third through hole 143 and a fourth through hole 144 are formed on the planar layer 140 . The third through hole 143 is interconnected with the first through hole 131 , and the fourth through hole 144 is interconnected with the second through hole 132 .

[0072] In some embodiments, the material of the planar layer 140 may be an organic material; in other embodiments, the planar layer 140 is a composite layer formed by alternating organic material layers and inorganic material layers.

[0073] S500, see Figure 6 A photoresist layer 150 is disposed on the planar layer 140 , and a fifth through hole 155 is formed on the photoresist layer 150 . The fifth through hole 155 and the third through hole 143 are interconnected.

[0074] For example, the fifth through hole 155 may be formed on the photoresist layer 150 by using an exposure and development method.

[0075] Please combine Figure 6 The cross-sectional area of ​​the fifth through hole 155 may be larger than the cross-sectional area of ​​the third through hole 143 , so that the etching liquid can more easily enter the third through hole 143 and then enter the first through hole 131 in the subsequent step S600 .

[0076] S600, see Figure 7, the etching liquid enters the first through hole 131 through the fifth through hole 155 and the third through hole 143, etches the portion of the passivation layer 130 located around the first through hole 131, so that the aperture of at least one end of the first through hole 131 close to the third auxiliary electrode 110 is enlarged, and in the direction from the first auxiliary electrode 73 to the second auxiliary electrode 74, the width of at least one end of the first through hole 131 close to the third auxiliary electrode 110 is greater than the width of the third through hole 143.

[0077] It should be noted that, since the first auxiliary electrode 73 and the second auxiliary electrode 74 are arranged at intervals, the first through hole 131 roughly has two sides facing the first auxiliary electrode 73 and the second auxiliary electrode 74 respectively and two opposite sides facing the two ends of the interval area between the first auxiliary electrode 73 and the second auxiliary electrode 74 respectively, wherein, since the first auxiliary electrode 73 and the second auxiliary electrode 74 are in the shape of strip-shaped protrusions, the range in which the hole wall of the first through hole 131 extends toward the first auxiliary electrode 73 and the second auxiliary electrode 74 respectively during etching is limited, thereby forming an undercut structure, and in the interval area between the first auxiliary electrode 73 and the second auxiliary electrode 74, since obstacles similar to the first auxiliary electrode 73 and the second auxiliary electrode 74 are not set at both ends of the interval area, the etching of the hole wall of the first through hole 131 will not have an undercut structure, but will form a slope shape according to the normal etching process.

[0078] like Figure 7 As shown, in some embodiments, only the aperture of the first through hole 131 near the third auxiliary electrode 110 is enlarged, and the aperture of the end near the flat layer 140 remains unchanged or changes slightly. In other embodiments, the aperture of the first through hole 131 from the end near the third auxiliary electrode 110 to the end near the flat layer 140 can be enlarged.

[0079] It can be understood that the embodiment of the present application sets the first auxiliary electrode 73 and the second auxiliary electrode 74 that are spaced apart and the third auxiliary electrode 110 that covers the first auxiliary electrode 73 and the second auxiliary electrode 74, so that when the portion of the passivation layer 130 located around the first through hole 131 is etched, the maximum expansion range of the first through hole 131 in width and depth is limited, forming an undercut structure with a controllable etching range, thereby avoiding the collapse of the passivation layer 130 due to excessive etching depth and width.

[0080] S700, see Figure 8 , remove the photoresist layer 150 , and set an anode 160 on the planar layer 140 . The anode 160 is electrically connected to the source electrode 71 via the fourth through hole 144 and the second through hole 132 .

[0081] Exemplarily, when the first conductive layer also includes a protective layer 120 spaced apart from the third auxiliary electrode 110, the anode 160 is electrically connected to a side of the protective layer 120 away from the source 71. Since the side of the protective layer 120 away from the anode 160 is electrically connected to the source 71, electrical connection between the anode 160 and the source 71 can be achieved.

[0082] S800, see Fig. 9 A pixel definition layer 170 covering the anode 160 is disposed on the planar layer 140 , and an opening 171 and a sixth through hole 176 are formed on the pixel definition layer 170 . The sixth through hole 176 is disposed corresponding to the third through hole 143 , and the opening 171 exposes the anode 160 .

[0083] Please combine Fig. 9 , the cross-sectional area of ​​the sixth through hole 176 may be greater than the cross-sectional area of ​​the third through hole 143 to facilitate the subsequent deposition of the conductive material, and the conductive material may enter the third through hole 143 more easily, and then pass through the third through hole 143 into the first through hole 131. Exemplarily, in the direction from the first auxiliary electrode 73 to the second auxiliary electrode 74, the width of the sixth through hole 176 may be greater than the width of the third through hole 143. It should be noted that in the embodiment of the present application, the cross-sectional area refers to the area of ​​the cross section obtained by cutting in a direction parallel to the substrate 10.

[0084] By way of example, the material of the anode 160 may be a transparent conductive metal oxide, such as indium tin oxide (ITO).

[0085] S900, see Fig.10 A light-emitting material is deposited on one side of a pixel definition layer 170 on the TFT backplane 200, and the light-emitting material deposited on the pixel definition layer 170 forms a first light-emitting layer 181. The light-emitting material deposited on the third auxiliary electrode 110 through the sixth through hole 176 and the third through hole 143 forms a second light-emitting layer 182, wherein a portion of the first light-emitting layer 181 corresponding to the opening 171 covers the anode 160.

[0086] For example, the light emitting material may be deposited on the side of the TFT backplane 200 where the pixel definition layer 170 is disposed by evaporation or inkjet printing.

[0087] It should be noted that, in the embodiment of the present application, no mask is required when preparing the first light-emitting layer 181 and the second light-emitting layer 182 , and thus the manufacturing cost of the OLED display panel 100 can be reduced.

[0088] S1000, see Figures 11 to 13A conductive material is deposited on one side of a first light-emitting layer 181 on the TFT backplane 200, the conductive material deposited on the first light-emitting layer 181 forms a first cathode 191, and the conductive material deposited on the second light-emitting layer 182 forms a second cathode 192, the first cathode 191 is connected to the second cathode 192, the second cathode 192 covers the second light-emitting layer 182 and contacts the third auxiliary electrode 110.

[0089] For example, the conductive material may be deposited on the side of the TFT backplane 200 where the first light emitting layer 181 is disposed by evaporation or sputtering.

[0090] Exemplarily, the material of the cathode may be a metal or an alloy, such as silver or a magnesium-silver alloy. It is understood that the cathode has a light-transmitting property so that the light emitted by the light-emitting layer can be emitted through the cathode, that is, the OLED display panel 100 provided in the embodiment of the present application is a top-emitting OLED display panel. Exemplarily, the light transmittance of the cathode is above 30%, such as 30%, 40%, 50%, 60%, 70%, 80%, 90%, 95%, 99%, etc.

[0091] Fig.11 A schematic top view of an OLED display panel provided in an embodiment of the present application, Fig.12 for Fig.11 The schematic cross-sectional view of the OLED display panel shown in the AA direction, Fig.13 for Fig.11 The cross-sectional view of the OLED display panel shown in FIG. Figures 11 to 13 It can be seen that the AA direction is the direction from the first auxiliary electrode 73 to the second auxiliary electrode 74, and the BB direction is perpendicular to the AA direction, that is, the BB direction is the direction perpendicular to the direction from the first auxiliary electrode 73 to the second auxiliary electrode 74. Fig.13 It is a cross-sectional schematic diagram obtained by cutting the OLED display panel 100 along the BB direction in the spacing area between the first auxiliary electrode 73 and the second auxiliary electrode 74. It can be seen that in the BB direction, the hole wall of the first through hole 131 presents a slope shape, so that the second cathode 192 can extend along the slope to connect with the first cathode 191.

[0092] Please combine Fig.12 A driving TFT area, a light-emitting area and an auxiliary electrode area can be defined on the OLED display panel 100, wherein the source electrode 71, the drain electrode 72, the gate electrode 50 and the active layer 31 are all arranged in the driving TFT area, the opening 171 on the pixel definition layer 170 and the first storage capacitor electrode 32 are all arranged in the light-emitting area, and the first auxiliary electrode 73, the second auxiliary electrode 74 and the third auxiliary electrode 110 are all arranged in the auxiliary electrode area.

[0093] It can be understood that a TFT device is arranged in the driving TFT area, and the light-emitting layer in the light-emitting area can emit light when driven by the voltage between the anode 160 and the first cathode 191, so that the OLED display panel 100 can display the picture. The first auxiliary electrode 73, the second auxiliary electrode 74 and the third auxiliary electrode 110 are arranged in the auxiliary electrode area, which can reduce the impedance of the first cathode 191, so that the display brightness of different areas on the OLED display panel 100 is uniform, thereby improving the uniformity of the picture.

[0094] Exemplarily, a ninth through hole 90 is provided on the interlayer dielectric layer 60 and the buffer layer 20 , and the source electrode 71 is connected to the light shielding layer 80 via the ninth through hole 90 , which can improve the electrical performance of the TFT and make the channel current more stable.

[0095] In summary, the manufacturing method of the OLED display panel provided in the embodiment of the present application is to provide a first auxiliary electrode 73 and a second auxiliary electrode 74 spaced apart in the source and drain layer, and to provide a third auxiliary electrode 110 above the first auxiliary electrode 73 and the second auxiliary electrode 74, and to cover and connect the first auxiliary electrode 73 and the second auxiliary electrode 74 with the third auxiliary electrode 110, and then to prepare the first cathode 191 and the second cathode 192, because the second cathode 192 is in contact with the third auxiliary electrode 110, the first cathode 191 is connected to the second cathode 192, so that the first cathode 191 and the first auxiliary electrode 110 can be connected. The electrical connection between the auxiliary electrode 73, the second auxiliary electrode 74, and the third auxiliary electrode 110 can improve the problem of uneven display brightness in different areas of the OLED display panel 100 caused by the large impedance of the first cathode 191; the embodiment of the present application does not need to use a mask when preparing the first light-emitting layer 181 and the second light-emitting layer 182, so the production cost of the OLED display panel 100 can be reduced; the embodiment of the present application arranges the first auxiliary electrode 73 and the second auxiliary electrode 74 arranged at intervals and the third auxiliary electrode 110 covering the first auxiliary electrode 73 and the second auxiliary electrode 74, so as to When etching the portion of the passivation layer 130 around the first through hole 131, the maximum expansion range of the first through hole 131 in width and depth is limited, forming an undercut structure with a controllable etching range, thereby avoiding the collapse of the passivation layer 130 due to excessive etching depth and width; since the aperture of at least one end of the first through hole 131 close to the third auxiliary electrode 110 is enlarged after etching, when depositing a conductive material to prepare the first cathode 191 and the second cathode 192, the conductive material can be diffused in the enlarged aperture portion of the first through hole 131, so that the prepared second cathode 192 covers the second light-emitting layer 182 and is in contact with the second auxiliary electrode 110. The third auxiliary electrode 110 contacts, thereby realizing electrical connection between the second cathode 192 and the third auxiliary electrode 110; it can be understood that since the first auxiliary electrode 73 and the second auxiliary electrode 74 are arranged at intervals, in the interval area between the first auxiliary electrode 73 and the second auxiliary electrode 74, since there are no obstacles at both ends of the interval area, the etching of the hole wall of the first through hole 131 will not cause undercutting. After etching, the hole walls on the opposite sides of the first through hole 131 facing the two ends of the interval area respectively present a slope shape, so that the second cathode 192 can extend along the slope to connect with the first cathode 191.

[0096] Please combine Fig.12 and Fig.13The embodiment of the present application also provides an OLED display panel 100, which can be manufactured using the manufacturing method of the OLED display panel in any of the above embodiments. The OLED display panel 100 may include a TFT backplane 200, a first conductive layer, a passivation layer 130, a flat layer 140, an anode 160, a pixel definition layer 170, a first light-emitting layer 181, a second light-emitting layer 182, a first cathode 191 and a second cathode 192.

[0097] The topmost structural layer in the TFT backplane 200 is a source-drain electrode layer, which includes a source electrode 71 , a drain electrode 72 , a first auxiliary electrode 73 and a second auxiliary electrode 74 that are spaced apart.

[0098] The first conductive layer is disposed on the TFT backplane 200 . The first conductive layer includes a third auxiliary electrode 110 . The third auxiliary electrode 110 covers the first auxiliary electrode 73 and the second auxiliary electrode 74 , and electrically connects the first auxiliary electrode 73 and the second auxiliary electrode 74 .

[0099] The passivation layer 130 is disposed on the TFT backplane 200 and covers the source and drain electrode layer and the first conductive layer. The passivation layer 130 is provided with a first through hole 131 and a second through hole 132. The first through hole 131 is arranged corresponding to the spacing area between the first auxiliary electrode 73 and the second auxiliary electrode 74, and the second through hole 132 is arranged corresponding to the source electrode 71.

[0100] The flat layer 140 is disposed on a side of the passivation layer 130 away from the TFT backplane 200. A third through hole 143 and a fourth through hole 144 are disposed on the flat layer 140. The third through hole 143 and the first through hole 131 are interconnected, and the fourth through hole 144 and the second through hole 132 are interconnected. In the direction from the first auxiliary electrode 73 to the second auxiliary electrode 74, the width of at least one end of the first through hole 131 close to the third auxiliary electrode 110 is greater than the width of the third through hole 143.

[0101] The anode 160 is disposed on the planar layer 140 , and the anode 160 is electrically connected to the source 71 via the fourth through hole 144 and the second through hole 132 .

[0102] The pixel definition layer 170 is disposed on the planar layer 140 . The pixel definition layer 170 is provided with an opening 171 and a sixth through hole 176 . The sixth through hole 176 is disposed corresponding to the third through hole 143 . The opening 171 exposes the anode 160 .

[0103] The first light-emitting layer 181 is disposed on the pixel definition layer 170 , and a portion of the first light-emitting layer 181 corresponding to the opening 171 covers the anode 160 ; the second light-emitting layer 182 is disposed on the third auxiliary electrode 110 .

[0104] The first cathode 191 is disposed on the first light emitting layer 181 ; the second cathode 192 is disposed on the second light emitting layer 182 , the first cathode 191 is connected to the second cathode 192 , and the second cathode 192 covers the second light emitting layer 182 and contacts the third auxiliary electrode 110 .

[0105] Please combine Figure 2 , the first auxiliary electrode 73 and the second auxiliary electrode 74 may be parallel to each other.

[0106] Please combine Fig. 9 The cross-sectional area of ​​the sixth through hole 176 may be larger than the cross-sectional area of ​​the third through hole 143 to facilitate the subsequent deposition of the conductive material, so that the conductive material can more easily enter the third through hole 143 and then pass through the third through hole 143 into the first through hole 131. For example, in the direction from the first auxiliary electrode 73 to the second auxiliary electrode 74, the width of the sixth through hole 176 may be larger than the width of the third through hole 143. Fig.12 The first conductive layer may further include a protective layer 120 spaced apart from the third auxiliary electrode 110 . The protective layer 120 is disposed above the source electrode 71 . Both sides of the protective layer 120 are electrically connected to the source electrode 71 and the anode 160 , respectively.

[0107] Please combine Fig.12 The TFT backplane 200 may include a base substrate 10, a buffer layer 20, a semiconductor layer, a gate insulating layer 40, a gate 50, an interlayer dielectric layer 60 and a source-drain layer stacked in sequence, wherein the semiconductor layer includes an active layer 31, the active layer 31 is arranged corresponding to the gate 50, the active layer 31 includes a channel region 312 and a source contact region 311 and a drain contact region 313 arranged on both sides of the channel region 312, a seventh through hole 67 and an eighth through hole 68 are provided on the interlayer dielectric layer 60, the source electrode 71 is connected to the source contact region 311 of the active layer 31 via the seventh through hole 67, and the drain electrode 72 is connected to the drain contact region 313 of the active layer 31 via the eighth through hole 68.

[0108] Please combine Fig.12 The semiconductor layer may further include a first storage capacitor electrode 32 spaced apart from the active layer 31; a light shielding layer 80 is provided between the base substrate 10 and the buffer layer 20, and the light shielding layer 80 is provided corresponding to the active layer 31 and the first storage capacitor electrode 32, and a storage capacitor is formed between the light shielding layer 80 and the first storage capacitor electrode 32.

[0109] Please combine Fig.12A driving TFT area, a light-emitting area and an auxiliary electrode area can be defined on the OLED display panel 100, wherein the source electrode 71, the drain electrode 72, the gate electrode 50 and the active layer 31 are all arranged in the driving TFT area, the opening 171 on the pixel definition layer 170 and the first storage capacitor electrode 32 are all arranged in the light-emitting area, and the first auxiliary electrode 73, the second auxiliary electrode 74 and the third auxiliary electrode 110 are all arranged in the auxiliary electrode area.

[0110] The above is a detailed introduction to the OLED display panel and its manufacturing method provided by the embodiment of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the present application. At the same time, for those skilled in the art, according to the idea of ​​the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. An OLED display panel, characterized in that: include: A TFT backplane, wherein the topmost structural layer of the TFT backplane is a source-drain electrode layer, and the source-drain electrode layer includes a source electrode, a drain electrode, a first auxiliary electrode, and a second auxiliary electrode arranged at intervals; A first conductive layer, disposed on the TFT backplane, the first conductive layer comprising a third auxiliary electrode, the third auxiliary electrode covers the first auxiliary electrode and the second auxiliary electrode, and electrically connects the first auxiliary electrode to the second auxiliary electrode; a passivation layer, disposed on the TFT backplane and covering the source-drain electrode layer and the first conductive layer, the passivation layer being provided with a first through hole and a second through hole, the first through hole being provided corresponding to the spacing region between the first auxiliary electrode and the second auxiliary electrode, and the second through hole being provided corresponding to the source electrode; a planar layer, disposed on a side of the passivation layer away from the TFT backplane, wherein a third through hole and a fourth through hole are disposed on the planar layer, wherein the third through hole and the first through hole are mutually interpenetrating, and the fourth through hole and the second through hole are mutually interpenetrating, and in a direction from the first auxiliary electrode to the second auxiliary electrode, a width of at least one end of the first through hole close to the third auxiliary electrode is greater than a width of the third through hole; an anode, disposed on the planar layer, the anode being electrically connected to the source electrode via the fourth through hole and the second through hole; A pixel definition layer, disposed on the planar layer, the pixel definition layer is provided with an opening and a sixth through hole, the sixth through hole is arranged corresponding to the third through hole, and the opening exposes the anode; A first light-emitting layer is disposed on the pixel definition layer, and a portion of the first light-emitting layer corresponding to the opening covers the anode; A second light-emitting layer is disposed on the third auxiliary electrode; A first cathode, disposed on the first light-emitting layer; The second cathode is disposed on the second light-emitting layer, the first cathode is connected to the second cathode, and the second cathode covers the second light-emitting layer and contacts the third auxiliary electrode.

2. The OLED display panel according to claim 1, characterized in that: The first auxiliary electrode and the second auxiliary electrode are parallel to each other.

3. The OLED display panel according to claim 1, characterized in that: A cross-sectional area of ​​the sixth through hole is greater than a cross-sectional area of ​​the third through hole.

4. The OLED display panel according to claim 1, characterized in that: The first conductive layer further includes a protection layer spaced apart from the third auxiliary electrode, the protection layer is disposed above the source electrode, and two sides of the protection layer are electrically connected to the source electrode and the anode electrode respectively.

5. The OLED display panel according to any one of claims 1 to 4, characterized in that: The TFT backplane includes a substrate, a buffer layer, a semiconductor layer, a gate insulating layer, a gate, an interlayer dielectric layer and a source-drain layer stacked in sequence, wherein the semiconductor layer includes an active layer, the active layer is arranged corresponding to the gate, the active layer includes a channel region and a source contact region and a drain contact region arranged on both sides of the channel region, a seventh through hole and an eighth through hole are provided on the interlayer dielectric layer, the source is connected to the source contact region of the active layer via the seventh through hole, and the drain is connected to the drain contact region of the active layer via the eighth through hole.

6. The OLED display panel according to claim 5, characterized in that: The semiconductor layer also includes a first storage capacitor electrode spaced apart from the active layer; a shading layer is provided between the base substrate and the buffer layer, the shading layer is arranged corresponding to the active layer and the first storage capacitor electrode, and a storage capacitor is formed between the shading layer and the first storage capacitor electrode.

7. The OLED display panel according to claim 6, characterized in that: The OLED display panel is defined with a driving TFT area, a light-emitting area and an auxiliary electrode area, wherein the source electrode, the drain electrode, the gate electrode and the active layer are all arranged in the driving TFT area, the opening on the pixel definition layer and the first storage capacitor electrode are all arranged in the light-emitting area, and the first auxiliary electrode, the second auxiliary electrode and the third auxiliary electrode are all arranged in the auxiliary electrode area.

8. A method for manufacturing an OLED display panel, characterized in that: include: Providing a TFT backplane, wherein the topmost structural layer of the TFT backplane is a source-drain electrode layer, and the source-drain electrode layer includes a source electrode, a drain electrode, a first auxiliary electrode, and a second auxiliary electrode that are spaced apart; A first conductive layer is disposed on the TFT backplane, wherein the first conductive layer includes a third auxiliary electrode, the third auxiliary electrode covers the first auxiliary electrode and the second auxiliary electrode, and the first auxiliary electrode is electrically connected to the second auxiliary electrode; A passivation layer covering the source-drain electrode layer and the first conductive layer is provided on the TFT backplane, and a first through hole and a second through hole are formed on the passivation layer, wherein the first through hole is provided corresponding to the spacing area between the first auxiliary electrode and the second auxiliary electrode, and the second through hole is provided corresponding to the source electrode; A planar layer is provided on a side of the passivation layer away from the TFT back plate, and a third through hole and a fourth through hole are formed on the planar layer, wherein the third through hole is interconnected with the first through hole, and the fourth through hole is interconnected with the second through hole; Disposing a photoresist layer on the flat layer, forming a fifth through hole on the photoresist layer, wherein the fifth through hole and the third through hole are interconnected; Allowing etching liquid to enter the first through hole through the fifth through hole and the third through hole to etch a portion of the passivation layer located around the first through hole, so that the aperture of at least one end of the first through hole close to the third auxiliary electrode is enlarged, and in a direction from the first auxiliary electrode to the second auxiliary electrode, the width of at least one end of the first through hole close to the third auxiliary electrode is greater than the width of the third through hole; removing the photoresist layer, and disposing an anode on the planar layer, wherein the anode is electrically connected to the source electrode via the fourth through hole and the second through hole; A pixel definition layer covering the anode is arranged on the planar layer, an opening and a sixth through hole are formed on the pixel definition layer, the sixth through hole is arranged corresponding to the third through hole, and the opening exposes the anode; A light-emitting material is deposited on one side of the pixel definition layer on the TFT backplane, the light-emitting material deposited on the pixel definition layer forms a first light-emitting layer, and the light-emitting material deposited on the third auxiliary electrode through the sixth through hole and the third through hole forms a second light-emitting layer, wherein a portion of the first light-emitting layer corresponding to the opening covers the anode; A conductive material is deposited on one side of the first light-emitting layer on the TFT backplane, the conductive material deposited on the first light-emitting layer forms a first cathode, the conductive material deposited on the second light-emitting layer forms a second cathode, the first cathode is connected to the second cathode, the second cathode covers the second light-emitting layer and is in contact with the third auxiliary electrode.

9. The method for manufacturing an OLED display panel according to claim 8, characterized in that: The first auxiliary electrode and the second auxiliary electrode are parallel to each other.

10. The method for manufacturing an OLED display panel according to claim 8, characterized in that: A cross-sectional area of ​​the sixth through hole is greater than a cross-sectional area of ​​the third through hole.

11. The method for manufacturing an OLED display panel according to claim 8, characterized in that: The first conductive layer further comprises a protective layer spaced apart from the third auxiliary electrode, the protective layer is disposed above the source electrode, and the protective layer is electrically connected to the source electrode; After the anode is disposed on the planar layer, the anode is electrically connected to a side of the protection layer away from the source electrode.

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