Display substrate and manufacturing method thereof, and display device

Abstract

A display substrate and a method for preparing the same, and a display device. The display substrate includes a driving structure layer disposed on a substrate, the driving structure layer includes a pixel driving circuit, the pixel driving circuit includes at least a first type transistor and a second type transistor, the first type transistor includes at least a first active layer, and the second type transistor includes at least a second active layer; the first active layer includes a first channel region and first source-drain connection regions located on both sides of the first channel region, the second active layer includes a second channel region and second source-drain connection regions located on both sides of the second channel region; the resistivity of the first active layer corresponding to the first source-drain connection region is different from the resistivity of the second active layer corresponding to the second source-drain connection region.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of display technology, and in particular, to a display substrate and a method for preparing the same, and a display device. Background Art

[0002] Among the display substrates of Organic Light Emitting Diode (OLED), the most widely used one is Low Temperature Poly-silicon (LTPS) display substrate. In the LTPS backplane, all thin film transistors (TFT) are prepared by LTPS process, and the obtained transistors have high mobility and good stability, which ensures the display effect of the display device at high resolution (Pixels Per Inch, PPI).

[0003] The inventors of the present application have found through research that in the LTPS display substrate, the leakage current of the transistor is relatively large, and the power consumption of the display substrate is relatively large. Summary of the invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] The embodiments of the present disclosure provide a display substrate and a method for manufacturing the same, and a display device to solve the problem of large leakage current of transistors in the existing LTPS display substrate.

[0006] In a first aspect, an embodiment of the present disclosure provides a display substrate, comprising a driving structure layer arranged on a substrate, the driving structure layer comprising a pixel driving circuit, the pixel driving circuit comprising at least a first type transistor and a second type transistor, the first type transistor comprising at least a first active layer, and the second type transistor comprising at least a second active layer; the first active layer comprising a first channel region and a first source-drain connection region located on both sides of the first channel region, the second active layer comprising a second channel region and a second source-drain connection region located on both sides of the second channel region; the resistivity of the first active layer corresponding to the first source-drain connection region is different from the resistivity of the second active layer corresponding to the second source-drain connection region.

[0007] In an exemplary embodiment, the first type transistor is a driving transistor, the second type transistor is a switching transistor, and the resistivity of the first active layer corresponding to the first source-drain connection region is lower than the resistivity of the second active layer corresponding to the second source-drain connection region.

[0008] In an exemplary embodiment, the resistivity of the first active layer corresponding to the first source-drain connection region is: 1E-4Ω〃cm to 1E-1Ω〃cm; the resistivity of the second active layer corresponding to the second source-drain connection region is: 1E-1Ω〃cm to 1E2Ω〃cm.

[0009] In an exemplary embodiment, the first active layer corresponding to the first source-drain connection region and the second active layer corresponding to the second source-drain connection region both contain doped N-type ions, and the N-type ion content of the first active layer corresponding to the first source-drain connection region is higher than the N-type ion content of the second active layer corresponding to the second source-drain connection region.

[0010] In an exemplary embodiment, the content of N-type ions in the first active layer corresponding to the first source-drain connection region is 1E18 cm -3 To 1E21cm -3 The content of N-type ions in the second active layer corresponding to the second source-drain connection region is 1E15cm -3 To 1E18cm -3 .

[0011] In an exemplary embodiment, the N-type ions include one or more of the following ions: phosphorus ions, nitrogen ions, arsenic ions, and antimony ions.

[0012] In an exemplary embodiment, the first active layer corresponding to the first source-drain connection region and the second active layer corresponding to the second source-drain connection region both contain doped P-type ions, and the P-type ion content of the first active layer corresponding to the first source-drain connection region is higher than the P-type ion content of the second active layer corresponding to the second source-drain connection region.

[0013] In an exemplary embodiment, the content of P-type ions in the first active layer corresponding to the first source-drain connection region is 1E18 cm -3 To 1E21cm -3 The content of P-type ions in the second active layer corresponding to the second source-drain connection region is 1E15cm -3 To 1E18cm -3 .

[0014] In an exemplary embodiment, the P-type ions include one or more of the following ions: boron ions, aluminum ions, gallium ions, and indium ions.

[0015] In a second aspect, an embodiment of the present disclosure provides a display device, comprising the display substrate as described above.

[0016] In a third aspect, an embodiment of the present disclosure provides a method for preparing a display substrate, comprising: forming a driving structure layer on a substrate, the driving structure layer comprising a pixel driving circuit, the pixel driving circuit comprising at least a first type transistor and a second type transistor, the first type transistor comprising at least a first active layer, and the second type transistor comprising at least a second active layer; the first active layer comprising a first channel region and a first source-drain connection region located on both sides of the first channel region, the second active layer comprising a second channel region and a second source-drain connection region located on both sides of the second channel region; the resistivity of the first active layer corresponding to the first source-drain connection region is different from the resistivity of the second active layer corresponding to the second source-drain connection region.

[0017] In an exemplary embodiment, the driving structure layer is formed on the substrate, including: forming a first insulating layer and a semiconductor layer on the substrate in sequence, the semiconductor layer including at least a first active layer and a second active layer; forming a second insulating layer and a first conductive layer on the semiconductor layer, the first conductive layer including at least a first gate electrode and a second gate electrode; performing two ion implantation treatments on the first active layer and one ion implantation treatment on the second active layer, so that the first active layer forms a first channel region and a first source-drain connection region, and the second active layer forms a second channel region and a second source-drain connection region, and the resistivity of the first active layer corresponding to the first source-drain connection region is lower than the resistivity of the second active layer corresponding to the second source-drain connection region.

[0018] In an exemplary embodiment, the first active layer is subjected to two ion implantation treatments and the second active layer is subjected to one ion implantation treatment, comprising: using the first gate electrode and the second gate electrode as shielding, performing a first ion implantation treatment on the first active layer and the second active layer, wherein an area of ​​the first active layer not shielded by the first gate electrode forms a first source-drain connection area, and an area of ​​the first active layer shielded by the first gate electrode forms a first channel area; an area of ​​the second active layer not shielded by the second gate electrode forms a second source-drain connection area, and an area of ​​the second active layer shielded by the second gate electrode forms a second channel area; forming a photoresist layer on the substrate, wherein the photoresist layer covers the second active layer and the second gate electrode; and performing a second ion implantation treatment on the first active layer using the first gate electrode as shielding.

[0019] In an exemplary embodiment, in the first ion implantation process performed on the first active layer and the second active layer, the dose of the implanted ions is: 1E10 cm -2 To 1E13cm -2 ; In the second ion implantation treatment of the first active layer, the dose of the implanted ions is: 1E13cm -2To 1E16cm -2 .

[0020] In an exemplary embodiment, the first active layer is subjected to two ion implantation treatments and the second active layer is subjected to one ion implantation treatment, comprising: forming a photoresist layer on the substrate, the photoresist layer covering the second active layer and the second gate electrode; using the first gate electrode as a shield, performing a first ion implantation treatment on the first active layer, the area of ​​the first active layer not shielded by the first gate electrode forms a first source-drain connection area, and the area of ​​the first active layer shielded by the first gate electrode forms a first channel area; stripping the photoresist layer; using the first gate electrode and the second gate electrode as shields, performing a second ion implantation treatment on the first active layer, performing a first ion implantation treatment on the second active layer, the area of ​​the second active layer not shielded by the second gate electrode forms a second source-drain connection area, and the area of ​​the second active layer shielded by the second gate electrode forms a second channel area.

[0021] The display substrate proposed in the embodiment of the present disclosure, by setting the active layers corresponding to the source-drain connection regions of different transistors in the pixel driving circuit to have different resistivities, helps to reduce the leakage current of the corresponding transistors, thereby reducing the power consumption of the display substrate, and solves the problem of large leakage current of transistors in the existing LTPS display substrate.

[0022] Other aspects will be apparent upon reading and understanding the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The accompanying drawings are used to provide further understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation on the technical solution of the present disclosure.

[0024] Figure 1 is a structural schematic diagram of a display device;

[0025] Figure 2 is a schematic diagram of an equivalent circuit of a pixel driving circuit;

[0026] Figure 3 is a working timing diagram of a pixel driving circuit;

[0027] Figure 4 A schematic diagram showing a cross-sectional structure of a substrate according to an embodiment of the present disclosure;

[0028] Figure 5 This is a schematic diagram showing a substrate after a semiconductor layer is formed according to an embodiment of the present disclosure;

[0029] Figure 6This is a schematic diagram showing a substrate after a first conductive layer is formed in an embodiment of the present disclosure;

[0030] Figure 7 This is a schematic diagram showing a substrate after the first ion implantation according to an embodiment of the present disclosure;

[0031] Figure 8 This is a schematic diagram showing a substrate after a second ion implantation according to an embodiment of the present disclosure;

[0032] Fig. 9 This is a schematic diagram showing a substrate after a second conductive layer is formed in an embodiment of the present disclosure;

[0033] Fig.10 This is a schematic diagram showing a substrate after a fourth insulating layer is formed in an embodiment of the present disclosure;

[0034] Fig.11 This is a schematic diagram showing a substrate after a third conductive layer is formed in an embodiment of the present disclosure;

[0035] Fig.12 This is a schematic diagram showing a substrate after a flat layer is formed according to an embodiment of the present disclosure;

[0036] Fig.13 It is a schematic diagram of an embodiment of the present disclosure after an anode is formed on a display substrate;

[0037] Fig.14 It is a schematic diagram of the embodiment of the present disclosure after a pixel definition layer is formed on a display substrate;

[0038] Fig.15 The voltage-current relationship curve of the switching transistor prepared by the method of the embodiment of the present disclosure and the switching transistor prepared by the traditional LTPS process is shown.

[0039] Description of reference numerals:

[0040] 10—substrate; 11—first insulating layer; 11-1—first sub-insulating layer;

[0041] 11-2—second sub-insulating layer; 12—second insulating layer; 13—third insulating layer;

[0042] 14—fourth insulating layer; 15—planar layer; 21—first active layer;

[0043] 22—first gate electrode; 23—first source electrode; 24—first drain electrode;

[0044] 31: second active layer; 32: second gate electrode; 33: second source electrode;

[0045] 34—second drain electrode; 41—first electrode plate; 42—second electrode plate;

[0046] 51—anode; 61—pixel definition layer; 71—first channel region;

[0047] 72—first source-drain connection region; 81—second channel region; 82—second source-drain connection region;

[0048] 100—photoresist layer; 200—first type transistor; 300—second type transistor. DETAILED DESCRIPTION

[0049] The embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings. Note that the embodiments can be implemented in a plurality of different forms. A person skilled in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0050] The proportions of the drawings in this disclosure can be used as a reference in the actual process, but are not limited to this. For example: the width-to-length ratio of the channel, the thickness and spacing of each film layer, the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The drawings described in this disclosure are only structural schematic diagrams, and one method of this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0051] In the present specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0052] In this specification, for the sake of convenience, the words and phrases indicating the orientation or positional relationship, such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which each constituent element is described. Therefore, it is not limited to the words and phrases described in the specification, and can be appropriately replaced according to the situation.

[0053] In this specification, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this disclosure can be understood according to specific circumstances.

[0054] In this specification, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to a region where current mainly flows.

[0055] In this specification, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and the "drain electrode" may be interchanged, and the "source terminal" and the "drain terminal" may be interchanged.

[0056] In this specification, "electrical connection" includes the case where components are connected together through an element having some electrical function. There is no particular limitation on the "element having some electrical function" as long as it can transmit electrical signals between connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0057] In this specification, "parallel" means a state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, also includes a state where the angle is greater than -5° and less than 5°. In addition, "perpendicular" means a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, also includes a state where the angle is greater than 85° and less than 95°.

[0058] In this specification, "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced by "conductive film". Similarly, "insulating film" may be replaced by "insulating layer".

[0059] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, and may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0060] The term "about" in the present disclosure refers to a numerical value that is not strictly limited to allow for process and measurement errors.

[0061] Figure 1 FIG. 1 is a schematic diagram of the structure of a display device. Figure 1As shown, the display device may include a timing controller, a data driver, a scan driver, a light emitting driver and a pixel array, the timing controller is respectively connected to the data driver, the scan driver and the light emitting driver, the data driver is respectively connected to a plurality of data signal lines (D1 to Dn), the scan driver is respectively connected to a plurality of scan signal lines (S1 to Sm), and the light emitting driver is respectively connected to a plurality of light emitting signal lines (E1 to Eo). The pixel array may include a plurality of sub-pixels Pxij, i and j may be natural numbers, at least one sub-pixel Pxij may include a circuit unit and a light emitting device connected to the circuit unit, the circuit unit may include a pixel driving circuit, and the pixel driving circuit is connected to the scan signal line, the data signal line and the light emitting signal line. In an exemplary embodiment, the timing controller may provide a grayscale value and a control signal suitable for the specification of the data driver to the data driver, may provide a clock signal suitable for the specification of the scan driver, a scan start signal, etc. to the scan driver, and may provide a clock signal suitable for the specification of the light emitting driver, an emission stop signal, etc. to the light emitting driver. The data driver may generate a data voltage to be provided to the data signal lines D1, D2, D3, ... and Dn using the grayscale value and the control signal received from the timing controller. For example, the data driver may sample the grayscale value using the clock signal, and apply the data voltage corresponding to the grayscale value to the data signal lines D1 to Dn in units of pixel rows, where n may be a natural number. The scan driver may generate a scan signal to be provided to the scan signal lines S1, S2, S3, ... and Sm by receiving a clock signal, a scan start signal, etc. from the timing controller. For example, the scan driver may sequentially provide a scan signal with a conduction level pulse to the scan signal lines S1 to Sm. For example, the scan driver may be constructed in the form of a shift register, and may sequentially transmit the scan start signal provided in the form of a conduction level pulse to the next level circuit under the control of the clock signal to generate a scan signal, where m may be a natural number. The light emitting driver may generate an emission signal to be provided to the light emitting signal lines E1, E2, E3, ... and Eo by receiving a clock signal, an emission stop signal, etc. from the timing controller. For example, the light emitting driver may sequentially provide an emission signal having a cut-off level pulse to the light emitting signal lines E1 to Eo. For example, the light emitting driver may be constructed in the form of a shift register, and may generate an emission signal in a manner of sequentially transmitting an emission stop signal provided in the form of a cut-off level pulse to a next stage circuit under the control of a clock signal, and o may be a natural number.

[0062] Figure 2 FIG. 1 is a schematic diagram of an equivalent circuit of a pixel driving circuit. In an exemplary embodiment, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C or 7T1C structure. Figure 2As shown, the pixel driving circuit may include 7 transistors (first transistor T1 to seventh transistor T7), 1 storage capacitor C, and the pixel driving circuit is connected to 7 signal lines (data signal line D, first scanning signal line S1, second scanning signal line S2, light emitting signal line E, initial signal line INIT, first power line VDD and second power line VSS).

[0063] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, and a third node N3. The first node N1 is respectively connected to the first electrode of the third transistor T3, the second electrode of the fourth transistor T4, and the second electrode of the fifth transistor T5, the second node N2 is respectively connected to the second electrode of the first transistor, the first electrode of the second transistor T2, the control electrode of the third transistor T3, and the second end of the storage capacitor C, and the third node N3 is respectively connected to the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6.

[0064] In an exemplary embodiment, a first end of the storage capacitor C is connected to the first power line VDD, and a second end of the storage capacitor C is connected to the second node N2 , ie, the second end of the storage capacitor C is connected to the control electrode of the third transistor T3 .

[0065] The control electrode of the first transistor T1 is connected to the second scan signal line S2, the first electrode of the first transistor T1 is connected to the initial signal line INIT, and the second electrode of the first transistor is connected to the second node N2. When the on-level scan signal is applied to the second scan signal line S2, the first transistor T1 transmits the initialization voltage to the control electrode of the third transistor T3, so that the charge amount of the control electrode of the third transistor T3 is initialized.

[0066] The control electrode of the second transistor T2 is connected to the first scan signal line S1, the first electrode of the second transistor T2 is connected to the second node N2, and the second electrode of the second transistor T2 is connected to the third node N3. When the on-level scan signal is applied to the first scan signal line S1, the second transistor T2 connects the control electrode of the third transistor T3 to the second electrode.

[0067] The control electrode of the third transistor T3 is connected to the second node N2, that is, the control electrode of the third transistor T3 is connected to the second end of the storage capacitor C, the first electrode of the third transistor T3 is connected to the first node N1, and the second electrode of the third transistor T3 is connected to the third node N3. The third transistor T3 can be called a driving transistor, and the third transistor T3 determines the amount of driving current flowing between the first power line VDD and the second power line VSS according to the potential difference between its control electrode and the first electrode.

[0068] The control electrode of the fourth transistor T4 is connected to the first scan signal line S1, the first electrode of the fourth transistor T4 is connected to the data signal line D, and the second electrode of the fourth transistor T4 is connected to the first node N1. When the on-level scan signal is applied to the first scan signal line S1, the fourth transistor T4 enables the data voltage of the data signal line D to be input to the pixel driving circuit.

[0069] The control electrode of the fifth transistor T5 is connected to the light emitting signal line E, the first electrode of the fifth transistor T5 is connected to the first power line VDD, and the second electrode of the fifth transistor T5 is connected to the first node N1. The control electrode of the sixth transistor T6 is connected to the light emitting signal line E, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light emitting device. When the on-level light emitting signal is applied to the light emitting signal line E, the fifth transistor T5 and the sixth transistor T6 form a driving current path between the first power line VDD and the second power line VSS to make the light emitting device emit light.

[0070] The control electrode of the seventh transistor T7 is connected to the second scan signal line S2, the first electrode of the seventh transistor T7 is connected to the initial signal line INIT, and the second electrode of the seventh transistor T7 is connected to the first electrode of the light emitting device. When the on-level scan signal is applied to the second scan signal line S2, the seventh transistor T7 transmits the initialization voltage to the first electrode of the light emitting device to initialize or release the charge accumulated in the first electrode of the light emitting device.

[0071] In an exemplary embodiment, the light-emitting device can be an OLED, including a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode), or can be a QLED, including a stacked first electrode (anode), a quantum dot light-emitting layer, and a second electrode (cathode), or can be an LED.

[0072] In an exemplary embodiment, the second electrode of the light emitting device is connected to the second power line VSS, the signal of the second power line VSS is a low level signal, and the signal of the first power line VDD is a continuously provided high level signal. The first scanning signal line S1 is a scanning signal line in the pixel driving circuit of the current display row, and the second scanning signal line S2 is a scanning signal line in the pixel driving circuit of the previous display row, that is, for the nth display row, the first scanning signal line S1 is S(n), and the second scanning signal line S2 is S(n-1), and the second scanning signal line S2 of the current display row is the same as the first scanning signal line S1 in the pixel driving circuit of the previous display row, which can reduce the signal lines of the display panel and realize the narrow frame of the display panel.

[0073] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 may be a P-type transistor, or may be an N-type transistor. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product. In some possible implementations, the first transistor T1 to the seventh transistor T7 may include a P-type transistor and an N-type transistor.

[0074] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 may be a low-temperature polysilicon thin film transistor, or an oxide thin film transistor, or a low-temperature polysilicon thin film transistor and an oxide thin film transistor. The active layer of the low-temperature polysilicon thin film transistor is low-temperature polysilicon (LTPS for short), and the active layer of the oxide thin film transistor is oxide semiconductor (Oxide). The low-temperature polysilicon thin film transistor has the advantages of high mobility and fast charging, and the oxide thin film transistor has the advantages of low leakage current. The low-temperature polysilicon thin film transistor and the oxide thin film transistor are integrated on a display substrate to form a low-temperature polycrystalline oxide (LTPO for short) display substrate, which can take advantage of the advantages of both, can achieve low-frequency driving, can reduce power consumption, and can improve display quality.

[0075] Figure 3 is a working timing diagram of a pixel driving circuit. Figure 2 Taking the example that all the seven transistors in the pixel driving circuit are P-type transistors, in an exemplary embodiment, the operation process of the pixel driving circuit may include:

[0076] The first stage A1 is called the reset stage. The signal of the second scanning signal line S2 is a low-level signal, and the signals of the first scanning signal line S1 and the light-emitting signal line E are high-level signals. The signal of the second scanning signal line S2 is a low-level signal, which turns on the first transistor T1. The signal of the initial signal line INIT is provided to the second node N2 to initialize the storage capacitor C and clear the original data voltage in the storage capacitor. The signals of the first scanning signal line S1 and the light-emitting signal line E are high-level signals, which turns off the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7. In this stage, the OLED does not emit light.

[0077] The second stage A2 is called the data writing stage or the threshold compensation stage. The signal of the first scanning signal line S1 is a low level signal, the signals of the second scanning signal line S2 and the light emitting signal line E are high level signals, and the data signal line D outputs the data voltage. In this stage, since the second end of the storage capacitor C is at a low level, the third transistor T3 is turned on. The signal of the first scanning signal line S1 is a low level signal, which turns on the second transistor T2, the fourth transistor T4 and the seventh transistor T7. The second transistor T2 and the fourth transistor T4 are turned on so that the data voltage output by the data signal line D is provided to the second node N2 through the first node N1, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2, and the difference between the data voltage output by the data signal line D and the threshold voltage of the third transistor T3 is charged into the storage capacitor C. The voltage of the second end (the second node N2) of the storage capacitor C is Vd-|Vth|, Vd is the data voltage output by the data signal line D, and Vth is the threshold voltage of the third transistor T3. The seventh transistor T7 is turned on so that the initial voltage of the initial signal line INIT is provided to the first electrode of the OLED, the first electrode of the OLED is initialized (reset), the pre-stored voltage inside it is cleared, the initialization is completed, and the OLED is ensured not to emit light. The signal of the second scanning signal line S2 is a high-level signal, which turns off the first transistor T1. The signal of the light-emitting signal line E is a high-level signal, which turns off the fifth transistor T5 and the sixth transistor T6.

[0078] The third stage A3 is called the light-emitting stage, the signal of the light-emitting signal line E is a low-level signal, and the signals of the first scanning signal line S1 and the second scanning signal line S2 are high-level signals. The signal of the light-emitting signal line E is a low-level signal, which turns on the fifth transistor T5 and the sixth transistor T6, and the power supply voltage output by the first power supply line VDD provides a driving voltage to the first electrode of the OLED through the turned-on fifth transistor T5, the third transistor T3 and the sixth transistor T6, driving the OLED to emit light.

[0079] During the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its gate electrode and the first electrode. Since the voltage of the second node N2 is Vd-|Vth|, the driving current of the third transistor T3 is:

[0080] I=K*(Vgs-Vth) 2 =K*[(Vdd-Vd+|Vth|)-Vth] 2 =K*[(Vdd-Vd] 2

[0081] Among them, I is the driving current flowing through the third transistor T3, that is, the driving current driving the OLED, K is a constant, Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vd is the data voltage output by the data signal line D, and Vdd is the power supply voltage output by the first power supply line VDD.

[0082] In recent years, low-temperature polycrystalline oxide (LTPO) display substrates have emerged based on LTPS display substrates, and the switch transistors (STFT) in the pixel circuits are prepared using oxide processes, that is, transistors that act as switches in the pixel circuits. Although the mobility of oxide transistors is low, their extremely low leakage current enables the screen to maintain display quality at low refresh rates, such as 1Hz, thereby reducing power consumption. However, although the LTPO display substrate can reduce the leakage current of the switching transistor, an oxide process needs to be used in the preparation process. This process requires a large number of masks, and there are problems of complex process and high production cost.

[0083] An embodiment of the present disclosure provides a display substrate, including a driving structure layer arranged on a substrate, the driving structure layer includes a pixel driving circuit, the pixel driving circuit includes at least a first type transistor and a second type transistor, the first type transistor includes at least a first active layer, and the second type transistor includes at least a second active layer; the first active layer includes a first channel region and a first source-drain connection region located on both sides of the first channel region, the second active layer includes a second channel region and a second source-drain connection region located on both sides of the second channel region; the resistivity of the first active layer corresponding to the first source-drain connection region is different from the resistivity of the second active layer corresponding to the second source-drain connection region.

[0084] The display substrate proposed in the embodiment of the present disclosure helps to reduce the leakage current of the corresponding transistors by setting the active layers corresponding to the source-drain connection regions of different transistors in the pixel driving circuit to have different resistivities, thereby reducing the power consumption of the display substrate.

[0085] In an exemplary embodiment, the first type transistor is a driving transistor, the second type transistor is a switching transistor, and the resistivity of the first active layer corresponding to the first source-drain connection region is lower than the resistivity of the second active layer corresponding to the second source-drain connection region.

[0086] In an exemplary embodiment, the resistivity of the first active layer corresponding to the first source-drain connection region is approximately 1E-4 ohm-cm (Ω"cm) to 1E-1Ω"cm; the resistivity of the second active layer corresponding to the second source-drain connection region is approximately 1E-1Ω"cm to 1E2Ω"cm.

[0087] In an exemplary embodiment, the first active layer corresponding to the first source-drain connection region and the second active layer corresponding to the second source-drain connection region both contain doped N-type ions, and the N-type ion content of the first active layer corresponding to the first source-drain connection region is higher than the N-type ion content of the second active layer corresponding to the second source-drain connection region.

[0088] In an exemplary embodiment, the content of N-type ions in the first active layer corresponding to the first source-drain connection region is 1E18 cm -3 To 1E21cm -3 The content of N-type ions in the second active layer corresponding to the second source-drain connection region is 1E15cm -3 To 1E18cm -3 .

[0089] In an exemplary embodiment, the N-type ions include one or more of the following ions: phosphorus ions, nitrogen ions, arsenic ions, and antimony ions. In an exemplary embodiment, the first active layer corresponding to the first source-drain connection region may include one or more of the following doped N-type ions: phosphorus ions, nitrogen ions, arsenic ions, and antimony ions. The second active layer corresponding to the second source-drain connection region may include one or more of the following doped N-type ions: phosphorus ions, nitrogen ions, arsenic ions, and antimony ions. In other embodiments, other suitable doping ions may be selected as needed, and the present disclosure is not limited thereto.

[0090] In an exemplary embodiment, the first active layer corresponding to the first source-drain connection region and the second active layer corresponding to the second source-drain connection region both contain doped P-type ions, and the P-type ion content of the first active layer corresponding to the first source-drain connection region is higher than the P-type ion content of the second active layer corresponding to the second source-drain connection region.

[0091] In an exemplary embodiment, the content of P-type ions in the first active layer corresponding to the first source-drain connection region is 1E18 cm -3 To 1E21cm -3 The content of P-type ions in the second active layer corresponding to the second source-drain connection region is 1E15cm -3 To 1E18cm -3 .

[0092] In an exemplary embodiment, the P-type ions include one or more of the following ions: boron ions, aluminum ions, gallium ions, and indium ions. In an exemplary embodiment, the first active layer corresponding to the first source-drain connection region may include one or more of the following doped P-type ions: boron ions, aluminum ions, gallium ions, and indium ions. The second active layer corresponding to the second source-drain connection region may include one or more of the following doped P-type ions: boron ions, aluminum ions, gallium ions, and indium ions. In other embodiments, other suitable doping ions may be selected as needed, and the present disclosure is not limited thereto.

[0093] Figure 4 FIG. 1 is a schematic diagram of a display substrate according to an exemplary embodiment of the present disclosure. Figure 4 As shown, the exemplary embodiment of the present disclosure shows that the substrate may include a driving structure layer arranged on a substrate 10, the driving structure layer may include a pixel driving circuit, the pixel driving circuit may include at least a first type transistor 200 and a second type transistor 300, the first type transistor 200 may include at least a first active layer 21, a first gate electrode 22, a first source electrode 23 and a first drain electrode 24, and the second type transistor 300 may include at least a second active layer 31, a second gate electrode 32, a second source electrode 33 and a second drain electrode 34.

[0094] In an exemplary embodiment, the first active layer 21 may include a first channel region 71 and a first source-drain connection region 72 located on both sides of the first channel region 71, the second active layer 31 may include a second channel region 81 and a second source-drain connection region 82 located on both sides of the second channel region 81, and the resistivity of the first source-drain connection region 72 is different from the resistivity of the second source-drain connection region 82.

[0095] In an exemplary embodiment, the orthographic projection of the first gate electrode 22 on the substrate may be within the range of the orthographic projection of the first active layer 21 on the substrate, and the orthographic projection of the second gate electrode 32 on the substrate may be within the range of the orthographic projection of the second active layer 31 on the substrate.

[0096] In an exemplary embodiment, the first source-drain connection region 72 may include a first source connection region and a first drain connection region. The first source electrode 23 may be connected to the first source connection region of the first active layer 21, and the first drain electrode 24 may be connected to the first drain connection region of the first active layer 21. The second source-drain connection region 82 may include a second source connection region and a second drain connection region. The second source electrode 33 may be connected to the second source connection region of the second active layer 31, and the second drain electrode 34 may be connected to the second drain connection region of the second active layer 31 through a second active via.

[0097] In an exemplary embodiment, the first type transistor 200 may be a driving transistor, the second type transistor 300 may be a switching transistor, and the resistivity of the first active layer 21 corresponding to the first source-drain connection region 72 may be lower than the resistivity of the second active layer 31 corresponding to the second source-drain connection region 82 .

[0098] In an exemplary embodiment, the first active layer 21 corresponding to the first source-drain connection region 72 and the second active layer 31 corresponding to the second source-drain connection region 82 may both contain doped N-type ions, and the N-type ion content of the first active layer 21 corresponding to the first source-drain connection region 72 may be higher than the N-type ion content of the second active layer 31 corresponding to the second source-drain connection region 82.

[0099] In an exemplary embodiment, the content of N-type ions in the first active layer 21 corresponding to the first source-drain connection region 72 may be 1E18 cm -3 To 1E21cm -3 The content of N-type ions in the second active layer 31 corresponding to the second source-drain connection region 82 may be 1E15 cm -3 To 1E18cm -3 .

[0100] In an exemplary embodiment, the N-type ions may include one or more of the following ions: phosphorus ions, nitrogen ions, arsenic ions, and antimony ions.

[0101] In an exemplary embodiment, the first active layer corresponding to the first source-drain connection region and the second active layer corresponding to the second source-drain connection region may both contain doped P-type ions, and the P-type ion content of the first active layer 21 corresponding to the first source-drain connection region 72 may be higher than the P-type ion content of the second active layer 31 corresponding to the second source-drain connection region 82.

[0102] In an exemplary embodiment, the content of P-type ions in the first active layer 21 corresponding to the first source-drain connection region 72 may be 1E18 cm -3 To 1E21cm -3 The content of P-type ions in the second active layer 31 corresponding to the second source-drain connection region 82 may be 1E15 cm -3 To 1E18cm -3 .

[0103] In an exemplary embodiment, the P-type ions may include one or more of the following ions: boron ions, aluminum ions, gallium ions, and indium ions.

[0104] In an exemplary embodiment, the pixel driving circuit may include a first capacitor, and the first capacitor may include a first plate 41 and a second plate 42 , wherein an orthographic projection of the second plate 42 on the substrate at least partially overlaps an orthographic projection of the first plate 41 on the substrate.

[0105] In an exemplary embodiment, the display substrate may include a first insulating layer 11, a second insulating layer 12, a third insulating layer 13 and a fourth insulating layer 14, the first insulating layer 11 is disposed on a substrate 10, a first active layer 21 and a second active layer 31 are disposed on the first insulating layer 11, the second insulating layer 12 covers the first active layer 21 and the second active layer 31, a first gate electrode 22, a second gate electrode 32 and a first electrode plate 41 are disposed on the second insulating layer 12, the third insulating layer 13 covers the first gate electrode 22, the second gate electrode 32 and the first electrode plate 41, the second electrode plate 42 is disposed on the third insulating layer 13, the fourth insulating layer 14 covers the second electrode plate 42, and the first source electrode 23, the first drain electrode 24, the second source electrode 33 and the second drain electrode 34 are disposed on the fourth insulating layer 14. The fourth insulating layer 14 may include a first active via and a second active via, and the first source electrode 23 and the first drain electrode 24 may be connected to the first source connection region and the first drain connection region respectively through the first active via, and the second source electrode 33 and the second drain electrode 34 may be connected to the second source connection region and the second drain connection region respectively through the second active via.

[0106] The following is an exemplary explanation through the preparation process of the display substrate. The "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials or transparent conductive materials, and includes processes such as coating organic materials, mask exposure and development for organic materials. Deposition can be any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be any one or more of spraying, spin coating and inkjet printing, and etching can be any one or more of dry etching and wet etching, which are not limited in the present disclosure. "Thin film" refers to a layer of thin film made by deposition, coating or other processes of a certain material on a substrate. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The "A and B are arranged in the same layer" mentioned in the present disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the size of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of the present disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0107] In an exemplary embodiment, a process of preparing a display substrate may include the following steps.

[0108] (1) Forming a semiconductor layer pattern. In an exemplary embodiment, forming a semiconductor layer pattern may include sequentially depositing a first insulating film and an amorphous silicon (a-Si) film on a substrate, treating the amorphous silicon film by a laser method to crystallize the amorphous silicon film into a polycrystalline silicon film, and patterning the polycrystalline silicon film by a patterning process to form a first insulating layer 11 disposed on the substrate and a semiconductor layer pattern disposed on the first insulating layer 11. The semiconductor layer pattern may include at least a first active layer 21 and a second active layer 31, such as Figure 5 shown.

[0109] In an exemplary embodiment, the substrate may be a rigid substrate or a flexible substrate. The rigid substrate may be made of materials such as glass or quartz, the flexible substrate may be made of materials such as polyimide (PI), and the flexible substrate may be a single-layer structure or a laminated structure consisting of an inorganic material layer and a flexible material layer, which is not limited in the present disclosure.

[0110] In an exemplary embodiment, the material of the first insulating layer 11 may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and may be a single layer, a double layer or a multilayer structure. For example, the first insulating layer 11 may include a first sub-insulating layer 11-1 and a second sub-insulating layer 11-2 stacked together, the first sub-insulating layer 11-1 may be referred to as a barrier layer, and the second sub-insulating layer 11-2 may be referred to as a buffer layer. The buffer layer may prevent metal ions in the substrate from diffusing into the active layer, thereby preventing the threshold voltage and leakage current from being affected. A suitable buffer layer may improve the quality of the back interface of the polysilicon layer, prevent leakage current from being generated at the back interface of the polysilicon layer, and further reduce heat conduction and slow down the cooling rate of the silicon heated by the laser.

[0111] In an exemplary embodiment, ion implantation equipment may be used to perform ion implantation on the first active layer 21 and the second active layer 31 to adjust the doping conditions of the first active layer 21 and the second active layer 31 , which is not limited in the present disclosure.

[0112] In an exemplary embodiment, the laser laser can use XeCl laser, ArF laser, KrF laser and XeF laser, etc. These excimer lasers generate a laser beam in the ultraviolet band. By irradiating the amorphous silicon film with a short pulse laser beam in the ultraviolet band, the amorphous silicon film will quickly absorb the laser energy to melt and recrystallize.

[0113] In an exemplary embodiment, the amorphous silicon thin film may be deposited by chemical vapor deposition (CVD) and other methods, which are not limited in the present disclosure.

[0114] (2) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: sequentially depositing a second insulating film and a first conductive film on a substrate formed with the aforementioned pattern, patterning the first conductive film through a patterning process, and forming a second insulating layer 12 covering the semiconductor layer pattern and a first conductive layer pattern disposed on the second insulating layer 12. The first conductive layer pattern may include at least a first gate electrode 22, a second gate electrode 32, and a first electrode 41. Figure 6 shown.

[0115] In an exemplary embodiment, the orthographic projection of the first gate electrode 22 on the substrate may be located within the range of the orthographic projection of the first active layer 21 on the substrate, and the orthographic projection of the second gate electrode 32 on the substrate may be located within the range of the orthographic projection of the second active layer 31 on the substrate. The orthographic projection of the first electrode plate 41 on the substrate may not overlap with the orthographic projection of the first active layer 21 on the substrate, and the orthographic projection of the first electrode plate 41 on the substrate may not overlap with the orthographic projection of the second active layer 31 on the substrate.

[0116] In an exemplary embodiment, the second insulating film may be deposited by a CVD method, and the first conductive film may be deposited by a sputtering method, which is not limited in the present disclosure.

[0117] In an exemplary embodiment, the second insulating film may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), aluminum oxide, zirconium oxide and hafnium oxide, and may be a single layer, a multilayer or a composite layer. The second insulating layer 12 may be referred to as a gate insulating (GI) layer. The first conductive film may be a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), tungsten (W) and molybdenum (Mo), or an alloy material of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and may be a single layer structure, or a multilayer composite structure, such as Ti / Al / Ti, etc., which is not limited in the present disclosure.

[0118] (3) Performing a first ion implantation. In an exemplary embodiment, performing a first ion implantation may include:

[0119] By using an ion implantation method, the first gate electrode 22 and the second gate electrode 32 are used as shields to perform a first ion implantation process on the first active layer 21 and the second active layer 31 to form an LTPS active layer pattern including a source-drain connection region and a channel region. The LTPS active layer pattern at least includes: a first active layer 21 including a first source-drain connection region 72 and a first channel region 71, and a second active layer 31 including a second source-drain connection region 82 and a second channel region 81, such as Figure 7shown.

[0120] In an exemplary embodiment, the region of the first active layer 21 blocked by the first gate electrode 22 forms a first channel region 71, which is a channel region of the first type transistor. The region of the first active layer 21 not blocked by the first gate electrode 22 forms a first source-drain connection region 72, which is located on both sides of the first channel region 71 and includes a first source connection region and a first drain connection region.

[0121] In the exemplary embodiment, the area of ​​the second active layer 31 blocked by the second gate electrode 32 forms a second channel area 81, which is the channel area of ​​the second type transistor. The area of ​​the second active layer 31 not blocked by the second gate electrode 32 forms a second source-drain connection area 82, which is located on both sides of the second channel area 81 and includes a second source connection area and a second drain connection area.

[0122] In an exemplary embodiment, ion implantation equipment may be used to implant ions into the first active layer 21 and the second active layer 31, which is not limited in the present disclosure. By doping the source and drain regions of the LTPS active layer using an ion implantation process to form a doped region, the subsequently formed source and drain electrodes are connected to the doped region of the LTPS active layer, thereby reducing contact resistance and obtaining better TFT electrical characteristics.

[0123] In an exemplary embodiment, the first active layer 21 and the second active layer 31 may be simultaneously subjected to a first ion implantation. The first ion implantation may implant N-type ions, and the N-type ions may be one or more of phosphorus ions, nitrogen ions, arsenic ions, and antimony ions. In other embodiments, the first ion implantation may implant P-type ions, and the P-type ions may be one or more of boron ions, aluminum ions, gallium ions, and indium ions. During actual preparation, the type and species of implanted ions may be selected as needed, and the present disclosure does not limit this. The ion implantation may be performed by ion implantation with a mass analyzer, ion cloud implantation without a mass analyzer, plasma implantation, or solid-state diffusion implantation, and the present disclosure does not limit this.

[0124] In an exemplary embodiment, when the first active layer 21 and the second active layer 31 are first ion-implanted, the ion implantation dose may be about 1E10 cm -2 To 1E13cm -2 , that is, the total number of ions implanted per square centimeter is 1E10 to 1E13, which can be called the surface concentration of ions. The appropriate ion implantation dose can be selected as needed, and the present disclosure does not limit this.

[0125] In an exemplary embodiment, considering that the channel region is getting shorter and shorter, the short channel effect is becoming more and more obvious, and the short channel effect causes abnormal TFT characteristics, such as large cut-off voltage Vth, high leakage current Ioff, etc. In order to avoid such abnormalities, a third doped region can be added between the doped region and the undoped region, and the doping amount of the third doped region can be less than that of the first doped region or the second doped region, which is equivalent to connecting a resistor in series between the source and drain electrodes and the channel, reducing the horizontal electric field of the channel and suppressing the leakage current. In actual implementation, one or two third doped regions can be set. For example, when the LTPS thin film transistor is used as a switching device of the pixel driving circuit in the display area, two third doped regions need to be designed, and when the LTPS thin film transistor is used as a switching device of the gate driving circuit in the peripheral area, only one third doped region needs to be set on the side of the drain electrode, and the present disclosure does not limit this.

[0126] (4) Performing a second ion implantation. In an exemplary embodiment, performing a second ion implantation may include: coating a photoresist on the substrate having the above-mentioned pattern, removing the photoresist in the area above the first active layer 21 by masking, exposure and development, and forming a photoresist layer 100, wherein the photoresist layer 100 covers the second active layer 31, the second gate electrode 22 and the first electrode 41. Subsequently, an ion implantation method is used to perform a second ion implantation process on the first active layer 21 with the first gate electrode 22 as a shield. Figure 8 Then, the photoresist layer 100 is stripped off.

[0127] In an exemplary embodiment, the region of the first active layer 21 not blocked by the first gate electrode 22 undergoes a second ion implantation, further increasing the doping amount of the first source-drain connection region 72 on both sides of the first active layer 21. The region of the first active layer 21 blocked by the first gate electrode 22 is still the first channel region 71.

[0128] In an exemplary embodiment, the first type transistor may be a driving transistor, and the second type transistor may be a switching transistor.

[0129] In an exemplary embodiment, the orthographic projection of the photoresist layer 100 on the substrate may cover the orthographic projection of the second active layer 16. The photoresist layer 100 may cover the region where the switch transistor is located and expose the region where the drive transistor is located, thereby facilitating a second ion implantation of the drive transistor.

[0130] In an exemplary embodiment, an orthographic projection of the photoresist layer 100 on the substrate may include an orthographic projection of the first electrode plate 41 on the substrate.

[0131] In an exemplary embodiment, the ion type and ion species of the second ion implantation may be the same as those of the first ion implantation, and a suitable ion implantation method may be selected as needed, which is not limited in the present disclosure.

[0132] In an exemplary embodiment, when the second ion implantation is performed on the first active layer 21, the implantation dose of the ion implantation may be about 1E13 cm -2 To 1E16cm -2 , that is, the total number of ions implanted per square centimeter of the surface is 1E13 to 1E16. The appropriate ion implantation dose can be selected as needed, and the present disclosure does not limit this.

[0133] In an exemplary embodiment, the second active layer 31 can be shielded by a photoresist during the first ion implantation, and the first ion implantation is performed only on the first active layer 21, and then the photoresist is stripped off, and the second ion implantation is performed on the first active layer 21 and the second active layer 31, and different doses of ions can be implanted into the driving transistor and the switching transistor, and the present disclosure is not limited to this. In other embodiments, multiple ion implantation operations can also be performed, and a suitable ion implantation process can be selected as needed, and the present disclosure is not limited to this.

[0134] In an exemplary embodiment, after the ion implantation is completed, the volume concentration of the ions can be calculated by dividing the surface concentration of the ions by the thickness of the corresponding active layer, that is, the number of atoms contained in the active layer per cubic centimeter. In an exemplary embodiment, the first source-drain connection region 72 of the first type transistor has undergone two ion implantations, and the content of N-type ions or P-type ions in the first active layer corresponding to the first source-drain connection region 72 is approximately 1E18cm -3 To 1E21cm -3 The second source-drain connection region 82 of the second type transistor has been subjected to an ion implantation, and the content of N-type ions or P-type ions in the second active layer corresponding to the second source-drain connection region is about 1E15 cm -3 To 1E18cm -3 .

[0135] In an exemplary embodiment, the first source-drain connection region 72 of the first type transistor has undergone two ion implantations, has lower resistivity and stronger conductivity, and the resistivity of the first source-drain connection region 72 of the first type transistor is lower than the resistivity of the second source-drain connection region 82 of the second type transistor.

[0136] After the second ion implantation, since the source-drain connection region of the switch transistor has only undergone one ion implantation, the ion implantation dose is lower than that of the source-drain region of the drive transistor, thereby reducing the leakage current of the switch transistor and achieving the purpose of reducing the power consumption of the display substrate.

[0137] (5) Forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern may include: sequentially depositing a third insulating film and a second conductive film on the substrate formed with the aforementioned pattern, patterning the second conductive film through a patterning process, and forming a third insulating layer 13 covering the first conductive layer and a second conductive layer pattern disposed on the third insulating layer 13. The second conductive layer pattern may include at least a second electrode 42. Fig. 9 shown.

[0138] In an exemplary embodiment, an orthographic projection of the second electrode plate 42 on the substrate at least partially overlaps an orthographic projection of the first electrode plate 41 on the substrate.

[0139] In an exemplary embodiment, the third insulating film may be deposited by chemical vapor deposition, and the second conductive film may be deposited by sputtering, which is not limited in the present disclosure.

[0140] In an exemplary embodiment, the third insulating film may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), aluminum oxide, zirconium oxide, and hafnium oxide, and may be a single layer, a multilayer, or a composite layer. The third insulating layer 23 may be referred to as a first interlayer insulating (ILD) layer. The second conductive film may be a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), tungsten (W), and molybdenum (Mo), or an alloy material of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and may be a single layer structure, or a multilayer composite structure, such as Ti / Al / Ti, etc., which is not limited in the present disclosure.

[0141] (6) Forming a fourth insulating layer pattern. In an exemplary embodiment, forming the fourth insulating layer pattern may include: depositing a fourth insulating film on the substrate formed with the aforementioned pattern, patterning the fourth insulating film through a patterning process to form a fourth insulating layer 14 covering the second conductive layer, and forming a plurality of via holes on the fourth insulating layer 14, such as Fig.10 shown.

[0142] In an exemplary embodiment, the plurality of vias may include a first active via K1 and a second active via K2, and the fourth insulating layer 14, the third insulating layer 13, and the second insulating layer 12 in the first active via K1 are removed to expose the surface of the first source-drain connection region 72 in the first active layer 21. The fourth insulating layer 14, the third insulating layer 13, and the second insulating layer 12 in the second active via K2 are removed to expose the surface of the second source-drain connection region 82 in the second active layer 31.

[0143] In an exemplary embodiment, the orthographic projection of the first active via K1 on the substrate may be located within the orthographic projection of the first source-drain connection region 72 on the substrate. The second active via K2 may be located within the orthographic projection of the second source-drain connection region 82 on the substrate.

[0144] In an exemplary embodiment, the fourth insulating film may be deposited by a chemical vapor deposition method, which is not limited in the present disclosure.

[0145] In an exemplary embodiment, the fourth insulating film may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), aluminum oxide, zirconium oxide, and hafnium oxide, and may be a single layer, a multilayer, or a composite layer, which is not limited in the present disclosure. The fourth insulating layer 25 may be referred to as a second interlayer insulating layer.

[0146] (7) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer pattern may include: depositing a third conductive film on the substrate on which the aforementioned pattern is formed, patterning the third conductive film through a patterning process, and forming the third conductive layer pattern on the fourth insulating layer 14. The third conductive layer pattern may include at least the first source electrode 23, the first drain electrode 24, the second source electrode 33, and the second drain electrode 34. Fig.11 shown.

[0147] In an exemplary embodiment, the first source electrode 23 may be connected to the first source connection region of the first active layer 21 through the first active via hole K1, and the first drain electrode 24 may be connected to the first drain connection region of the first active layer 21 through the first active via hole K1, forming an LTPS thin film transistor. The second source electrode 33 may be connected to the second source connection region of the second active layer 31 through the second active via hole K2, and the second drain electrode 34 may be connected to the second drain connection region of the second active layer 31 through the second active via hole K2, forming an LTPS thin film transistor.

[0148] In an exemplary embodiment, the third conductive film may be deposited by sputtering, which is not limited in the present disclosure.

[0149] In an exemplary embodiment, the third conductive film may be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), tungsten (W) and molybdenum (Mo), or an alloy material of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and may be a single-layer structure, or a multi-layer composite structure, such as Ti / Al / Ti, etc., which is not limited in the present disclosure.

[0150] In an exemplary embodiment, the first type transistor may include: a first active layer 21, a first gate electrode 22, a first source electrode 23, and a first drain electrode 24. The second type transistor may include: a second active layer 31, a second gate electrode 32, a second source electrode 33, and a second drain electrode 34. The first capacitor may include a first plate 41 and a second plate 42. The first type transistor may be a driving transistor in a pixel driving circuit. The pixel driving circuit may include a plurality of transistors and a storage capacitor, Fig.11 In the figure, only the first capacitor, the first type transistor and the second type transistor are taken as examples.

[0151] (7) Forming a planar layer pattern. In an exemplary embodiment, forming a planar layer pattern may include:

[0152] A flat film is coated on the substrate formed with the aforementioned pattern, and a patterning process of masking, exposure and development is performed to form a flat layer 15 covering the third conductive layer. A flat via K3 is formed on the flat layer 15, and the flat via K3 can expose the surface of the first drain electrode 24 of the first type transistor. Fig.12 shown.

[0153] In an exemplary embodiment, the orthographic projection of the planar via K3 on the substrate may be located within the range of the orthographic projection of the first drain electrode 24 of the first type transistor on the substrate. In other embodiments, the planar via K3 may expose the surface of the first source electrode 23 of the first type transistor, and the orthographic projection of the planar via K3 on the substrate may be located within the range of the orthographic projection of the first source electrode 23 of the first type transistor on the substrate.

[0154] In exemplary embodiments, the planar thin film may be an organic material, which is not limited by the present disclosure.

[0155] At this point, the drive structure layer is prepared, such as Fig.12 As shown. From the above preparation process, it can be seen that compared with the traditional LTPS process, the preparation method provided by the embodiment of the present disclosure can control the ion implantation dose of the switching transistor, thereby reducing the leakage current of the switching transistor, which can play a role in energy saving and consumption reduction. Compared with the LTPO process, the preparation method provided by the embodiment of the present disclosure does not use an oxidation process, has a lower process complexity, requires fewer masks, and can reduce costs.

[0156] In an exemplary embodiment, a light emitting structure layer may be further prepared on the display substrate, and the process of preparing the light emitting structure layer may include:

[0157] (8) Forming an anode pattern. In an exemplary embodiment, forming an anode pattern may include:

[0158] A transparent conductive film is deposited on the substrate having the aforementioned pattern, and the transparent conductive film is patterned by a patterning process to form an anode 51 pattern. Fig.13 shown.

[0159] In an exemplary embodiment, the anode 51 may be connected to the first drain electrode 24 of the first type transistor through a planar via K3 on the planar layer 15 .

[0160] In an exemplary embodiment, the transparent conductive film may be deposited by sputtering, which is not limited in the present disclosure.

[0161] In an exemplary embodiment, the transparent conductive film may be made of a metal material, a transparent conductive material, or a multilayer composite structure of a metal material and a transparent conductive material. The metal material may include any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), or an alloy material of the above metals. The transparent conductive material may include indium tin oxide (ITO) or indium zinc oxide (IZO). The multilayer composite structure may be ITO / Al / ITO, etc., which is not limited in the present disclosure.

[0162] (9) Forming a pixel definition layer pattern. In an exemplary embodiment, forming a pixel definition layer pattern includes:

[0163] A pixel definition film is coated on the substrate formed with the aforementioned pattern, and a portion of the pixel definition film is removed by masking, exposure and development to form a pixel definition layer 61 pattern. Fig.14 shown.

[0164] In an exemplary embodiment, a pixel opening K4 is provided on the pixel definition layer 61 , and the pixel definition film in the pixel opening K4 is removed to expose the surface of the anode 51 .

[0165] In an exemplary embodiment, the pixel definition film may be made of a material such as polyimide, acrylic, or polyethylene terephthalate, which is not limited in the present disclosure.

[0166] In an exemplary embodiment, a light-emitting device can be prepared on the display substrate as needed, and the light-emitting device can be connected to the anode 51 through the pixel opening K4. The light-emitting device can be an LED, an OLED, or a QLED, etc., which is not limited in the present disclosure.

[0167] In an exemplary embodiment, the display substrate may further include other film layer structures, such as a protective layer and other structures, which may be prepared according to actual needs and will not be described in detail here.

[0168] The structure and preparation process shown in the exemplary embodiment of the present disclosure are merely exemplary. In actual implementation, the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs, and the present disclosure does not limit this.

[0169] Fig.15 The voltage-current relationship curve of the switching transistor prepared by the method of the embodiment of the present disclosure and the switching transistor prepared by the traditional LTPS process is shown. Fig.15 The horizontal axis is the gate voltage, in volts (V), and the vertical axis is the current, in amperes (A). Figure 4 Curve a represents the current curve of a switch transistor manufactured by a conventional LTPS process at different gate voltages, and curve b represents the current curve of a switch transistor manufactured by the method of an embodiment of the present disclosure at different gate voltages. Except for the difference in the switch transistor, curve a and curve b have the same test conditions. Fig.15 It can be seen that under the same gate voltage, the current of curve b is generally smaller than that of curve a, and the operating current and leakage current of the switching transistor in curve b are both smaller than those in curve a. After simulation experiments, it is found that the characteristic mobility of the switching transistor in curve a is 62.38cm 2 / V-sec, the leakage current is -1.32E-14A, and the characteristic mobility of the switching transistor of curve b is 15.31cm 2 / V-sec, the leakage current is -8.81E-16A. It can be seen that the leakage current of the switching transistor prepared by the method of the embodiment of the present disclosure is two orders of magnitude smaller than the leakage current of the switching transistor prepared by the traditional LTPS process. Moreover, although the operating current and characteristic mobility of the switching transistor prepared by the method of the embodiment of the present disclosure are reduced, they can still be maintained at the level of oxide transistors. Therefore, the switching transistor prepared by the preparation method provided by the embodiment of the present disclosure not only solves the serious leakage problem of the LTPS transistor, but also solves the problem of complex process and high production cost of the LTPO transistor, and the changes to the existing process are very small, and it has broad application prospects.

[0170] The embodiment of the present disclosure also provides a method for preparing a display substrate, comprising: forming a driving structure layer on a substrate, the driving structure layer comprising a pixel driving circuit, the pixel driving circuit comprising at least a first type transistor and a second type transistor, the first type transistor comprising at least a first active layer, and the second type transistor comprising at least a second active layer; the first active layer comprising a first channel region and a first source-drain connection region located on both sides of the first channel region, the second active layer comprising a second channel region and a second source-drain connection region located on both sides of the second channel region; the resistivity of the first active layer corresponding to the first source-drain connection region is different from the resistivity of the second active layer corresponding to the second source-drain connection region.

[0171] In an exemplary embodiment, the driving structure layer is formed on a substrate, comprising: sequentially forming a first insulating layer and a semiconductor layer on the substrate, the semiconductor layer comprising a first active layer and a second active layer; forming a second insulating layer and a first conductive layer on the substrate, the first conductive layer comprising a first gate electrode and a second gate electrode; performing two ion implantation treatments on the first active layer and one ion implantation treatment on the second active layer, so that the first active layer forms a first channel region and a first source-drain connection region, and the second active layer forms a second channel region and a second source-drain connection region.

[0172] In an exemplary embodiment, the first active layer is subjected to two ion implantation treatments and the second active layer is subjected to one ion implantation treatment, comprising: using the first gate electrode and the second gate electrode as shielding, performing a first ion implantation treatment on the first active layer and the second active layer, wherein an area of ​​the first active layer not shielded by the first gate electrode forms a first source-drain connection area, and an area of ​​the first active layer shielded by the first gate electrode forms a first channel area; an area of ​​the second active layer not shielded by the second gate electrode forms a second source-drain connection area, and an area of ​​the second active layer shielded by the second gate electrode forms a second channel area; forming a photoresist layer on the substrate, wherein the photoresist layer covers the second active layer and the second gate electrode; and performing a second ion implantation treatment on the first active layer using the first gate electrode as shielding.

[0173] In an exemplary embodiment, in the first ion implantation process on the first active layer and the second active layer, the dose of the implanted ions is: 1E10cm -2 To 1E13cm -2 In the second ion implantation treatment of the first active layer, the dose of the implanted ions is: 1E13cm -2 To 1E16cm -2 .

[0174] In an exemplary embodiment, the first active layer is subjected to two ion implantation treatments and the second active layer is subjected to one ion implantation treatment, comprising: forming a photoresist layer on the substrate, the photoresist layer covering the second active layer and the second gate electrode; using the first gate electrode as a shield, performing a first ion implantation treatment on the first active layer, the area of ​​the first active layer not shielded by the first gate electrode forms a first source-drain connection area, and the area of ​​the first active layer shielded by the first gate electrode forms a first channel area; stripping the photoresist layer; using the first gate electrode and the second gate electrode as shields, performing a second ion implantation treatment on the first active layer, performing a first ion implantation treatment on the second active layer, the area of ​​the second active layer not shielded by the second gate electrode forms a second source-drain connection area, and the area of ​​the second active layer shielded by the second gate electrode forms a second channel area.

[0175] In an exemplary embodiment, in the first ion implantation process on the first active layer, the dose of the implanted ions is: 1E13cm -2 To 1E16cm -2 In the second ion implantation treatment of the first active layer and the first ion implantation treatment of the second active layer, the dose of the implanted ions is: 1E10cm -2 To 1E13cm -2 .

[0176] The inventors of this application have found through research that the ion implantation conditions in the source-drain connection region of the LTPS transistor have a significant impact on the operating current Ion and the leakage current Ioff of the transistor. On this basis, the method for preparing the display substrate proposed in the embodiment of the present disclosure reduces the leakage current of the switching transistor by reducing the ion implantation dose in the source-drain region of the switching transistor, which helps to reduce the power consumption of the display substrate. The method for preparing the display substrate proposed in the embodiment of the present disclosure does not require the use of an oxidation process, and the changes to the existing process are minimal. The process is simple, the cost is lower, and it has broad application prospects. The display substrate prepared by the preparation method of the embodiment of the present disclosure can not only solve the problem of large transistor leakage current and high power consumption of the LTPS display substrate, but also solve the problem of complex process and high cost of the LTPO display substrate.

[0177] The embodiments of the present disclosure also provide a display device, including the display substrate described in any of the above embodiments. The display device can be: an OLED display, a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, or any other product or component with a display function, and the embodiments of the present disclosure are not limited thereto.

[0178] Although the embodiments disclosed in the present invention are as above, the contents described are only embodiments adopted to facilitate understanding of the present invention and are not intended to limit the present invention. Any technician in the field to which the present invention belongs can make any modifications and changes in the form and details of implementation without departing from the spirit and scope disclosed in the present invention, but the patent protection scope of the present invention shall still be subject to the scope defined in the attached claims.

Claims

1. A display substrate, characterized in that: The invention comprises a driving structure layer arranged on a substrate, the driving structure layer comprises a pixel driving circuit, the pixel driving circuit comprises at least a first type transistor and a second type transistor, the first type transistor is a driving transistor, the second type transistor is a switching transistor, the first type transistor comprises at least a first active layer, and the second type transistor comprises at least a second active layer; the first active layer comprises a first channel region and first source-drain connection regions located on both sides of the first channel region, the second active layer comprises a second channel region and second source-drain connection regions located on both sides of the second channel region; the resistivity of the first active layer corresponding to the first source-drain connection region is lower than the resistivity of the second active layer corresponding to the second source-drain connection region; The first active layer corresponding to the first source-drain connection region and the second active layer corresponding to the second source-drain connection region both contain doped N-type ions, and the content of N-type ions in the first active layer corresponding to the first source-drain connection region is 1E18 cm -3 to 1E21 cm -3 The content of N-type ions in the second active layer corresponding to the second source-drain connection region is 1E15 cm -3 to 1E18 cm -3 ;or, The first active layer corresponding to the first source-drain connection region and the second active layer corresponding to the second source-drain connection region both contain doped P-type ions, and the content of the P-type ions in the first active layer corresponding to the first source-drain connection region is 1E18 cm -3 to 1E21 cm -3 The content of P-type ions in the second active layer corresponding to the second source-drain connection region is 1E15cm -3 to 1E18 cm -3 .

2. The display substrate according to claim 1, characterized in that: The resistivity of the first active layer corresponding to the first source-drain connection region is 1E-4Ω·cm to 1E-1Ω·cm; the resistivity of the second active layer corresponding to the second source-drain connection region is 1E-1Ω·cm to 1E2Ω·cm.

3. The display substrate according to claim 1, characterized in that: The N-type ions include one or more of the following ions: phosphorus ions, nitrogen ions, arsenic ions, and antimony ions.

4. The display substrate according to claim 1, characterized in that: The P-type ions include one or more of the following ions: boron ions, aluminum ions, gallium ions, and indium ions.

5. A display device, characterized in that: The display substrate comprises the display substrate as claimed in any one of claims 1 to 4.

6. A method for preparing a display substrate, characterized in that: include: A driving structure layer is formed on a substrate, the driving structure layer includes a pixel driving circuit, the pixel driving circuit includes at least a first type transistor and a second type transistor, the first type transistor is a driving transistor, the second type transistor is a switching transistor, the first type transistor includes at least a first active layer, and the second type transistor includes at least a second active layer; the first active layer includes a first channel region and a first source-drain connection region located on both sides of the first channel region, the second active layer includes a second channel region and a second source-drain connection region located on both sides of the second channel region; the resistivity of the first active layer corresponding to the first source-drain connection region is lower than the resistivity of the second active layer corresponding to the second source-drain connection region; The first active layer corresponding to the first source-drain connection region and the second active layer corresponding to the second source-drain connection region both contain doped N-type ions, and the content of N-type ions in the first active layer corresponding to the first source-drain connection region is 1E18 cm -3 to 1E21 cm -3 The content of N-type ions in the second active layer corresponding to the second source-drain connection region is 1E15 cm -3 to 1E18 cm -3 ;or, The first active layer corresponding to the first source-drain connection region and the second active layer corresponding to the second source-drain connection region both contain doped P-type ions, and the content of the P-type ions in the first active layer corresponding to the first source-drain connection region is 1E18 cm -3 to 1E21 cm -3 The content of P-type ions in the second active layer corresponding to the second source-drain connection region is 1E15cm -3 to 1E18 cm -3 .

7. The preparation method according to claim 6, characterized in that: The step of forming a driving structure layer on a substrate comprises: Sequentially forming a first insulating layer and a semiconductor layer on a substrate, wherein the semiconductor layer comprises at least a first active layer and a second active layer; forming a second insulating layer and a first conductive layer on the semiconductor layer, wherein the first conductive layer comprises at least a first gate electrode and a second gate electrode; The first active layer is subjected to two ion implantation treatments, and the second active layer is subjected to one ion implantation treatment, so that the first active layer forms a first channel region and a first source-drain connection region, and the second active layer forms a second channel region and a second source-drain connection region, and the resistivity of the first active layer corresponding to the first source-drain connection region is lower than the resistivity of the second active layer corresponding to the second source-drain connection region.

8. The preparation method according to claim 7, characterized in that: The step of performing two ion implantation processes on the first active layer and one ion implantation process on the second active layer comprises: The first active layer and the second active layer are subjected to a first ion implantation process with the first gate electrode and the second gate electrode as shielding, so that a region of the first active layer not shielded by the first gate electrode forms a first source-drain connection region, and a region of the first active layer shielded by the first gate electrode forms a first channel region; a region of the second active layer not shielded by the second gate electrode forms a second source-drain connection region, and a region of the second active layer shielded by the second gate electrode forms a second channel region; A photoresist layer is formed on the substrate, the photoresist layer covers the second active layer and the second gate electrode; and a second ion implantation process is performed on the first active layer with the first gate electrode as a shield.

9. The preparation method according to claim 8, characterized in that: In the first ion implantation process for the first active layer and the second active layer, the dose of the implanted ions is: 1E10 cm -2 to 1E13 cm -2 ; In the second ion implantation treatment of the first active layer, the dose of the implanted ions is: 1E13 cm -2 to 1E16 cm -2 .

10. The preparation method according to claim 7, characterized in that: The step of performing two ion implantation processes on the first active layer and one ion implantation process on the second active layer comprises: Forming a photoresist layer on the substrate, the photoresist layer covering the second active layer and the second gate electrode; performing a first ion implantation process on the first active layer with the first gate electrode as a shield, so that the area of ​​the first active layer not shielded by the first gate electrode forms a first source-drain connection area, and the area of ​​the first active layer shielded by the first gate electrode forms a first channel area; The photoresist layer is peeled off; with the first gate electrode and the second gate electrode as shielding, the first active layer is subjected to a second ion implantation treatment, and the second active layer is subjected to a first ion implantation treatment, the area of ​​the second active layer not shielded by the second gate electrode forms a second source-drain connection area, and the area of ​​the second active layer shielded by the second gate electrode forms a second channel area.

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