A first-order NS-SAR ADC and analog-to-digital conversion method based on sampling noise suppression technology

Abstract

The present invention relates to a noise shaping successive approximation analog-to-digital converter, and in particular to a first-order NS-SAR ADC and an analog-to-digital conversion method based on sampling noise suppression technology, which is used to solve the problem that the existing NS-SAR ADC usually suppresses sampling noise by increasing the size of input capacitors in order to meet the signal-to-noise ratio requirements, and the large input capacitors make the design cost of ADC input drivers and reference buffers very high, and increase the design complexity of ADC input drivers and reference buffers. The first-order NS-SAR ADC based on sampling noise suppression technology includes a power supply module, a capacitor array, a sampling noise suppression structure, a first-order passive noise shaping structure, a comparator and digital logic. The present invention uses sampling noise suppression technology to reduce the area and power consumption of the capacitor array, reduce the design difficulty of the input reference level, and use oversampling and noise shaping technology to improve the accuracy of the analog-to-digital converter.

Description

Technical Field

[0001] The invention relates to a noise shaping successive approximation analog-to-digital converter, and in particular to a first-order NS-SAR ADC and an analog-to-digital conversion method based on sampling noise suppression technology. Background Art

[0002] As the integrated circuit manufacturing process continues to improve according to Moore's Law, the process gradually moves towards lower nodes, and the proportional reduction of process feature size improves the speed, power consumption and integration of digital integrated circuits. It is precisely because of the advantage of SAR ADC (successive approximation analog-to-digital converter) based on digital circuits that it is better compatible with advanced processes and is very suitable for on-chip system integration. However, for high-resolution applications, its power efficiency will decrease due to the strict requirements on comparator noise and the exponentially growing capacitor DAC (digital-to-analog converter) array. △-∑ ADC (Delta-Sigma analog-to-digital converter) is a widely used architecture for high-resolution applications. Taking advantage of oversampling and noise shaping, it can achieve high resolution through low-resolution quantizers and DACs. However, △-∑ ADC usually requires high-performance active integrators based on operational amplifiers, which consumes a lot of power and has poor compatibility with advanced processes.

[0003] NS-SAR ADC (Noise Shaping Successive Approximation Analog-to-Digital Converter) combines the advantages of SAR ADC's simple structure, low power consumption, high degree of digitization, and noise shaping in △-∑ ADC to achieve high precision. It only requires a small number of conversion bits to achieve high precision and allows for larger conversion errors, thus reducing the requirements for comparator noise and achieving low power consumption and high precision at the same time. Therefore, NS-SAR ADC is very suitable for low-speed and high-precision applications that require high power efficiency.

[0004] At the same time, existing noise shaping solutions still face a major challenge when pushing for higher resolutions: sampling noise. In order to meet the signal-to-noise ratio requirements, sampling noise is usually suppressed by increasing the size of the input capacitor. Large input capacitors make the design cost of ADC input drivers and reference buffers very high, and their power, area, and design complexity are usually much higher than the ADC itself. Summary of the invention

[0005] The purpose of the present invention is to solve the problem that the existing NS-SAR ADC usually suppresses sampling noise by increasing the size of input capacitor in order to meet the signal-to-noise ratio requirement, and the large input capacitor makes the design cost of ADC input driver and reference buffer very high and increases the design complexity of ADC input driver and reference buffer, and to provide a first-order NS-SAR ADC and analog-to-digital conversion method based on sampling noise suppression technology.

[0006] In order to solve the deficiencies of the above-mentioned prior art, the present invention provides the following technical solutions:

[0007] A first-order NS-SAR ADC based on sampling noise suppression technology includes a power module, a capacitor array, a first-order passive noise shaping structure, a comparator and digital logic, and is special in that: it also includes a sampling noise suppression structure;

[0008] The input end of the capacitor array is connected to the output end of the power module or the analog input signal V in , the output end is connected to the input end of the sampling noise suppression structure;

[0009] The sampling noise suppression structure is used to collect the analog input signal V in With the noise information, the sampling noise suppression structure includes a switch Φ S1 , switch Φ S2 , amplifier A and sampling capacitor C2; the input end of the sampling noise suppression structure is used to pass the switch Φ S1 Connect the external common mode voltage V cm1 , the output terminal is used to switch Φ S2 Connect the external common mode voltage V cm2 , and connected to the first input terminal of the comparator, the amplifier A and the sampling capacitor C2 are sequentially connected between the input terminal and the output terminal of the sampling noise suppression structure;

[0010] The first-order passive noise shaping structure is used to collect the residual voltage on the capacitor array after the SAR ADC conversion phase of the current cycle is completed and participate in the quantization process of the new analog input signal in the next cycle as a feedforward integration signal; the first-order passive noise shaping structure includes an integration capacitor C1 and a switch Φ1; one end of the switch Φ1 is connected to the top plate of the capacitor array, the other end of the switch Φ1 is connected to one end of the integration capacitor C1 and the second input end of the comparator, and the other end of the integration capacitor C1 is grounded;

[0011] The output end of the comparator is connected to the input end of the digital logic, and is used to sum the inputs of the first input end of the comparator and the second input end of the comparator to obtain a comparison result, and output the comparison result to the digital logic;

[0012] One output end of the digital logic is connected to the input end of the power module, and is used to control the switch of the bottom plate of the capacitor array and the output of the power module (1) according to the comparison result to complete the successive approximation process. Another output end of the digital logic is used to output a digital output signal D out .

[0013] Furthermore, the capacitor array includes a plurality of capacitor circuits connected in parallel, each capacitor circuit includes a switch Φ connected in series. S3 and capacitor; the switch ΦS3 The first static contact is connected to the output end of the power module, and the second static contact is connected to the analog input signal V in , the moving contact is connected to one end of the capacitor.

[0014] Furthermore, the power supply module includes a common mode voltage V cm , negative reference voltage V refn and the positive reference voltage V refp , common mode voltage V cm , negative reference voltage V refn and the positive reference voltage V refp The output terminals of the power modules are connected through corresponding switches. The output of the power modules is the common mode voltage V cm , negative reference voltage V refn and the positive reference voltage V refp The common mode voltage V cm Used to set the midpoint voltage of the capacitor array; the negative reference voltage V refn and the positive reference voltage V refp Used to define the quantization range of the capacitor array.

[0015] Furthermore, the comparator is configured to switch Φ c Control, the gain of the first input terminal of the comparator and the second input terminal of the comparator is 1:g.

[0016] Furthermore, the size of the sampling capacitor C2 is C, the size of the integrating capacitor C1 is 3C, and the gain of the comparator is 1:g is 1:3.

[0017] Furthermore, the digital output signal D out With the analog input signal V in After z-transformation, they are respectively digital output signals D out (z) and the analog input signal V in (z), digital output signal D out (z) and the analog input signal V in (z) satisfy the following relationship:

[0018] D out (z) = V in (z)+0.75z -1 ·n s (z)+3z -1 n 1，Φ1 (z)+(1-0.75z -1 )

[0019] (Q(z)+n4(z)+n5(z))

[0020] Where n s(z) represents sampling noise, n 1，Φ1 (z) represents the integrated thermal noise, Q(z) represents the quantization noise, n4(z) represents the comparator noise, and n5(z) represents the DAC thermal noise.

[0021] At the same time, the present invention also provides an analog-to-digital conversion method of a first-order NS-SAR ADC, which has the following special features:

[0022] Step 1, constructing the first-order NS-SAR ADC based on sampling noise suppression technology as described in claim 1;

[0023] Step 2: Control switch Φ S1 , switch Φ S2 Closed, switch Φ1 is opened, and the input of the capacitor array controlled by digital logic is connected to the analog input signal V in ;

[0024] Then control the switch Φ S1 Disconnect and use amplifier A and sampling capacitor C2 to simulate the input signal V in After sampling the noise information, the switch Φ S2 disconnecting and connecting the input end of the capacitor array to the output end of the power module by controlling the digital logic;

[0025] Step 3: Set the analog input signal V in and the feedforward integral signal V int The comparator adds the gain in the ratio of 1:g, and then the digital logic controls the output of the power module according to the comparison result of the comparator to complete the process of successive approximation;

[0026] Step 4: Control switch Φ1 to close, and collect the residual voltage V on the capacitor array after step 3 through the integrating capacitor C1. res , used as the feedforward integration signal V in the next cycle int The new analog input signal V in The quantification process;

[0027] Step 5: Repeat steps 2 to 4 and collect the digital output signal D of the digital logic output in each cycle. out , until the preset period is reached and the process ends.

[0028] Compared with the prior art, the present invention has the following beneficial effects:

[0029] (1) The present invention discloses a first-order NS-SAR ADC based on sampling noise suppression technology. Compared with the prior art 1, the integrated thermal noise in the noise shaping stage is reduced by a direct integration structure (first-order passive noise shaping structure), and the branch gain required for the comparator of the multi-channel input port is reduced. When realizing the same NTF as the prior art 1, the first-order passive noise technology proposed by the present invention is applied, and the branch gain of the comparator of the multi-channel input port is reduced from 1:4 (prior art 1) to 1:3 (the present invention), thereby saving a part of the power consumption. Compared with the prior art 2, the sampling noise suppression technology of the present invention only requires an additional operational amplifier and switch, thereby reducing the sampling noise of the noise shaping SAR ADC, and further reducing the scale of the capacitor array. Specifically, compared with the prior art 1, the scale of the capacitor array of the present invention is reduced by 4 times, and compared with the prior art 2, the sampling noise is reduced by 1 / 4 times, the design difficulty of the input driver and reference buffer of the ADC is reduced, and the signal-to-noise ratio and effective number of bits of the ADC are improved.

[0030] (2) In a first-order NS-SAR ADC based on sampling noise suppression technology of the present invention, sampling noise suppression is performed through amplifier A and sampling capacitor C2. Under the same noise budget, the size of the capacitor array is reduced compared with the prior art 2. Specifically, under the condition that the size of the capacitor array is the same, the present invention performs sampling noise suppression through amplifier A and sampling capacitor C2. The sampling noise of the present invention is reduced by 1 / 4 times compared with the sampling noise of the prior art 2, thereby improving the accuracy of the ADC. (The sampling noise here refers to the reference level relative to the capacitor array. The SAR ADC conversion process is completed by flipping the reference level of the bottom plate of the capacitor array. The area of ​​the capacitor array is reduced, and the difficulty and cost of the reference level drive design will be reduced), so that the ADC conversion speed becomes faster and the difficulty and cost of the input reference level design become lower.

[0031] (3) In a first-order NS-SAR ADC based on sampling noise suppression technology of the present invention, the accuracy of the ADC is greatly improved by using the integral capacitor C1 and the switch Φ1. Specifically, compared with the SAR ADC, the quantization noise of the ADC is reduced, and the transfer function of the quantization noise is changed from 1 to (1-0.75z -1 ), which improves the accuracy of the ADC, and the coefficient of its noise transfer function is determined by the ratio between the capacitors and the gain of the amplifier A input to the tube, so it has PVT (process, voltage, temperature) stability.

[0032] (4) In the first-order NS-SAR ADC based on sampling noise suppression technology of the present invention, only the timing is modified, which can significantly improve the accuracy and stability of the ADC, thereby enabling it to cope with more complex practical application scenarios.

[0033] (5) In a first-order NS-SAR ADC based on sampling noise suppression technology of the present invention, the four noise sources of sampling noise, quantization noise, comparator noise and DAC thermal noise are suppressed, so that the signal-to-noise ratio and effective number of bits of the ADC can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 It is a structural diagram of the NS-SAR ADC proposed in prior art 1;

[0035] Figure 2 yes Figure 1 The corresponding timing diagram;

[0036] Figure 3 yes Figure 1 The corresponding noise signal flow graph;

[0037] Figure 4 It is a structural diagram of the NS-SAR ADC proposed in prior art 2;

[0038] Figure 5 yes Figure 4 The corresponding timing diagram;

[0039] Figure 6 yes Figure 4 The corresponding noise signal flow graph;

[0040] Figure 7 is a structural diagram of an embodiment of a NS-SAR ADC based on sampling noise suppression technology of the present invention;

[0041] Figure 8 yes Figure 7 The corresponding timing diagram;

[0042] Fig. 9 yes Figure 7 Corresponding noisy signal flow graph.

[0043] Figure 7 Explanation of the reference numerals: 1 - power supply module; 2 - capacitor array; 3 - first-order passive noise shaping structure; 4 - sampling noise suppression structure; 5 - comparator; 6 - digital logic. DETAILED DESCRIPTION

[0044] The present invention will be further described below in conjunction with the accompanying drawings and exemplary embodiments.

[0045] Figures 1 to 3 They are the circuit diagram, timing diagram and noise signal flow diagram of the NS-SAR ADC proposed in the prior art 1 (Liu Jiaxin. Research on key technologies of high-efficiency analog-to-digital converter chips based on noise shaping [D]. University of Electronic Science and Technology of China, 2018.).

[0046] Figures 4 to 6 They are the circuit diagram, timing diagram and noise signal flow diagram of the NS-SAR ADC proposed in prior art 2 (Liu Jiaxin. Research on key technologies of high-efficiency analog-to-digital converter chip based on noise shaping [D]. University of Electronic Science and Technology of China, 2018.). The NS-SAR ADC includes a sampling capacitor Integral capacitor Integral switch Comparator, switch The sampling capacitor The size of C is the integral capacitor The size is 3C, and the comparator input gain is g 02 =3; the system transfer function of the NS-SAR ADC is:

[0047]

[0048] In the formula, Indicates the output digital signal, represents the analog input signal, z represents the z domain, represents the sampling noise, is the integrated thermal noise, Q 02 (z) represents the quantization noise, represents the comparator noise, represents the DAC thermal noise.

[0049] Figure 3 middle Figure 6 middle The noise shaping effect of prior art 1 and prior art 2 only suppresses quantization noise, comparator noise and DAC thermal noise, but has no suppressing effect on sampling noise and integrated thermal noise. Compared with prior art 1, prior art 2 achieves the same remaining noise transfer function equal to 1-0.75z -1 Under the condition of , the switch thermal noise of the margin acquisition and capacitor zeroing is omitted. When the total capacitor area is the same, the in-band switch thermal noise of the prior art 2 is reduced by 4 times compared with the prior art 1. The reduced DAC capacitance can not only reduce the power consumption and area of ​​the ADC, but also reduce the DAC settling time during the SAR ADC conversion stage, thereby increasing the speed of the ADC.

[0050] The present invention suppresses sampling noise based on the noise shaping structure of prior art 2. The sampling noise suppression technology suppresses sampling noise during the conversion process, which can be understood as the idea of ​​offsetting the output digital code and the offset voltage. However, the replica of the sampling noise copied in the SAR ADC conversion stage is shaped, so the sampling noise cannot be completely eliminated.

[0051] Reference Figure 7The present invention discloses a first-order NS-SAR ADC based on sampling noise suppression technology, including a capacitor array 2, a sampling noise suppression structure 4, a first-order passive noise shaping structure 3, a comparator 5, a digital logic 6 and a power supply module 1.

[0052] The power module 1 includes a common mode voltage V cm , negative reference voltage V refn and the positive reference voltage V refp , common mode voltage V cm Used to set the midpoint voltage of capacitor array 2; negative reference voltage V refn and the positive reference voltage V refp Used to define the quantization range of capacitor array 2. Common mode voltage V cm , negative reference voltage V refn and the positive reference voltage V refp The output terminals of the power module 1 are connected through corresponding switches. The output of the power module 1 is the common mode voltage V cm , negative reference voltage V refn and the positive reference voltage V refp one of the.

[0053] The capacitor array 2 includes a plurality of capacitor circuits connected in parallel, each of which includes a switch Φ connected in series. S3 and capacitors, the input end of capacitor array 2 is connected to the output end of power module 1 or the analog input signal V in , the output end is connected to the input end of the sampling noise suppression structure 4; the above switch Φ S3 The first static contact is connected to the output end of the power module 1, and the second static contact is connected to the analog input signal V in , the moving contact is connected to one end of the capacitor.

[0054] The sampling noise suppression structure 4 is used to collect analog input signals and noise information. The sampling noise suppression structure 4 includes an amplifier A and a sampling capacitor C2. The input end of the sampling noise suppression structure 4 is connected to an external common mode voltage V cm1 A switch is provided between S1 , the output terminal passes through the switch Φ S2 Connect the external common mode voltage V cm2 , and connected to the first input terminal of the comparator 5. The above-mentioned amplifier A and sampling capacitor C2 are connected between the input terminal and the output terminal of the sampling noise suppression structure 4 in sequence. The amplification factor of the amplifier A is A, which is used to amplify the voltage change on the sampling capacitor C2, thereby reducing the error caused by switching and circuit noise.

[0055] The first-order passive noise shaping structure 3 is used to collect the residual voltage on the capacitor array 2 after the SAR ADC conversion phase of this cycle is completed and participate in the quantization process of the new analog input signal in the next cycle as a feedforward integration signal; the first-order passive noise shaping structure 3 includes an integration capacitor C1 and a switch Φ1; one end of the switch Φ1 is connected to the top board of the capacitor array 2, the other end of the switch Φ1 is connected to one end of the above-mentioned integration capacitor C1 and the second input end of the comparator 5, and the other end of the integration capacitor C1 is grounded.

[0056] The comparator 5 is used to sum the input of the first input terminal of the comparator 5 and the second input terminal of the comparator 5 to obtain a comparison result, and output the comparison result to the digital logic 6. The comparator 5 is switched by the switch Φ c The gain of the first input terminal of the comparator 5 and the second input terminal of the comparator 5 is controlled to be 1:g. The output terminal of the comparator 5 is connected to the input terminal of the digital logic 6.

[0057] An output terminal of the digital logic 6 is connected to the input terminal of the power module 1, and is used to control the switch of the bottom plate of the capacitor array 2 and the output of the power module 1 according to the comparison result to complete the successive approximation process, specifically to control the common mode voltage V cm , negative reference voltage V refn and the positive reference voltage V refp The corresponding switch of the closing or opening is used to control the output of the power module 1, and the control switch Φ S3 Connect to the output of power module 1 or connect to the analog input signal V in The other output terminal of the digital logic 6 is used to output the digital output signal D out .

[0058] The above digital output signal D out With the analog input signal V in After z-transformation, they are respectively digital output signals D out (z) and the analog input signal V in (z), the residual voltage V finally converted by the embodiment of the present invention res (z) and the analog input signal V in (z) and the digital output signal D out (z) have the following relationship in the z domain:

[0059] V res (z) = D out (z)-V in (z)

[0060] After the SAR ADC conversion stage is completed, the final residual voltage V res(z) Noise shaping is performed to obtain the feedforward integral signal V int (z), in the next cycle the analog input signal V in (z) and the feedforward integral signal V int (z) is added by the ratio of the gain 1:g of comparator 5; assuming that the system transfer function of the passive loop filter is H(z), the z-domain output of the passive loop filter can be obtained as:

[0061] V int (z)=H(z)V res (z)

[0062] In the embodiment of the present invention, the size of the sampling capacitor C2 is C, the size of the integrating capacitor C1 is 3C, the gain 1:g of the comparator 5 is 1:3, and the digital output signal D is obtained. out (z) and the analog input signal V in (z) satisfy the following relationship:

[0063] D out (z) = V in (z)+0.75z -1 ·n s (z)+3z -1 n 1，Φ1 (z)+(1-0.75z -1 )

[0064] (Q(z)+n4(z)+n5(z))

[0065] Where n s (z) represents sampling noise, n 1，Φ1 (z) represents the integrated thermal noise, Q(z) represents the quantization noise, n4(z) represents the comparator noise, and n5(z) represents the DAC thermal noise.

[0066] The timing diagram of the embodiment of the present invention is as follows Figure 8 As shown, each cycle is divided into three phases, namely, the sampling phase t1, the SAR ADC conversion phase t2 and the noise shaping phase t3.

[0067] like Fig. 9 The figure shows a noise signal flow diagram of an embodiment of the present invention, where b = C1 / (C DAC +C1), C DAC 2 represents a capacitor array. Under the action of a passive loop filter, the present invention introduces a first-order passive noise shaping structure 3 into the conversion loop of the NS-SAR ADC. Only one additional capacitor and switch are required, the structure is simple, and the system complexity and power consumption are effectively reduced.

[0068] There is no sampling capacitor in the passive loop filter, thereby removing the kT / C noise caused by the residual sampling capacitor and capacitor zeroing.

[0069] The sampling noise suppression technology only requires the sampling capacitor C2 and the amplifier A. The amplifier A does not require PVT robustness and has a small amplification factor, which reduces the scale of the capacitor array 2 and the design difficulty of the input reference level, saving power consumption and cost.

[0070] The present invention also discloses an analog-to-digital conversion method of a first-order NS-SAR ADC, comprising the following steps:

[0071] Step 1, construct the above-mentioned first-order NS-SAR ADC based on sampling noise suppression technology;

[0072] Step 2: Control switch Φ S1 , switch Φ S2 Close, switch Φ1, switch Φ c The input terminal of the capacitor array 2 is disconnected and connected to the analog input signal V by the digital logic 6. in ;

[0073] Then control the switch Φ S1 Disconnect and use amplifier A and sampling capacitor C2 to simulate the input signal V in After sampling the noise information, the switch Φ S2 Disconnect, and control the input end of the capacitor array 2 to be connected to the output end of the power module 1 by the digital logic 6;

[0074] Step 3: Control switch Φ c Close, the analog input signal V in and the feedforward integral signal V int The gain is added by comparator 5 at a ratio of 1:g, and then the digital logic 6 controls the common mode voltage V in the power module 1 according to the comparison result of comparator 5. cm , negative reference voltage V refn and the positive reference voltage V refp The corresponding switch is closed or opened to control the output of the power module 1 at the common mode voltage V cm , negative reference voltage V refn and the positive reference voltage V refp Switch between them to complete the process of successive approximation;

[0075] Step 4: Control switch Φ1 to close, and collect the residual voltage V on capacitor array 2 after step 3 through integrating capacitor C1. res , used as the feedforward integration signal V in the next cycle int The new analog input signal V in The quantification process;

[0076] Step 5: Repeat steps 2 to 4 and collect the digital output signal D output by the digital logic 6 in each cycle. out , until the preset period is reached and the process ends.

Claims

1. A first-order NS-SAR ADC based on sampling noise suppression technology, comprising a power module (1), a capacitor array (2), a first-order passive noise shaping structure (3), a comparator (5) and digital logic (6), characterized in that: Also included is a sampling noise suppression structure (4); The power module (1) comprises a common mode voltage , negative reference voltage and positive reference voltage , common mode voltage , negative reference voltage and positive reference voltage The output terminals of the power module (1) are connected through corresponding switches, and the output of the power module (1) is a common mode voltage. , negative reference voltage and positive reference voltage One of the common mode voltage Used to set the midpoint voltage of the capacitor array (2); the negative reference voltage and positive reference voltage Used to define the quantization range of the capacitor array (2); The input end of the capacitor array (2) is connected to the output end of the power module (1) or the analog input signal , the output end is connected to the input end of the sampling noise suppression structure (4); The sampling noise suppression structure (4) is used to collect analog input signals With the noise information, the sampling noise suppression structure (4) includes a switch ,switch , Amplifier and sampling capacitor ; The input of the sampling noise suppression structure (4) is used to pass the switch Connect external common mode voltage , the output terminal is used to switch Connect external common mode voltage , and connect the first input terminal of the comparator (5), the amplifier and sampling capacitor Connected in sequence between the input terminal and the output terminal of the sampling noise suppression structure (4); The first-order passive noise shaping structure (3) is used to collect the residual voltage on the capacitor array (2) after the SAR ADC conversion phase of the current cycle is completed and participates in the quantization process of the new analog input signal as a feedforward integration signal in the next cycle; The first-order passive noise shaping structure (3) includes an integrating capacitor and switch ;switch Connect one end of the capacitor array (2) to the top board, switch The other end of the integrating capacitor is connected to and the second input terminal of the comparator (5), the integrating capacitor The other end is grounded; The output end of the comparator (5) is connected to the input end of the digital logic (6), and is used to sum the input of the first input end of the comparator (5) and the input of the second input end of the comparator (5) to obtain a comparison result, and output the comparison result to the digital logic (6); One output end of the digital logic (6) is connected to the input end of the power module (1) and is used to control the switch of the bottom plate of the capacitor array (2) and the output of the power module (1) according to the comparison result to complete the successive approximation process. Another output end of the digital logic (6) is used to output a digital output signal. ; The digital output signal With analog input signal After z-transformation, they are respectively digital output signals and analog input signal , digital output signal and analog input signal The following relationship is satisfied: In the formula, represents the sampling noise, represents the integrated thermal noise, represents the quantization noise, represents the comparator noise, represents the DAC thermal noise.

2. The first-order NS-SAR ADC based on sampling noise suppression technology according to claim 1, characterized in that: The capacitor array (2) comprises a plurality of capacitor circuits connected in parallel, each capacitor circuit comprising a switch connected in series and capacitor; the switch The first static contact is connected to the output end of the power module (1), and the second static contact is connected to the analog input signal , the moving contact is connected to one end of the capacitor.

3. The first-order NS-SAR ADC based on sampling noise suppression technology according to claim 1, characterized in that: The comparator (5) is switched The gain of the first input terminal of the comparator (5) and the second input terminal of the comparator (5) is controlled to be 1:g.

4. The first-order NS-SAR ADC based on sampling noise suppression technology according to claim 3, characterized in that: The sampling capacitor The size is , integrating capacitor The size is , the gain of comparator (5) is 1:g and 1:

3.

5. A method for analog-to-digital conversion of a first-order NS-SAR ADC, characterized in that: The steps include: Step 1, constructing the first-order NS-SAR ADC based on sampling noise suppression technology as described in claim 1; Step 2: Control switch ,switch Close, switch disconnected, and the input terminal of the capacitor array (2) is connected to the analog input signal by the digital logic (6) ; Then control the switch Disconnect and use amplifier and sampling capacitor For analog input signals Sampling the noise information, and then controlling the switch disconnecting, and connecting the input end of the capacitor array (2) to the output end of the power module (1) by controlling the digital logic (6); Step 3: Analog input signal and the feedforward integral signal The comparator (5) adds the gain in a ratio of 1:g, and then the digital logic (6) controls the output of the power module (1) according to the comparison result of the comparator (5), thereby completing the process of successive approximation; Step 4: Control switch Closed, through the integrating capacitor After collecting step 3, the residual voltage on the capacitor array (2) is , used as a feedforward integration signal in the next cycle Involving new analog input signals The quantification process; Step 5: Repeat steps 2 to 4 and collect the digital output signal output by the digital logic (6) in each cycle. , until the preset period is reached and the process ends.

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