A multi-core brain-like processor based on instruction set and working method

Abstract

The present invention relates to a multi-core brain-like processor and a working method based on an instruction set, belonging to the field of electronic information technology. The multi-core brain-like processor of the present invention includes a 4-directional LVDS interface and a data proxy unit, and a 2-D mesh chip network composed of mn routers, each router is connected to a cortical column core, a cortical column core is composed of a scheduling core and a neuron cluster, and a neuron cluster includes multiple neuron cores. The present invention can accelerate the search of sparse weights, reduce the power consumption of the processor operation in an event-driven computing mode, and can support a variety of neuron models, synaptic models and on-chip learning algorithms in the form of instructions, which can meet the needs of the model that is constantly evolving in the future, help the flexible deployment of brain simulation and brain-like pulse neural network models, and support brain-like intelligent high-energy-efficiency accelerated computing.

Description

Technical Field

[0001] The present invention belongs to the field of electronic information technology, and specifically relates to an instruction set-based multi-core brain-like processor and a working method. Background Art

[0002] Brain-like computing draws on the brain's information processing mechanism and physiological structure, and models the neurons, axons, and dendrites of organisms, making it similar to the brain in terms of information processing mechanism and similar to humans in terms of cognitive behavior and intelligence level. A brain-like processor is a processor that is similar to the brain in structure and uses sparse, parallel, and asynchronous computing methods to simulate the brain with low power consumption.

[0003] Many brain-like processors have emerged in recent years. IBM's TrueNorth processor has a total of 4096 neuron cores, each with 256 neurons and axons, forming 64,000 synapses in the form of cross switches, and supports configurable IF neuron models. Intel's multi-core brain-like processor Loihi has 128 neuron cores and 3 x86 control cores. Each computing core can support up to 1024 LIF neurons and 1 million synapses, while supporting on-chip learning algorithms based on pulse time-dependent plasticity. Zhejiang University's Darwin chip can support 2048 LIF neurons and 400,000 synapses. Tsinghua University's Tianjic chip has 156 functional cores and can support up to 40,000 LIF neurons and 10 million synapses.

[0004] Most of the existing brain-like chips use multi-core to achieve the simulation of large-scale neurons on a single chip. However, they are difficult to effectively support the sparse synaptic connection characteristics between neurons in organisms, which results in a large waste of storage resources. At the same time, only supporting specific neuron models limits the scope of application of the chip. Nowadays, various large brain-like models are constantly emerging, the demand for brain simulation is increasing, the model size and computing power requirements are increasing rapidly, and the existing brain-like processors are difficult to effectively support the ever-changing algorithm models and highly sparse brain network topologies. To this end, it is necessary to design a flexible and programmable brain-like processor that can make full use of the sparsity of neuronal pulses and the sparsity of neuronal connections. Summary of the invention

[0005] The technical problem to be solved by the present invention is to address the shortcomings of existing brain-like processors and provide an instruction set-based many-core brain-like processor and working method, which can solve the problems of poor flexibility and sparse support capability of brain-like processors, support complex and diverse neurons, synapse models and on-chip learning algorithms, and improve the utilization rate of on-chip storage of the processor.

[0006] In order to solve the above technical problems, the technical solution adopted by the present invention is:

[0007] A multi-core brain-like processor based on an instruction set, comprising a LVDS interface and a data proxy unit in four directions, and a processor composed of m A 2-D mesh on-chip network consists of n routers, each router is connected to a cortical column core, a cortical column core consists of a scheduling core and a neuron cluster, and a neuron cluster includes multiple neuron cores.

[0008] The LDVS interface can be directly connected to the interface of other brain-like processors for data transmission between multi-core brain-like processor chips. The data proxy unit is used for the mutual conversion between the internal data of the processor and the data between processors. The router is a ten-port router, including five ports of east, south, west, north and local, each port including two input and output ports, the local port is used to transmit data packets between the cortical column core, and the four ports of east, south, west and north are used to transmit data packets with the connected router. The scheduling core includes a scheduler, an input event projection table, and an output event projection table, which are used to send and receive data packets, parse received data packets and distribute them to the internal neuron core; at the same time, the status information of the neuron core is obtained, and data packets are generated and sent to the corresponding cortical column core. The neuron core includes a seven-stage pipeline neuron execution unit, an instruction memory and a data memory, which can complete the neuron model and network calculation according to the data distributed by the scheduling core.

[0009] Furthermore, the input event projection table is stored in the form of a two-level table. The first-level table stores the tag indicating whether the data packet is received, the base address addr and the number num; the second-level table stores the neuron id and the axon id. If the data packet is received, the neuron id and the axon id are obtained from the addr item of the second-level table, and num information is read downward from this address.

[0010] Furthermore, the output event projection table is stored in the form of two-level tables, the first-level table stores the base address and the number num; the second-level table stores the routing information of the data packet. The base address is used to obtain the routing information from the address of the second-level table, and read num information from the address downward.

[0011] Furthermore, the neuron core implements an event-driven computing method based on an instruction set. The execution unit of the neuron core will perform computing only when it receives data sent by the scheduling core. The instruction memory stores model instructions and programs, and the data memory stores model data.

[0012] Furthermore, the type of the instruction is a CISC structure, and five special acceleration instructions are designed for brain-like computing, including membrane potential update instructions, sparse weight search instructions, synaptic current accumulation instructions, event reception instructions, and send pulse instructions. The membrane potential update instruction is used to accelerate the membrane potential expression based on partial differential equations; the sparse weight search instruction is used to accelerate the search for weights based on bitmap sparse representation; the synaptic current accumulation instruction is used to accelerate the model accumulation current operation; the event reception instruction is used to implement the core event-driven working mechanism; the pulse issuance instruction is used to set the model calculation results that need to be sent.

[0013] The present invention also proposes a working method of a multi-core brain-like processor based on an instruction set, the method comprising three different working phases: an initialization configuration phase, an integral issuance phase and a membrane potential update phase; information is transmitted through data packets; in the data packets, the type field is used to indicate the type of the data packet, including four types: "configuration", "unicast", "multicast" and "probe", the phase field is a data packet propagation status identifier, the tag and index fields are used to index the input event projection table, the Destination ID field is the ID of the destination cortical column core, and the Data Payload field is the data carried by the data packet.

[0014] Compared with the prior art, the present invention has the following advantages:

[0015] The multi-core brain-like processor of the present invention comprises an inter-chip data proxy unit, m The 2-D mesh chip network consists of n routers, each of which is connected to a cortical column core. A cortical column core consists of an event scheduling core and 8 fully programmable neuron cores. Based on the event trigger mechanism, the scheduling core and the neuron core only work when an event exists to achieve low-power operation. Based on the scheduling core input event projection table, output event projection table and 2-D mesh chip network, each neuron of the processor can propagate pulse information to its postsynaptic neuron through the router, and expand the number of presynaptic neurons accommodated by the neuron by splicing neurons, realizing a neural network model with complex network topology, which reduces the hardware overhead of the deployment model compared with the implementation based on the crossbar switch. The neuron core based on the instruction set can realize a variety of neuron models, synaptic models and on-chip learning algorithms. The membrane potential update instruction, sparse weight lookup instruction and synaptic current accumulation instruction reduce the delay and power consumption of model calculation by reducing unnecessary data write-back operations; the event reception instruction enables the core to work only when an event exists, and maintain a low-power quiescent state when there is no event, reducing the power consumption of the core; the pulse issuance instruction can send the model calculation results of the neuron core to the output event memory, so that the scheduling core can convert the calculation results into data packets and send them to other neuron cores. Based on the designed multi-core brain-like processor, it can meet the evolving model needs in the future, help the flexible deployment of brain simulation and brain-like pulse neural network models, and support brain-like intelligent energy-efficient accelerated computing. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 This is a schematic diagram of a multi-core brain-like processor;

[0017] Figure 2 It is a schematic diagram of the structure of the scheduling core SC;

[0018] Figure 3 A two-level representation of the input event projection table and the output event projection table of the scheduling core SC;

[0019] Figure 4 is a schematic diagram of the format of a data packet;

[0020] Figure 5 State transition diagram for the scheduling core SC to process input packets. DETAILED DESCRIPTION

[0021] In order to make the purpose, technical scheme and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention. In addition, the technical features involved in each embodiment of the present invention described below can be combined with each other as long as they do not conflict with each other. To achieve the above-mentioned purpose, the present invention adopts the following technical scheme.

[0022] The multi-core brain-like processor (hereinafter referred to as the processor) of this embodiment is as follows Figure 1 As shown in (a) of FIG. 1 , configuration information and external data information are sent from the host to any data proxy unit of the processor via the LVDS interface in the form of data packets. The data proxy unit converts the data packets into internal data packets of the processor and sends them to the router R inside the processor. The router R transmits the data packets to the Cortical column Core (CC) through the XY routing protocol. The structure of the router R is shown in Figure 1 As shown in (c), it has five local ports in the east, south, west and north, routing calculation, routing arbitration and cross switch. The number of routers is m n, where m and n are the number of rows and columns respectively. The core CC structure of the cortical column is as follows Figure 1 As shown in (b), there is a scheduling core (SC) and 8 neuron cores (NC) inside.

[0023] The structure of the scheduling core SC is as follows Figure 2 As shown in FIG. 1 , it includes a scheduler, an input event projection table, and an output event projection table, which are connected to the local input and output FIFOs of the router. The two-level representation diagram of the input event projection table and the output event projection table of the scheduling core SC is shown in FIG. Figure 3 As shown. The first-level table depth of the input event projection table is 2048, and each table entry is 30 bits, which is used to store the identifier tag, address information addr and number information num; wherein, the identifier tag, address information addr and number information num constitute the first-level table items, and the second-level table item depth is 65536, and each table item is 19 bits, which is used to store neuron id and axon id. The first-level table depth of the output event projection table is 2048, and each table item is 17 bits, which is used for address information and number information; the second-level table item depth is 8196, and each table item is 32 bits, which is used for pulse routing information.

[0024] Neuronal core NC Figure 1As shown in (d), it has a 7-stage pipeline execution unit, including seven stages: instruction fetch, decoding, address calculation, memory read, memory read back, execution, and write back. The data memory is 32768 deep and 16 bits wide, which is used to store model information such as weights, variables, and sparse coding. The instruction memory is 1024 deep and 16 bits wide, which is used to store the machine code of the neuron model, synaptic model, and on-chip learning algorithm.

[0025] To achieve accurate calculation of the model, the processor of the present invention has three different working stages: initialization configuration stage, integral distribution stage and membrane potential update stage, and information is transmitted through data packets. The format of the data packet is as follows: Figure 4 As shown in (a), the type field is used to indicate the type of data packet, including "configuration", "unicast", "multicast" and "probe". The phase field is the data packet propagation state identifier, the tag and index fields are used to index the input event projection table, the destination ID field is the ID of the destination cortical column core, and the data payload field is the data carried by the data packet.

[0026] When the processor is in the initialization configuration stage, the neuron core NC is in sleep state, and the scheduling core SC parses the data packet transmitted to the local by the router R. At this time, the type field of the data packet is "configuration", and the data carried by the data packet is written into the event projection table or the memory of the neuron core NC to complete the loading of the model.

[0027] When the processor is in the points issuance stage, the scheduling core SC is in full-duplex state: on the one hand, it reads the information of the neuron core NC, converts the activated neurons into data packets through the output event projection table and sends them to the corresponding cortical column core CC and neuron core NC; on the other hand, it receives data packets from the router R. At this time, the type field of the data packet is "unicast" or "multicast", and determines whether the data packet is received and sent to the neuron core NC inside the cortical column core CC. Figure 4(b) in the figure shows the process of the scheduling core SC parsing pulse events. The scheduling core SC will first read the index item of the first-level table of the input event projection table according to the index field of the data packet, and determine whether the tag of the item is consistent with the tag of the data packet. If they are consistent, it means that the data packet can be received, and according to the addr and num of the content of the table item, read the num items of the second-level table starting from the addr item, and send the read axon id (axonid) and neuron id (neuronid) to the neuron core, and determine the specific neuron core NC to send it according to the upper three bits of the neuron id. If the tags are inconsistent, the data packet will be discarded, and the scheduling core SC will process the next data packet until all data packets are processed. After the neuron core NC receives the axon id and neuron id, it activates the core and starts to execute the model calculation. When the calculation is completed, the neuron core NC will be in a low-power state of listening to pulse events again until the next pulse event arrives.

[0028] When the current round of integral issuance phase is completed, the processor will switch to the membrane potential update phase, and the scheduling core SC will be in a dormant state. The neuron core NC will be in an activated state and automatically execute the program of the membrane potential update phase, complete the membrane potential update process / weight update process, and store the neuron information of the pulse. Then the neuron core NC will be in a dormant state, waiting for the next integral issuance phase. At this stage, the scheduling core SC may receive a data packet of type "probe". At this time, the scheduling core SC parses the data packet and reads the corresponding memory data, and sends the read-back data to the host in the form of a data packet. After the processor is initialized, the entire processor will continuously switch between the integral issuance phase and the membrane potential update phase until the model runs to the end.

[0029] The state transition diagram of the scheduling core SC processing input data packets is as follows Figure 5 shown.

[0030] In the neuron core NC of this embodiment, a variety of neuron models, synaptic models and on-chip learning algorithms are implemented in the form of instructions. Five acceleration instructions are designed for brain-like computing: membrane potential update instruction, sparse weight lookup instruction, synaptic current accumulation instruction, event reception instruction, and pulse issuance instruction.

[0031] The membrane potential update instruction is used to accelerate the form The equation of The data storage at the heart of the neuron, , Located in registers. A single instruction is used to access memory variables. Read and directly participate in the calculation. This instruction can be described as diff rd, rs1,rs2,rd are variables Register, register rs1 is the variable At the address of the data memory, rs2 is the variable registers.

[0032] The sparse weight search instruction is used to speed up the search for the location of non-zero weights represented by the bitmap. The instruction can be described as one rd, rs1, rs2, register rd is used to temporarily store the calculated sparse weight address, register rs1 contains the base address of the sparse code, and register rs2 is the id of the weight to be found. The range of the weight id to be found is 0~255, and the length of the sparse code table is 256. This instruction uses an addition tree to complete the calculation of a sparse code table of length 16 in a single cycle, and finally calculates the offset address of the weight id to be found in the non-zero weight block through N iterations, where N is the quotient of the weight id divided by 16 plus 1. The algorithm calculation process can be expressed as:

[0033]

[0034] The “>>” in the calculation process is the shift symbol and “%” is the remainder symbol.

[0035] The synaptic current accumulation instruction is used to accumulate the current corresponding to the event. This instruction can be described as locacc rs1, rs2, register rs1 is the accumulated current At the address of the data memory, rs2 is the current This instruction completes The operation of memory data is completed through one instruction Reading, The operation of modifying and writing data back to the memory.

[0036] The event receiving instruction is used to implement the core event-driven working mechanism, which is described as recv. This instruction has no operands. The events that each neuron core NC needs to process are stored in the input event buffer. The recv instruction determines the working state of the core by monitoring whether there are no events in the buffer. When there are no events in the buffer, the recv instruction pauses the pipeline of the instruction unit, so that the neuron core NC is in a low-power dormant state. At the same time, the neuron core NC keeps monitoring the status of the buffer; when there is an event in the buffer, the recv instruction will release the pipeline, read the event information from the buffer and store the information in the register. After completing the calculation of an event, the neuron core NC will execute a recv instruction to process the next event.

[0037] The pulse issuing instruction is described as send rd1,rs1, microcode. Register rd1 is the address of the output event memory of the neuron core NC to be written, register rs1 is the specific content to be written, and microcode is the type of data to be written, including: floating point activation value (act), binary pulse (spike) and neuron type (type). This instruction can send the results calculated by the neuron core NC in the membrane potential update phase to the output event memory, so that the scheduling core SC can directly obtain the model results and convert them into data packets to send to the destination neuron core.

Claims

1. A multi-core brain-like processor based on an instruction set, characterized in that: It includes LVDS interface and data proxy unit in four directions, A 2-D mesh on-chip network consisting of n routers, each router is connected to a cortical column core, a cortical column core consists of a scheduling core and a neuron cluster, and a neuron cluster includes multiple neuron cores; The LDVS interface is directly connected to the interfaces of other brain-like processors for data transmission between processors; The data proxy unit is used for the conversion of data within the processor and data between processors; The router is a ten-port router, including five ports of east, south, west, north and local. Each port includes two input and output ports. The local port is used to transmit data packets between the cortical column core, and the four ports of east, south, west and north are used to transmit data packets with the connected routers. The data is sent to any data proxy unit of the processor through the LVDS interface in the form of data packets. The scheduling core includes a scheduler, an input event projection table, and an output event projection table, which are used to send and receive data packets, parse received data packets and distribute them to the internal neuron cores; at the same time, it obtains information from the neuron core, generates data packets and sends them to the corresponding cortical column cores; The neuron core includes a seven-stage pipeline neuron execution unit, instruction memory and data memory, and completes the neuron model and network calculation according to the data packets distributed by the scheduling core; The input event projection table is stored in the form of a two-level table. The first-level table stores the identifier tag, base address addr, and number num indicating whether the data packet is received; the second-level table stores the neuron id and axon id. If the data packet is received, the neuron id and axon id are obtained from the addr item of the second-level table, and num information is read downward; The output event projection table is stored in the form of a two-level table. The first-level table stores the base address addr and the number num; the second-level table stores the routing information of the data packet, where the base address addr is used to obtain the routing information starting from the address of the second-level table and read num information downward; The neuron core implements an event-driven computing method based on the instruction set. The execution unit of the neuron core will only perform calculations when it receives a data packet sent by the scheduling core. The instruction memory stores model instructions and programs, and the data memory stores model parameters and variables.

2. The many-core brain-like processor according to claim 1, characterized in that: The type of instruction is CISC structure, and five special acceleration instructions are designed for brain-like computing, including membrane potential update instruction, sparse weight search instruction, synaptic current accumulation instruction, event reception instruction, and send pulse instruction; among them, the membrane potential update instruction is used to accelerate the membrane potential expression based on partial differential equations; the sparse weight search instruction is used to accelerate the search for weights based on bitmap sparse representation; the synaptic current accumulation instruction is used to accelerate the model accumulation current operation; the event reception instruction is used to realize the core event-driven working mechanism; the pulse issuance instruction is used to set the model calculation results that need to be issued.

3. A method for operating a multi-core brain-like processor based on an instruction set according to any one of claims 1 to 2, characterized in that: The method includes three different working phases: initialization configuration phase, integral issuance phase and membrane potential update phase; information is transmitted through data packets; in the data packets, the type field is used to indicate the type of the data packet, including "configuration", "unicast", "multicast" and "probe", the phase field is the data packet propagation state identifier, the tag and index fields are used to index the input event projection table, the Destination ID field is the ID of the destination cortical column core, and the Data Payload field is the data carried by the data packet.

4. The method according to claim 3, characterized in that When the processor is in the initialization configuration stage, the neuron core is in a dormant state, and the scheduling core parses the data packet transmitted to the local by the router. At this time, the type field of the data packet is "configuration", and the data carried by the data packet is written into the event projection table or the memory of the neuron core to complete the loading of the model.

5. The method according to claim 4, characterized in that When the processor is in the point distribution stage, the scheduling core is in full-duplex state: on the one hand, it reads the information of the neuron core, converts the activated neurons into data packets through the output event projection table and sends them to the corresponding cortical column core and neuron core; on the other hand, it receives data packets from the router. At this time, the type field of the data packet is "unicast" or "multicast", and determines whether the data packet is received and sent to the neuron core inside the cortical column core. The scheduling core will first read the index item of the first-level table of the input event projection table according to the index field of the data packet, and determine whether the tag of the item is consistent with the tag of the data packet. If it is consistent, it means that the data packet can be received, and according to the addr and num of the content of the table item, read the num items of the second-level table starting from the addr item, and send the read axon id and neuron id to the neuron core. According to the high three bits of the neuron id, it determines whether it is sent to the specific neuron core. If the tags are inconsistent, the data packet will be discarded, and the scheduling core processes the next data packet until all data packets are processed. After the neuron core receives the axon id and neuron id, it activates the neuron core and starts to execute the model calculation. When the calculation is completed, the neuron core will be in a low-power state of listening to pulse events again until the next pulse event arrives.

6. The method according to claim 5, characterized in that When the current round of integral issuance phase is completed, the processor will switch to the membrane potential update phase. At this time, the scheduling core will be in a dormant state, and the neuron core will be in an activated state. It will start to automatically execute the program of the membrane potential update phase, complete the membrane potential update process, and store the neuron information of the pulse. Then the neuron core will be in a dormant state, waiting for the arrival of the next integral issuance phase. At this stage, the scheduling core will receive a data packet of type "probe". At this time, the scheduling core parses the data packet and reads the corresponding memory data, and sends the read-back data to the host in the form of a data packet. After initializing the processor, the entire processor will continuously switch between the integral issuance phase and the membrane potential update phase until the model runs to the end.

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