Cross-chip bonding structure and preparation method

Abstract

The invention provides a cross-chip bonding structure and a preparation method, the cross-chip bonding structure comprises a lead frame base island and a chip arranged on the lead frame base island, the chip is provided with at least one group of cross-chip bonding links, each cross-chip bonding link at least comprises a first-section bonding wire and a tail-section bonding wire, and the first-section bonding wire is connected with the tail-section bonding wire. The at least one substrate is arranged on the lead frame base island, one end of the first-section bonding wire is electrically connected with a chip, the other end of the first-section bonding wire is electrically connected with the substrate, one end of the tail-section bonding wire is electrically connected with the substrate, and the other end of the tail-section bonding wire is electrically connected with at least one external chip system; according to the invention, the length of the bonding wire can be shortened through the cross-chip bonding link, the wire punching risk is greatly reduced, the universality is high, the method can be suitable for packaging chips and wiring diagrams of various sizes, and the technical problems of poor applicability and high cost in the prior art are solved.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor integrated circuit packaging and testing, and in particular to a cross-chip bonding structure and a preparation method thereof. Background Art

[0002] Wire bonding is the most critical process in the packaging process, which is directly related to the packaging quality and signal transmission. As semiconductors develop towards high density and high integration, the bonding wires in the package are becoming more and more dense, and the spacing between the bonding wires is becoming smaller and smaller. When the bonding is completed and the plastic is sealed, the arc shape of the bonding wire will be deformed during the flow of the molten plastic sealing material, and the bonding wires will come into contact with each other, causing the circuit to fail.

[0003] In view of the risk of wire punching, industry insiders have reduced the length of bonding wires from the perspective of frame design. The specific method is: in the frame design stage, by increasing the length of the pins, the pins are as close as possible to the lead frame base island of the mounted chip. When wiring the bonding wires, the length of the bonding wires can be effectively reduced, reducing the risk of wire punching. However, this method has many limitations and cannot be widely promoted. The specific reasons are as follows:

[0004] This method only uses small-sized chip packaging. For large-sized chips, the lead frame base island size needs to be increased during the frame design stage. However, increasing the lead frame base island size will lead to a reduction in pin design space, making it difficult to reduce the length of the bonding wire.

[0005] At the same time, this method has poor versatility. Using this method usually requires frame customization, and customized frames are only applicable to chips and wiring diagrams of specific sizes. When the chip size or wiring diagram changes significantly, it is often necessary to reopen the mold. The reopening of the mold has a long design cycle and high cost, making it difficult to promote widely. Summary of the invention

[0006] In order to solve the problems existing in the prior art, the present invention provides a cross-chip bonding structure and a preparation method thereof, so as to solve the technical problems of poor applicability and high cost existing in the prior related technology.

[0007] To achieve the above object, the present invention provides the following technical solutions:

[0008] A cross-chip bonding structure includes a lead frame base island and a chip arranged on the lead frame base island, wherein at least one group of cross-chip bonding links are arranged on the chip, and the cross-chip bonding links include at least a first-segment bonding wire and a last-segment bonding wire, and at least one substrate arranged on the lead frame base island, wherein one end of the first-segment bonding wire is electrically connected to the chip and the other end is electrically connected to the substrate, and one end of the last-segment bonding wire is electrically connected to the substrate and the other end is electrically connected to at least one external chip system.

[0009] Furthermore, the cross-chip bonding link includes a series link, a parallel link and a series-parallel link.

[0010] Furthermore, the cross-chip bonding link is a series link, and the cross-chip bonding link includes a first section bonding wire, a middle section bonding wire and a last section bonding wire, and adjacent substrates are electrically connected in series via the middle section bonding wire.

[0011] Furthermore, the cross-chip bonding link is a parallel link, and the cross-chip bonding link includes a first-segment bonding wire, a middle-segment bonding wire, and a last-segment bonding wire, and at least two substrates are electrically connected in parallel through the middle-segment bonding wire.

[0012] Furthermore, the cross-chip bonding link is a series-parallel link, and the cross-chip bonding link includes a first-section bonding wire, a middle-section bonding wire and a last-section bonding wire. At least two adjacent substrates are electrically connected in series through the middle-section bonding wire, and at least two substrates are electrically connected in parallel through the middle-section bonding wire.

[0013] Furthermore, at least one pair of gold fingers is disposed on the substrate.

[0014] Furthermore, the substrate includes a first solder resist layer, a copper layer and a second solder resist layer which are stacked in sequence.

[0015] Furthermore, the substrate is bonded to the lead frame base island.

[0016] Furthermore, the lead frame base island, chip, substrate and cross-chip bonding links are all wrapped in the same plastic packaging material.

[0017] A method for preparing a cross-chip bonding structure comprises the following steps:

[0018] Use a die bonding machine to bond the chip and substrate to the lead frame base island, and perform conductive adhesive curing after bonding;

[0019] A pressure welder is used to connect the chip, substrate and external chip system through bonding wires;

[0020] The connected cross-chip bonding structure is cleaned and plastic-sealed.

[0021] Compared with the prior art, the present invention has the following beneficial technical effects:

[0022] The present invention provides a cross-chip bonding structure, comprising a lead frame base island, and a chip arranged on the lead frame base island, wherein at least one group of cross-chip bonding links are arranged on the chip, and the cross-chip bonding links at least include a first-segment bonding wire and a last-segment bonding wire, and at least one substrate arranged on the lead frame base island, wherein one end of the first-segment bonding wire is electrically connected to the chip, and the other end is electrically connected to the substrate, and one end of the last-segment bonding wire is electrically connected to the substrate, and the other end is electrically connected to at least one external chip system; the present application can shorten the length of the bonding wire through the cross-chip bonding link, thereby greatly reducing the risk of wire punching, and has strong versatility, and can be applicable to the packaging of chips of various sizes and wiring diagrams, thereby solving the technical problems of poor applicability and high cost in the existing related technologies.

[0023] The present invention provides a method for preparing a cross-chip bonding structure, comprising the following steps: using a die bonding machine to bond a chip and a substrate to a lead frame base island, and curing a conductive adhesive after bonding; using a pressure welding machine to connect the chip, the substrate and an external chip system through bonding wires; cleaning and plastic-sealing the connected cross-chip bonding structure; the present application can transfer signals received or output by the chip through the substrate, thereby ensuring the stability of signal transmission, meeting all functions of cross-chip bonding, and greatly reducing the risk of wire punching. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 A schematic diagram of a cross-chip bonding structure according to an embodiment of the present disclosure is shown;

[0025] Figure 2 A schematic diagram showing the structure of the gold finger on the substrate of an embodiment of the present disclosure is shown;

[0026] Figure 3 A schematic diagram of a serial link according to an embodiment of the present disclosure is shown;

[0027] Figure 4 A schematic diagram of a parallel link according to an embodiment of the present disclosure is shown;

[0028] Figure 5 A schematic diagram of a series-parallel link according to an embodiment of the present disclosure is shown;

[0029] Figure 6 A schematic diagram of the substrate structure of an embodiment of the present disclosure is shown.

[0030] In the attached figure:

[0031] 1. Lead frame base island; 2. Chip; 3. Substrate; 4. Cross-chip bonding link; 40. First section bonding wire; 41. Middle section bonding wire; 42. Last section bonding wire; 30. Gold finger; 31. Solder mask layer; 32. Copper layer; 33. Second solder mask layer. DETAILED DESCRIPTION

[0032] In the following, only some exemplary embodiments are briefly described. As those skilled in the art will appreciate, the described embodiments may be modified in various ways without departing from the spirit or scope of the present invention. Therefore, the drawings and descriptions are considered to be exemplary and non-restrictive in nature.

[0033] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0034] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0035] In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or a communication; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0036] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being "above", "above" and "above" a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below", "below" and "below" a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0037] It should be understood that when used in this specification and the appended claims, the terms "include" and "comprises" indicate the presence of described features, integers, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or combinations thereof.

[0038] It should also be understood that the terms used in the present specification are only for the purpose of describing specific embodiments and are not intended to limit the present invention. As used in the present specification and the appended claims, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include plural forms.

[0039] It should be further understood that the term "and / or" used in the present description and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0040] Various structural schematic diagrams of the embodiments disclosed in the present invention are shown in the accompanying drawings. These figures are not drawn to scale, and some details are magnified and some details may be omitted for the purpose of clear expression. The shapes of various regions and layers shown in the figures and the relative sizes and positional relationships therebetween are only exemplary, and may deviate in practice due to manufacturing tolerances or technical limitations, and those skilled in the art may additionally design regions / layers with different shapes, sizes, and relative positions according to actual needs.

[0041] The embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0042] Figure 1 A cross-chip bonding structure of an embodiment of the present disclosure is shown. Figure 1 As shown, it includes a lead frame base island 1, and a chip 2 arranged on the lead frame base island 1, and at least one group of cross-chip bonding links 4 are arranged on the chip 2, and the cross-chip bonding links 4 at least include a first-section bonding wire 40 and a last-section bonding wire 42, and at least one substrate 3 arranged on the lead frame base island 1, one end of the first-section bonding wire 40 is electrically connected to the chip 2, and the other end is electrically connected to the substrate 3, and one end of the last-section bonding wire 42 is electrically connected to the substrate 3, and the other end is electrically connected to at least one external chip system.

[0043] It should be noted that in the embodiment of the present disclosure, for the convenience of explanation, the cross-chip bonding link 4 and the substrate 3 are both one, and the first section of the bonding wire 40, the substrate 3 and the last section of the bonding wire 42 constitute a simple series link; at the same time, in the embodiment of the present disclosure, the external chip system is connected through the pins formed on the lead frame, that is, the cross-chip bonding link 4 can realize the electrical signal connection to the external chip system by connecting the pins.

[0044] Preferably, in the embodiments of the present disclosure, the cross-chip bonding link 4 includes a serial link, a parallel link and a serial-parallel link. In some embodiments, the cross-chip bonding structure may include a cross-chip bonding link 4 of a serial link, a parallel link and / or a serial-parallel link to meet different cross-connection requirements.

[0045] In some embodiments, Figure 3 As shown, the inter-chip bonding link 4 is a series link, and the inter-chip bonding link 4 includes a first-segment bonding wire 40 , a middle-segment bonding wire 41 and a last-segment bonding wire 42 . Adjacent substrates 3 are electrically connected in series via the middle-segment bonding wire 41 .

[0046] In other embodiments, Figure 4 As shown, the cross-chip bonding link 4 is a parallel link, and the cross-chip bonding link 4 includes a first-segment bonding wire 40 , a middle-segment bonding wire 41 and a last-segment bonding wire 42 , and at least two substrates 3 are electrically connected in parallel through the middle-segment bonding wire 41 .

[0047] In other embodiments, Figure 5 As shown, the cross-chip bonding link 4 is a series-parallel link, and the cross-chip bonding link 4 includes a first-section bonding wire 40, a middle-section bonding wire 41 and a last-section bonding wire 42. At least two adjacent substrates 3 are electrically connected in series through the middle-section bonding wire 41, and at least two substrates 3 are electrically connected in parallel through the middle-section bonding wire 41.

[0048] Specifically, the lengths of the first bonding wire 40, the middle bonding wire 41 and the last bonding wire 42 are all less than 2 mm, and the first bonding wire 40, the middle bonding wire 41 and the last bonding wire 42 are all curved metal wires with a certain curvature; at the same time, the arrangement of the cross-chip bonding link 4 should follow the principle of non-interference and the fewer bonding wires used, the better, so as to reduce the complexity and reliability of the structure.

[0049] Preferably, in the embodiment of the present disclosure, at least one pair of gold fingers 30 is disposed on the substrate 3. In some other embodiments, Figure 2As shown, two pairs of gold fingers 30 are arranged on the substrate 3. In some cases, the two pairs of gold fingers 30 are interconnected, and the two pairs of interconnected gold fingers 30 can reduce the length of the bonding wire. In other cases, the two pairs of gold fingers 30 are respectively used to connect the bonding wires of different links to form a parallel link structure. It should be noted that the above two cases can be used in combination, and the number of gold fingers 30 can also be more to meet more complex connection requirements.

[0050] It should be further explained that, the substrate 3 described in this embodiment only forms a circuit for circuit conduction, and the substrate itself does not participate in the signal processing process.

[0051] Preferably, in the embodiments of the present disclosure, Figure 6 As shown, the substrate 3 is bonded to the lead frame base island 1; the substrate 3 includes a first solder resist layer 31, a copper layer 32 and a second solder resist layer 33 which are stacked in sequence; it should be noted that the first solder resist layer 31 can enhance the bonding force between the plastic encapsulation material and the surface of the substrate 3 and reduce the risk of delamination; the second solder resist layer 33 of the substrate 3 has no window area, which can prevent the circuit of the substrate 3 and the lead frame base island 1 from being conductive.

[0052] When designing the size of the substrate 3, the following points should be considered:

[0053] 1. The size of the substrate 3 should not be too large. After the chip 2 is mounted on the lead frame island 1, the area on the lead frame island 1 where the device can be mounted is small. When a larger substrate 3 is mounted on the lead frame island 1, the substrate 3 will be suspended and the adhesion will be poor.

[0054] Second, when designing the gold finger 30 of the substrate 3, the diameter of the bonding wire, the downward pressure of the splitter during bonding, and the anti-arc space should be fully considered to avoid the splitter collapsing the arc of the first bonding wire during the second bonding.

[0055] Therefore, in some embodiments, the total thickness of the substrate 3 does not exceed 70 μm, which greatly reduces the thickness of the substrate and meets the requirements of thin and light devices; specifically, the size of a typical complete substrate is 76.3×240 mm, and multiple units can be distributed in an array on a complete substrate. After the size of a single substrate 3 is designed, the single substrate 3 can be distributed in an array on a whole substrate with a size of 76.3×240 mm, with a 0.3 mm cutting path left between the single substrates 3, and the substrate can be cut into single products using a Tape Saw.

[0056] In some embodiments, the substrate 3 is provided with a mark for distinguishing the mounting direction, so as to facilitate technicians in this field to mount the substrate 3 .

[0057] In some embodiments, the lead frame island 1 , the chip 2 , the substrate 3 and the cross-chip bonding link 4 are all wrapped in the same plastic packaging material.

[0058] This embodiment also discloses a method for preparing a cross-chip bonding structure, comprising the following steps:

[0059] Use a die bonding machine to bond the chip 2 and the substrate 3 to the lead frame base island 1, and after bonding, perform a conductive adhesive curing process;

[0060] A pressure welding machine is used to connect the chip 2, the substrate 3 and the external chip system through bonding wires;

[0061] The connected cross-chip bonding structure is cleaned and plastic-sealed.

[0062] Embodiment 1:

[0063] This embodiment will complete the bonding of 5×5mm QFN36L, the size of chip 2 is 3×3mm, and the specific steps are as follows:

[0064] Step 1: Use a thinning machine to thin the 12-inch wafer with a chip size of 3×3mm to 200μm;

[0065] Step 2: Use a dicing machine to divide the thinned wafer into 3×3 mm chips 2;

[0066] Step 3: designing a substrate 3; arranging substrate units of size 0.3×0.6 mm in an array on a complete substrate of 76.3×240 mm, with only one pair of gold fingers 30 on the substrate unit;

[0067] Step 4: After the substrate unit is manufactured, use a Tape Saw to cut it, split the entire substrate into individual substrates 3, and put them into a waffle box;

[0068] Step 5: Use a die bonding machine to sequentially bond the chip and the single substrate to the lead frame base island 1, and then put them into an oven to cure the conductive adhesive;

[0069] Step 6: Use a sheet plasma machine to clean the frame, then install a 25μm diameter gold wire spool on the pressure welding machine, first connect the chip 2 and a gold finger 30 on the substrate 3, and then connect the other gold finger 30 to the pin of the external chip system. The first section of the bonding wire is about 2.0mm and the last section of the bonding wire is about 1.7mm.

[0070] Step 7: Use a sheet plasma machine to clean the frame and then plastic seal it.

[0071] Embodiment 2:

[0072] This example will complete the bonding of a 6×6mm QFN48L chip with a size of 4.15×3.28mm. The specific steps are as follows:

[0073] Step 1: Use a thinning machine to thin a 12-inch wafer with a chip size of 4.15×3.28 mm to 150 μm.

[0074] Step 2: Use a dicing machine to divide the thinned wafer into chips 2 of 4.15×3.28 mm.

[0075] Step 3: designing a substrate 3; arranging substrate units with a size of 0.7×0.6 mm in an array on a complete substrate of 76.3×240 mm, with two pairs of gold fingers 30 on the substrate units, which can reduce the length of two bonding wires.

[0076] Step 4: After the substrate unit is manufactured, use a Tape Saw to cut it, divide the entire substrate into individual substrates 3, and put them into a tray or a waffle box.

[0077] Step 5: Use a die bonding machine to sequentially bond the chip 2 and the single substrate 3 to the lead frame base island 1, and then place them in an oven to cure the conductive adhesive.

[0078] Step 6: Use a sheet plasma machine to clean the frame, then install a 20μm diameter gold wire spool on the pressure welding machine, first connect one solder joint of the first pair of gold fingers 30 on the chip 2 and the substrate 3, and then connect the other solder joint of the first pair of gold fingers 30 to the pin of the external chip system. The first section of the bonding wire is about 1.97mm, and the last section of the bonding wire is about 1.57mm.

[0079] Step 7: Connect the chip 2 and one soldering point of the second pair of gold fingers 30 on the substrate 3, and then connect the other soldering point of the second pair of gold fingers to the pin of the external chip system. The first section of the bonding wire is about 2.13mm and the last section of the bonding wire is about 1.95mm.

[0080] Step 8: Use a sheet plasma machine to clean the frame and then plastic seal it.

[0081] The above shows and describes the basic principles and main features of the present invention and the advantages of the present invention. It is obvious to those skilled in the art that the present invention is not limited to the details of the above exemplary embodiments, and the present invention can be implemented in other specific forms without departing from the spirit or basic features of the present invention. Therefore, no matter from which point of view, the embodiments should be regarded as exemplary and non-restrictive. The scope of the present invention is defined by the attached claims rather than the above description, and it is intended that all changes falling within the meaning and scope of the equivalent elements of the claims are included in the present invention. Any figure mark in the claims should not be regarded as limiting the claims involved.

[0082] In addition, it should be understood that although this specification is described in accordance with the implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other implementation modes that can be understood by those skilled in the art. The above content is only to illustrate the technical idea of ​​the present invention, and cannot be used to limit the protection scope of the present invention. Any changes made on the basis of the technical solution according to the technical idea proposed by the present invention shall fall within the protection scope of the claims of the present invention.

Claims

1. A cross-chip bonding structure, It is characterized in that The invention comprises a lead frame base island (1), and a chip (2) arranged on the lead frame base island (1), wherein at least one group of cross-chip bonding links (4) are arranged on the chip (2), and the cross-chip bonding links (4) at least comprise a first-segment bonding wire (40) and a last-segment bonding wire (42), and at least one substrate (3) arranged on the lead frame base island (1), wherein one end of the first-segment bonding wire (40) is electrically connected to the chip (2) and the other end is electrically connected to the substrate (3), and one end of the last-segment bonding wire (42) is electrically connected to the substrate (3) and the other end is electrically connected to at least one external chip system.

2. The cross-chip bonding structure according to claim 1, It is characterized in that The cross-chip bonding link (4) includes a series link, a parallel link and a series-parallel link.

3. The cross-chip bonding structure according to claim 2, It is characterized in that The cross-chip bonding link (4) is a series link, and the cross-chip bonding link (4) comprises a first section bonding wire (40), a middle section bonding wire (41) and a last section bonding wire (42), and adjacent substrates (3) are electrically connected in series via the middle section bonding wire (41).

4. The cross-chip bonding structure according to claim 2, It is characterized in that The cross-chip bonding link (4) is a parallel link, and the cross-chip bonding link (4) comprises a first-segment bonding wire (40), a middle-segment bonding wire (41), and a last-segment bonding wire (42), and at least two substrates (3) are electrically connected in parallel via the middle-segment bonding wire (41).

5. The cross-chip bonding structure according to claim 2, It is characterized in that The cross-chip bonding link (4) is a series-parallel link, and the cross-chip bonding link (4) comprises a first section bonding wire (40), a middle section bonding wire (41) and a last section bonding wire (42), at least two adjacent substrates (3) are electrically connected in series via the middle section bonding wire (41), and at least two substrates (3) are electrically connected in parallel via the middle section bonding wire (41).

6. The cross-chip bonding structure according to claim 1, It is characterized in that At least one pair of gold fingers (30) is arranged on the substrate (3).

7. The cross-chip bonding structure according to claim 1, It is characterized in that The substrate (3) comprises a first solder resist layer (31), a copper layer (32) and a second solder resist layer (33) which are sequentially stacked.

8. The cross-chip bonding structure according to claim 1, It is characterized in that The substrate (3) is bonded to the lead frame base island (1).

9. The cross-chip bonding structure according to claim 1, It is characterized in that The lead frame base island (1), chip (2), substrate (3) and cross-chip bonding link (4) are all wrapped in the same plastic packaging material.

10. A method for preparing a cross-chip bonding structure, It is characterized in that The cross-chip bonding structure according to any one of claims 1 to 9 comprises the following steps: Using a die bonding machine to bond the chip (2) and the substrate (3) to the lead frame base island (1), and after bonding, performing a conductive adhesive curing process; A pressure welding machine is used to connect the chip (2), the substrate (3) and the external chip system via bonding wires; The connected cross-chip bonding structure is cleaned and plastic-sealed.

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