Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof. The structure comprises a substrate; the storage gate structure is located on part of the surface of the substrate, the storage gate structure comprises a tunneling oxide layer, a charge trapping layer located on the tunneling oxide layer, a barrier layer located on the charge trapping layer and a gate layer located on the surface of the barrier layer, and the dielectric constant of the barrier layer is larger than that of the charge trapping layer; and the source doped region and the drain doped region are respectively positioned in the substrate at the two sides of the storage gate structure, so that the diffusion of electrons in the gate layer into the charge trapping layer is reduced, the back gate electron injection effect is favorably inhibited, and the performance of the storage device is favorably improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a forming method thereof. Background Art

[0002] As an essential storage device in computers, non-volatile memory plays an important role in storing the information being processed. Among them, SONOS (Silicon-Oxide-Nitride-Oxide-Silicon) memory based on silicon nitride storage medium with excellent insulation performance has attracted attention for its stronger charge storage capacity compared to traditional polysilicon floating gate memory, easy miniaturization and simple process.

[0003] SONOS devices replace the original polysilicon charge storage layer with a silicon nitride layer with charge trapping capability. Since it uses trapped charges to store charges, the stored charges are discretely distributed. Such a leakage channel will not cause a large leakage current, so the reliability is greatly improved.

[0004] However, the performance of SONOS devices formed by the prior art needs to be further improved. Summary of the invention

[0005] The technical problem solved by the present invention is to provide a semiconductor structure and a method for forming the same, so as to improve the performance of the formed semiconductor structure.

[0006] In order to solve the above technical problems, the technical solution of the present invention provides a semiconductor structure, including: a substrate; a storage gate structure located on a portion of the surface of the substrate, the storage gate structure including a tunneling oxide layer, a charge trapping layer located on the tunneling oxide layer, a blocking layer located on the charge trapping layer, and a gate layer located on the surface of the blocking layer, the dielectric constant of the blocking layer is greater than the dielectric constant of the charge trapping layer; a source doping region and a drain doping region in the substrate respectively located on both sides of the storage gate structure.

[0007] Optionally, the dielectric constant of the barrier layer is greater than 3.9.

[0008] Optionally, the material of the barrier layer includes one or more of HfAlO, HfSiO, and HfO2.

[0009] Optionally, the substrate includes an epitaxial layer; the source doping region and the drain doping region are located in the epitaxial layer; and the material of the epitaxial layer includes silicon carbide.

[0010] Optionally, the epitaxial layer has a well region; the source doped region and the drain doped region are located in the well region, the well region has a first conductivity type, the source doped region and the drain doped region have a second conductivity type, and the first conductivity type is different from the second conductivity type.

[0011] Optionally, the substrate further includes a base, and the epitaxial layer is located on a surface of the base; the material of the base includes silicon carbide.

[0012] Optionally, the material of the gate layer is metal; the metal includes one or more of TiN, Ti, Al, W, Ag, Au, Cu, Ni and TaN.

[0013] Optionally, the material of the tunneling oxide layer includes silicon oxide; and the material of the charge trapping layer includes silicon nitride.

[0014] Correspondingly, the technical solution of the present invention also provides a method for forming a semiconductor structure, comprising: providing a substrate; forming a storage gate structure on a portion of the substrate, the storage gate structure comprising a tunneling oxide layer, a charge trapping layer located on the tunneling oxide layer, a blocking layer located on the charge trapping layer, and a gate layer located on the surface of the blocking layer, the dielectric constant of the blocking layer being greater than the dielectric constant of the charge trapping layer; and forming a source doping region and a drain doping region in the substrate on both sides of the storage gate structure, respectively.

[0015] Optionally, the method for forming the storage gate structure includes: forming a storage gate material layer on the surface of the substrate, the storage gate material layer including a tunneling oxide material layer, a charge trapping material layer located on the surface of the tunneling oxide material layer, a blocking material layer located on the surface of the charge trapping material layer, and a gate material layer located on the surface of the blocking material layer; etching the storage gate material layer to form the storage gate structure, forming the tunneling oxide layer with the tunneling oxide material layer, forming the charge trapping layer with the charge trapping material layer, forming the blocking layer with the blocking material layer, and forming the gate layer with the gate material layer.

[0016] Optionally, the process for forming the tunneling oxide material layer includes a thermal oxidation process; and the material of the tunneling oxide layer includes silicon oxide.

[0017] Optionally, after forming the source doping region and the drain doping region, the storage gate structure is formed; the method for forming the source doping region and the drain doping region includes: injecting doping ions into part of the substrate to form the source doping region and the drain doping region that are separate from each other in the substrate.

[0018] Optionally, the substrate includes an epitaxial layer; the source doping region and the drain doping region are located in the epitaxial layer; and the material of the epitaxial layer includes silicon carbide.

[0019] Optionally, the epitaxial layer has a well region; the source doped region and the drain doped region are located in the well region, the well region has a first conductivity type, the source doped region and the drain doped region have a second conductivity type, and the first conductivity type is different from the second conductivity type; the method also includes: forming the well region before forming the source doped region and the drain doped region.

[0020] Optionally, the substrate further includes a base, and the epitaxial layer is located on a surface of the base; the material of the base includes silicon carbide.

[0021] Optionally, the dielectric constant of the barrier layer is greater than 3.9.

[0022] Optionally, the material of the barrier layer includes one or more of HfAlO, HfSiO, and HfO2.

[0023] Optionally, the material of the gate layer is metal; the metal includes one or more of TiN, Ti, Al, W, Ag, Au, Cu, Ni and TaN.

[0024] Optionally, the material of the tunneling oxide layer includes silicon oxide; and the material of the charge trapping layer includes silicon nitride.

[0025] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0026] In the method for forming a semiconductor structure provided by the technical solution of the present invention, the storage gate structure includes a tunneling oxide layer, a charge trapping layer located on the tunneling oxide layer, a blocking layer located on the charge trapping layer, and a gate layer located on the surface of the blocking layer. The dielectric constant of the blocking layer is greater than the dielectric constant of the charge trapping layer. The blocking layer has a higher dielectric constant, which reduces the diffusion of electrons in the gate layer into the charge trapping layer, thereby facilitating the suppression of the back gate electron injection effect and improving the performance of the storage device.

[0027] Furthermore, the material of the epitaxial layer includes silicon carbide. Compared with silicon material, silicon carbide material has higher thermal conductivity and lower on-resistance, which is more conducive to the heat dissipation and integration of the device and reduces the conduction loss of the device. In addition, since silicon carbide material has higher corrosion resistance and high temperature resistance, it is beneficial to improve the performance stability of the device when working in harsh environments.

[0028] In the semiconductor structure provided by the technical solution of the present invention, the storage gate structure includes a tunneling oxide layer, a charge trapping layer located on the tunneling oxide layer, a blocking layer located on the charge trapping layer, and a gate layer located on the surface of the blocking layer. The dielectric constant of the blocking layer is greater than the dielectric constant of the charge trapping layer. The blocking layer has a higher dielectric constant, which reduces the diffusion of electrons in the gate layer into the charge trapping layer, thereby facilitating the suppression of the back gate electron injection effect and improving the performance of the storage device. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 is a schematic diagram of a cross-sectional structure of a SONOS device;

[0030] Figure 2 is a schematic flow chart of a method for forming a semiconductor structure according to an embodiment of the present invention;

[0031] Figures 3 to 6 It is a structural schematic diagram of each step of the method for forming a semiconductor structure according to an embodiment of the present invention. DETAILED DESCRIPTION

[0032] It should be noted that the terms “surface” and “on” in this specification are used to describe relative positional relationships in space and are not limited to direct contact.

[0033] As described in the background art, the performance of the SONOS device formed by the prior art needs to be further improved. Now, a SONOS device is described and analyzed.

[0034] Figure 1 It is a schematic diagram of the cross-sectional structure of a SONOS device.

[0035] Please refer to Figure 1 The SONOS device includes: a substrate 100, a storage gate structure located on a surface of a portion of the substrate 100, the storage gate structure including a tunneling oxide layer 101, a charge trapping layer 102 located on the tunneling oxide layer 101, a control oxide layer 103 located on the charge trapping layer 102, and a gate layer 104 located on the control oxide layer 103, and source-drain doped regions 105 in the substrate 100 located on both sides of the storage gate structure.

[0036] In the above SONOS device, the material of the control oxide layer 104 is silicon oxide. As the device size shrinks, the thickness of the control oxide layer 104 also decreases accordingly, so that it is difficult to prevent the electrons in the gate layer 105 from diffusing into the silicon nitride storage layer 103, resulting in the back gate electron injection effect problem, which affects the performance of the SONOS device.

[0037] In order to solve the above problems, the present invention provides a semiconductor structure and a method for forming the same, wherein a storage gate structure includes a tunneling oxide layer, a charge trapping layer located on the tunneling oxide layer, a blocking layer located on the charge trapping layer, and a gate layer located on the surface of the blocking layer, wherein the dielectric constant of the blocking layer is greater than the dielectric constant of the charge trapping layer, and the blocking layer has a higher dielectric constant, which reduces the diffusion of electrons in the gate layer into the charge trapping layer, thereby facilitating the suppression of the back gate electron injection effect and improving the performance of the storage device.

[0038] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0039] Figure 2 It is a schematic flow chart of a method for forming a semiconductor structure according to an embodiment of the present invention.

[0040] Please refer to Figure 2 , the method for forming the semiconductor structure comprises the following steps:

[0041] Step S201, providing a substrate;

[0042] Step S202, forming a storage gate structure on a portion of the substrate, the storage gate structure comprising a tunneling oxide layer, a charge trapping layer on the tunneling oxide layer, a blocking layer on the charge trapping layer, and a gate layer on a surface of the blocking layer, wherein the dielectric constant of the blocking layer is greater than the dielectric constant of the charge trapping layer;

[0043] Step S203 , forming a source doping region and a drain doping region in the substrate at both sides of the storage gate structure respectively.

[0044] The following is a detailed description with reference to the accompanying drawings.

[0045] Figures 3 to 6 It is a structural schematic diagram of each step of the method for forming a semiconductor structure according to an embodiment of the present invention.

[0046] Please refer to Figure 3 , providing a substrate 300.

[0047] In this embodiment, the substrate 300 includes an epitaxial layer 300 b.

[0048] The material of the epitaxial layer 300b includes silicon carbide. In this embodiment, the material of the epitaxial layer 300b is silicon carbide.

[0049] Here, the reason for selecting silicon carbide as the material of the epitaxial layer 300b is that compared with silicon material, silicon carbide material has higher thermal conductivity and lower on-resistance, which is more conducive to the heat dissipation and integration of the device and reduces the conduction loss of the device; in addition, since silicon carbide material has higher corrosion resistance and high temperature resistance, it is beneficial to improve the performance stability of the device when working in harsh environments.

[0050] In this embodiment, the substrate 300b further includes a base 300a, and the epitaxial layer 300b is located on the surface of the base 300a.

[0051] The material of the substrate 300a includes silicon carbide. In this embodiment, the material of the substrate 300a is silicon carbide. That is, a silicon carbide epitaxial layer is formed on a silicon carbide wafer to form the epitaxial layer 300b. The epitaxial layer 300b is formed by a homoepitaxial process, which is conducive to improving the quality of the formed epitaxial layer 300b and reducing the defect density of the epitaxial layer 300b.

[0052] In this embodiment, the epitaxial layer 300 b has a well region (not shown in the figure), and the well region has a first conductivity type.

[0053] In this embodiment, the well region is formed before forming the source doping region and the drain doping region.

[0054] The first conductivity type includes P type or N type. In this embodiment, the first conductivity type is P type. In another embodiment, the first conductivity type is N type.

[0055] In this embodiment, the substrate 300 includes a first region i, a second region ii, and a third region iii located between the first region i and the second region ii. The first region i is used to define the position of a source doping region to be formed subsequently, the second region ii is used to define the position of a drain doping region to be formed subsequently, and the third region iii is used to define the position of a storage gate structure to be formed subsequently.

[0056] Subsequently, a storage gate structure is formed on part of the substrate, the storage gate structure comprising a tunneling oxide layer, a charge trapping layer on the tunneling oxide layer, a blocking layer on the charge trapping layer, and a gate layer on the surface of the blocking layer, wherein the dielectric constant of the blocking layer is greater than the dielectric constant of the charge trapping layer; and a source doping region and a drain doping region are respectively formed in the substrate on both sides of the storage gate structure.

[0057] In this embodiment, the storage gate structure is formed after the source doping region and the drain doping region are formed. In another embodiment, the source doping region and the drain doping region may be formed after the storage gate structure is formed.

[0058] In this embodiment, the method for forming the source doping region, the drain doping region and the storage gate structure can be found in Figures 4 to 6 .

[0059] Please refer to Figure 4 , doping ions are implanted into a portion of the substrate 300 to form the source doping region 302a and the drain doping region 302b that are separate from each other in the substrate 300.

[0060] Specifically, the method of injecting doping ions into a portion of the substrate 300 to form the source doping region 302a and the drain doping region 302b separated from each other in the substrate 300 includes: forming a photoresist material layer (not shown in the figure) on the surface of the substrate 300; patterning the photoresist material layer to form a photoresist layer 301, wherein the photoresist layer 301 is located on the third region iii and exposes the first region i and the second region ii; and using the photoresist layer 301 as a mask, injecting doping ions into the substrate 300.

[0061] In this embodiment, the source doping region 302 a and the drain doping region 302 b are located in the epitaxial layer 300 b .

[0062] Specifically, the source doping region 302a and the drain doping region 302b are located in the well region, the source doping region 302a and the drain doping region 302b have a second conductivity type, and the first conductivity type is different from the second conductivity type.

[0063] In this embodiment, the second conductivity type is N type. In another embodiment, the second conductivity type is P type.

[0064] Please refer to Figure 5 A storage gate material layer is formed on the surface of the substrate 300, and the storage gate material layer includes a tunneling oxide material layer 303, a charge trapping material layer 304 located on the surface of the tunneling oxide material layer 303, a blocking material layer 305 located on the surface of the charge trapping material layer 304, and a gate material layer 306 located on the surface of the blocking material layer 305.

[0065] In this embodiment, the dielectric constant of the barrier material layer 305 is greater than 3.9. The barrier material layer 305 is used to form a barrier layer.

[0066] The material of the barrier material layer 305 includes one or more of HfAlO, HfSiO, and HfO 2. In this embodiment, the material of the barrier material layer 305 is HfAlO.

[0067] The gate material layer 306 is made of metal, which includes one or more of TiN, Ti, Al, W, Ag, Au, Cu, Ni and TaN. In this embodiment, the gate material layer 306 is made of Al.

[0068] In this embodiment, the formation process of the tunneling oxide material layer 303 includes a thermal oxidation process.

[0069] In this embodiment, the material of the tunneling oxide material layer 303 includes silicon oxide.

[0070] In this embodiment, the charge trapping material layer 304 is made of silicon nitride.

[0071] In this embodiment, after forming the source doping region 302 a and the drain doping region 302 b and before forming the tunneling oxide material layer 303 , the photoresist layer 301 is further removed.

[0072] Please refer to Figure 6 , the storage gate material layer is etched to form the storage gate structure, the tunneling oxide layer 307 is formed by the tunneling oxide material layer 303, the charge trapping layer 308 is formed by the charge trapping material layer 304, the blocking layer 309 is formed by the blocking material layer 305, and the gate material layer 306 is formed to form the gate layer 310.

[0073] At this point, the dielectric constant of the blocking layer 309 is greater than the dielectric constant of the charge trapping layer 304. The blocking layer 309 has a higher dielectric constant, which reduces the diffusion of electrons in the gate layer 310 into the charge trapping layer 304, thereby helping to suppress the back gate electron injection effect and improve the performance of the storage device.

[0074] In this embodiment, the material of the tunnel oxide layer 307 includes silicon oxide.

[0075] In this embodiment, the material of the charge trapping layer 304 includes silicon nitride.

[0076] In this embodiment, the dielectric constant of the barrier layer 309 is greater than 3.9.

[0077] The material of the barrier layer 309 includes one or more of HfAlO, HfSiO, and HfO 2. In this embodiment, the material of the barrier layer 309 is HfAlO.

[0078] The gate layer 310 is made of metal, which includes one or more of TiN, Ti, Al, W, Ag, Au, Cu, Ni and TaN. In this embodiment, the gate layer 310 is made of Al.

[0079] Accordingly, the embodiment of the present invention further provides a semiconductor structure formed by the above method, please continue to refer to Figure 6 , including: a substrate 300; a storage gate structure located on a portion of the surface of the substrate 300, the storage gate structure including a tunneling oxide layer 307, a charge trapping layer 308 located on the tunneling oxide layer 307, a blocking layer 309 located on the charge trapping layer 308, and a gate layer 310 located on the surface of the blocking layer 309, the dielectric constant of the blocking layer 309 is greater than the dielectric constant of the charge trapping layer 308; a source doped region 302a and a drain doped region 302b in the substrate 300 respectively located on both sides of the storage gate structure.

[0080] At this point, the dielectric constant of the blocking layer 309 is greater than the dielectric constant of the charge trapping layer 304. The blocking layer 309 has a higher dielectric constant, which reduces the diffusion of electrons in the gate layer 310 into the charge trapping layer 304, thereby helping to suppress the back gate electron injection effect and improve the performance of the storage device.

[0081] In this embodiment, the dielectric constant of the barrier layer 309 is greater than 3.9.

[0082] The material of the barrier layer 309 includes one or more of HfAlO, HfSiO, and HfO 2. In this embodiment, the material of the barrier layer 309 is HfAlO.

[0083] In this embodiment, the substrate 300 includes an epitaxial layer 300 b ; the source doping region 302 a and the drain doping region 302 b are located in the epitaxial layer 300 b ; and the material of the epitaxial layer 300 b includes silicon carbide.

[0084] In this embodiment, the epitaxial layer 300b has a well region (not shown in the figure); the source doping region 302a and the drain doping region 302b are located in the well region, the source doping region 302a and the drain doping region 302b have a first conductivity type, and the well region has a second conductivity type, and the first conductivity type is different from the second conductivity type.

[0085] In this embodiment, the substrate 300 further includes a base 300a, and the epitaxial layer 300b is located on the surface of the base 300a; the material of the base 300a includes silicon carbide.

[0086] In this embodiment, the material of the gate layer 310 is metal; the metal includes one or more of TiN, Ti, Al, W, Ag, Au, Cu, Ni and TaN.

[0087] In this embodiment, the material of the tunneling oxide layer 307 includes silicon oxide; the material of the charge trapping layer 308 includes silicon nitride.

[0088] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, It is characterized in that include: substrate; a storage gate structure located on a portion of the substrate surface, the storage gate structure comprising a tunneling oxide layer, a charge trapping layer located on the tunneling oxide layer, a blocking layer located on the charge trapping layer, and a gate layer located on a surface of the blocking layer, wherein the dielectric constant of the blocking layer is greater than the dielectric constant of the charge trapping layer; A source doping region and a drain doping region are respectively located in the substrate on both sides of the storage gate structure.

2. The semiconductor structure according to claim 1, It is characterized in that The dielectric constant of the barrier layer is greater than 3.

9.

3. The semiconductor structure according to claim 2, It is characterized in that The material of the barrier layer includes HfAlO, HfSiO, HfO 2 One or more of .

4. The semiconductor structure according to claim 1, It is characterized in that The substrate comprises an epitaxial layer; the source doping region and the drain doping region are located in the epitaxial layer; and the material of the epitaxial layer comprises silicon carbide.

5. The semiconductor structure according to claim 4, It is characterized in that The epitaxial layer has a well region; the source doped region and the drain doped region are located in the well region, the well region has a first conductivity type, the source doped region and the drain doped region have a second conductivity type, and the first conductivity type is different from the second conductivity type.

6. The semiconductor structure according to claim 4, It is characterized in that The substrate also includes a base, and the epitaxial layer is located on the surface of the base; the material of the base includes silicon carbide.

7. The semiconductor structure according to claim 1, It is characterized in that The material of the gate layer is metal; the metal includes one or more of TiN, Ti, Al, W, Ag, Au, Cu, Ni and TaN.

8. The semiconductor structure according to claim 1, It is characterized in that The material of the tunneling oxide layer includes silicon oxide; the material of the charge trapping layer includes silicon nitride.

9. A method for forming a semiconductor structure, It is characterized in that include: providing a substrate; forming a storage gate structure on a portion of the substrate, the storage gate structure comprising a tunneling oxide layer, a charge trapping layer on the tunneling oxide layer, a blocking layer on the charge trapping layer, and a gate layer on a surface of the blocking layer, wherein the dielectric constant of the blocking layer is greater than the dielectric constant of the charge trapping layer; A source doping region and a drain doping region are respectively formed in the substrate at both sides of the storage gate structure.

10. The method for forming a semiconductor structure according to claim 9, It is characterized in that The method for forming the storage gate structure comprises: forming a storage gate material layer on the surface of the substrate, the storage gate material layer comprising a tunneling oxide material layer, a charge trapping material layer located on the surface of the tunneling oxide material layer, a blocking material layer located on the surface of the charge trapping material layer, and a gate material layer located on the surface of the blocking material layer; etching the storage gate material layer to form the storage gate structure, forming the tunneling oxide layer with the tunneling oxide material layer, forming the charge trapping layer with the charge trapping material layer, forming the blocking layer with the blocking material layer, and forming the gate layer with the gate material layer.

11. The method for forming a semiconductor structure according to claim 10, It is characterized in that The formation process of the tunneling oxide material layer includes a thermal oxidation process; and the material of the tunneling oxide layer includes silicon oxide.

12. The method for forming a semiconductor structure according to claim 10, It is characterized in that After forming the source doping region and the drain doping region, the storage gate structure is formed; the method for forming the source doping region and the drain doping region comprises: injecting doping ions into part of the substrate to form the source doping region and the drain doping region separated from each other in the substrate.

13. The method for forming a semiconductor structure according to claim 12, It is characterized in that The substrate comprises an epitaxial layer; the source doping region and the drain doping region are located in the epitaxial layer; and the material of the epitaxial layer comprises silicon carbide.

14. The method for forming a semiconductor structure according to claim 13, It is characterized in that The epitaxial layer has a well region; the source doped region and the drain doped region are located in the well region, the well region has a first conductivity type, the source doped region and the drain doped region have a second conductivity type, and the first conductivity type is different from the second conductivity type; the method also includes: before forming the source doped region and the drain doped region, forming the well region.

15. The method for forming a semiconductor structure according to claim 13, It is characterized in that The substrate also includes a base, and the epitaxial layer is located on the surface of the base; the material of the base includes silicon carbide.

16. The method for forming a semiconductor structure according to claim 9, It is characterized in that The dielectric constant of the barrier layer is greater than 3.

9.

17. The method for forming a semiconductor structure according to claim 9, It is characterized in that The material of the barrier layer includes HfAlO, HfSiO, HfO 2 One or more of .

18. The method for forming a semiconductor structure according to claim 9, It is characterized in that The material of the gate layer is metal; the metal includes one or more of TiN, Ti, Al, W, Ag, Au, Cu, Ni and TaN.

19. The method for forming a semiconductor structure according to claim 9, It is characterized in that The material of the tunneling oxide layer includes silicon oxide; the material of the charge trapping layer includes silicon nitride.

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