Semiconductor structure and forming method thereof

Abstract

The invention provides a semiconductor structure and a forming method thereof, and the method comprises the steps: providing a substrate which is internally provided with a drift region; forming a gate structure, wherein the gate structure covers a part of the drift region; a first body region is formed in the substrate, a first spacer region is arranged between the first body region and the drift region, and the doping type of the first spacer region is different from that of the drift region; a first inversion region is formed in the drift region, at least one part of the first inversion region is covered by the gate structure, and the doping type of the first inversion region is different from that of the drift region; the semiconductor structure is annealed, so that the first body region is diffused to the first interval region to obtain a second body region, the second body region is adjacent to the drift region, and the doping concentration of the second body region below the gate structure is gradually reduced in the direction adjacent to the drift region; a second inversion region is obtained based on the first inversion region, at least a part of the second inversion region is covered by the gate structure, and the doping type of the second inversion region is consistent with that of the first inversion region. By adopting the technical scheme, the breakdown voltage of the semiconductor structure can be improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a forming method thereof. Background Art

[0002] Voltage-controlled power devices refer to electronic devices whose operating state and output characteristics can be controlled according to voltage signals. They are widely used in industrial control, power electronics, power supply systems and other fields.

[0003] How to design voltage-controlled power devices is an issue worth discussing. Summary of the invention

[0004] In view of this, an embodiment of the present invention provides a semiconductor structure and a method for forming the same, which can improve the breakdown voltage of the semiconductor structure.

[0005] To solve the above technical problems, an embodiment of the present invention provides a method for forming a semiconductor structure. The method for forming a semiconductor structure includes: providing a substrate, wherein the substrate has a drift region; forming a gate structure on the substrate, wherein the gate structure covers a portion of the drift region; A first body region is formed in the substrate, wherein a first spacing region is provided between the first body region and the drift region, and the first body region and the drift region have different doping types; forming a first inversion region in the drift region, wherein at least a portion of the first inversion region is covered by the gate structure, and the first inversion region and the drift region have different doping types; Annealing the semiconductor structure so that the first body region diffuses into the first spacing region to obtain a second body region, wherein the second body region is adjacent to the drift region, and the doping concentration of the second body region below the gate structure gradually decreases in a direction adjacent to the drift region; A second inversion region is obtained based on the first inversion region, and at least a portion of the second inversion region is covered by the gate structure, wherein the doping type of the second inversion region is consistent with that of the first inversion region.

[0006] Optionally, a second spacing region is provided between the second inversion region and the gate structure.

[0007] Optionally, the semiconductor structure is an LDMOS device; The depth of the bottom surface of the second inversion region is less than or equal to the depth of the bottom surface of the second body region.

[0008] Optionally, the gate structure comprises a gate dielectric layer, a field dielectric layer and a gate body, wherein the field dielectric layer covers the drift region, the gate dielectric layer is adjacent to the field dielectric layer and covers the substrate adjacent to the drift region; the gate body covers the gate dielectric layer and the field dielectric layer; A first body region is formed, comprising: Ion implantation is performed on the substrate adjacent to the first spacing region to obtain a first body region, wherein the side is the side of the first spacing region away from the drift region.

[0009] Optionally, ion implantation is performed on the substrate adjacent to the first spacing region, comprising: Forming a patterned mask layer, wherein the patterned mask layer exposes the substrate adjacent to the first spacing region, wherein the side is a side of the first spacing region away from the drift region; Using the patterned mask layer as a mask, ion implantation is performed on the substrate adjacent to the first spacing region to obtain a first body region.

[0010] Optionally, the gate body covers a portion of the field dielectric layer adjacent to the gate dielectric layer, and exposes another portion of the field dielectric layer away from the gate dielectric layer.

[0011] Optionally, forming a first inversion region in the drift region includes: Ion implantation is performed on the substrate to obtain a first inversion region in the drift region not covered by the gate body.

[0012] Optionally, the thickness of the gate body is greater than or equal to 100 nanometers.

[0013] Optionally, the forming method further comprises: forming a drain region in a drift region not covered by the field dielectric layer; A source region is formed in the second body region not covered by the gate dielectric layer.

[0014] Optionally, obtaining the second inversion region based on the first inversion region comprises: In the process of forming the drain region, the first inversion region covered by the drain region is secondarily inverted, and the first inversion region covered by the field dielectric layer forms a second inversion region.

[0015] Optionally, the thickness of the field dielectric layer is greater than or equal to 100 nanometers.

[0016] To solve the above technical problems, an embodiment of the present invention provides a semiconductor structure. The semiconductor structure includes: a substrate, wherein the substrate has a drift region; A gate structure, the gate structure covering a portion of the drift region; A second body region, the second body region is adjacent to the drift region, and the doping concentration of the second body region below the gate structure gradually decreases along a direction adjacent to the drift region; The second inversion region is located in the drift region, at least a portion of the second inversion region is covered by the gate structure, and the second inversion region and the drift region have different doping types.

[0017] Optionally, a second spacing region is provided between the second inversion region and the gate structure.

[0018] Optionally, the semiconductor structure is an LDMOS device; The depth of the bottom surface of the second inversion region is less than or equal to the depth of the bottom surface of the second body region.

[0019] Optionally, the gate structure includes a gate dielectric layer, a field dielectric layer and a gate body, wherein the field dielectric layer covers the drift region, the gate dielectric layer is adjacent to the field dielectric layer and covers the substrate adjacent to the drift region; the gate body covers the gate dielectric layer and the field dielectric layer. Optionally, the gate body covers a portion of the field dielectric layer adjacent to the gate dielectric layer, and exposes another portion of the field dielectric layer away from the gate dielectric layer.

[0020] Optionally, the second inversion region is located in the drift region not covered by the gate body.

[0021] Optionally, the thickness of the gate body is greater than or equal to 100 nanometers.

[0022] Optionally, the semiconductor structure further comprises: A drain region, the drain region is located in the drift region not covered by the field dielectric layer; The source region is located in the second body region not covered by the gate dielectric layer.

[0023] Optionally, the thickness of the field dielectric layer is greater than or equal to 100 nanometers.

[0024] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages: In the semiconductor formation method provided by the embodiment of the present invention, the doping concentration of the second body region below the gate structure gradually decreases along the direction of the adjacent drift region, which can reduce the doping concentration of the second body region adjacent to the drift region, thereby increasing the width of the depletion region in the second body region and improving the breakdown voltage of the semiconductor structure; the second inversion region is in the drift region, and the doping type is different from that of the drift region, then the second inversion region forms a PN junction with the drift region in the drift region, and the second inversion region can assist in depleting the drift region, thereby enabling the depletion region to be fully widened without reducing the doping concentration of the drift region, which means that the second inversion region can further improve the breakdown voltage of the semiconductor structure without reducing the doping concentration of the drift region.

[0025] Furthermore, the first inversion region is in the drift region and has a different doping type from that of the drift region. The first inversion region forms a PN junction with the drift region in the drift region. The first inversion region can assist in depleting the drift region, thereby enabling the depletion region to be fully widened without reducing the doping concentration of the drift region. This means that the first inversion region can increase the breakdown voltage of the semiconductor structure without reducing the doping concentration of the drift region.

[0026] Furthermore, after removing the patterned mask layer, during the ion implantation process into the substrate, by setting the thickness of the gate body and selecting an appropriate ion implantation intensity, the gate body can prevent ions from being implanted into the substrate below the gate body, so that the first inversion zone is formed in the drift region exposed by the gate body. This means that before forming the first inversion zone, there is no need to form a new patterned mask layer above the gate body to prevent ions from being implanted into the substrate below the gate body, thereby reducing the preparation cost of the semiconductor structure.

[0027] Furthermore, there is a second spacing region between the first inversion region and the field dielectric layer, and the conduction path of the semiconductor structure in the drift region passes through the second spacing region. Compared with the first inversion region being adjacent to the field dielectric layer, the conduction path of the semiconductor structure in the drift region passes under the first inversion region. The former has a shorter conduction path and a smaller on-resistance.

[0028] Furthermore, the first inversion region exposed by the field dielectric layer and covered by the drain region is inverted for the second time, the remaining first inversion region covered by the field dielectric layer forms a second inversion region, and the second spacing region between the second inversion region and the field dielectric layer is the second spacing region between the remaining first inversion region covered by the field dielectric layer and the field dielectric layer.

[0029] Furthermore, the depth of the bottom surface of the second inversion zone is less than or equal to the depth of the bottom surface of the second body region, so that the auxiliary depletion area of ​​the second inversion zone in the drift region is located on one side of the second body region, thereby improving the breakdown voltage of the semiconductor structure along the direction parallel to the substrate surface. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions of the embodiments of this specification, the drawings required for use in the embodiments of this specification or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this specification. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0031] Figure 1 is a flow chart of a method for forming a semiconductor structure in an embodiment of the present invention; Figures 2 to 5 It is a schematic cross-sectional structure diagram corresponding to each step in a method for forming a semiconductor structure in an embodiment of the present invention.

[0032] Description of reference numerals: Substrate 100, drift region 110, first body region 120, second body region 121, first inversion region 130, second inversion region 131, source region 140, drain region 150, extraction region 160, first spacing region 101, second spacing region 102, isolation ring 200, gate structure 300, gate dielectric layer 310, field dielectric layer 320, gate body 330, mask layer 400. DETAILED DESCRIPTION

[0033] As can be seen from the background technology, how to design a voltage-controlled power device is an issue worth discussing.

[0034] Taking LDMOS as an example, LDMOS has a drift region and a body region, and a depletion region is formed at the junction of the drift region and the body region.

[0035] In a specific application scenario, in order to obtain a high-voltage LDMOS device, it is necessary to reduce the doping concentration of the drift region so that the depletion region is fully widened, which will increase the on-resistance of the LDMOS device.

[0036] In another specific application scenario, in order to obtain a low-resistance LDMOS device, it is necessary to increase the doping concentration of the device, which will prevent the depletion layer in the drift region from widening and reduce the breakdown voltage of the LDMOS device.

[0037] In order to solve the above technical problems, in an embodiment of the present invention, the doping concentration of the second body region under the gate structure gradually decreases along the direction of the adjacent drift region, which can reduce the doping concentration of the second body region adjacent to the drift region, thereby increasing the width of the depletion region in the second body region and improving the breakdown voltage of the semiconductor structure; the second inversion region is in the drift region, and the doping type is different from that of the drift region, then the second inversion region forms a PN junction with the drift region in the drift region, and the second inversion region can assist in depleting the drift region, thereby enabling the depletion region to be fully widened without reducing the doping concentration of the drift region, which means that the second inversion region can further improve the breakdown voltage of the semiconductor structure without reducing the doping concentration of the drift region.

[0038] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0039] Reference Figure 1 , Figure 1 A flow chart of a method for forming a semiconductor structure in an embodiment of the present invention is shown. The method for forming a semiconductor structure may include steps S11 to S16: Step S11: providing a substrate, wherein the substrate has a drift region; Step S12: forming a gate structure on the substrate, wherein the gate structure covers a portion of the drift region; Step S13: forming a first body region in the substrate, wherein a first spacing region is provided between the first body region and the drift region, and the first body region and the drift region have different doping types; Step S14: forming a first inversion region in the drift region, wherein at least a portion of the first inversion region is covered by the gate structure, and the first inversion region and the drift region have different doping types; Step S15: annealing the semiconductor structure to diffuse the first body region into the first spacing region to obtain a second body region, wherein the second body region is adjacent to the drift region, and the doping concentration of the second body region below the gate structure gradually decreases in a direction adjacent to the drift region; Step S16: obtaining a second inversion region based on the first inversion region, wherein at least a portion of the second inversion region is covered by the gate structure, wherein the doping type of the second inversion region is consistent with that of the first inversion region.

[0040] The following combination Figures 2 to 5 The above-mentioned formation method is explained.

[0041] Figures 2 to 5 It is a schematic cross-sectional structure diagram corresponding to each step in a method for forming a semiconductor structure in an embodiment of the present invention.

[0042] Reference Figure 2 , providing a substrate 100; Specifically, the substrate 100 is used to provide a process platform for the subsequent formation of a semiconductor structure.

[0043] In some embodiments, the substrate 100 may be a silicon substrate, or the material of the substrate 100 may also include germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium. The substrate 100 may also be a silicon substrate on an insulator or a germanium substrate on an insulator, or a substrate on which an epitaxial layer (Epitaxylayer, Epilayer) is grown.

[0044] In some embodiments, the doping type of the substrate 100 may be P-type doping or N-type doping.

[0045] It should be noted that in the following description, P-type doping may be used as an example for illustration, but it does not constitute a limitation on the specific doping type used for the substrate 100 .

[0046] Continue to refer to Figure 2 , an isolation ring 200 is formed on the substrate 100 .

[0047] Specifically, the step of forming the isolation ring 200 may include: etching the surface of the substrate 100 to obtain an isolation ring groove (not shown); and filling the isolation ring groove to obtain the isolation ring 200 .

[0048] Specifically, the isolation ring 200 is a ring structure, which can achieve electrical isolation between the inside and outside of the ring.

[0049] In some embodiments, the material of the isolation ring 200 may be silicon dioxide.

[0050] Continue to refer to Figure 2 , a drift region 110 is formed in the substrate 100 .

[0051] In some embodiments, the drift region 110 may be formed in the isolation ring groove by using an ion implantation process.

[0052] In some embodiments, the doping type of the drift region 110 may be N-type doping or P-type doping.

[0053] It should be noted that, in the following description, N-type trench doping may be used as an example for explanation, but it does not constitute a limitation on the specific doping type used in the drift region 110 .

[0054] Continue to refer to Figure 2 , a gate structure 300 is formed on the substrate 100 .

[0055] Specifically, the step of forming the gate structure 300 may include: forming a gate dielectric layer 310 and a field dielectric layer 320 of the gate structure 300 on the substrate 100 ; and forming a gate body 330 of the gate structure 300 on the gate dielectric layer 310 and the field dielectric layer 320 .

[0056] The field dielectric layer 320 covers the drift region 110 , and the gate dielectric layer 310 is adjacent to the field dielectric layer 320 and covers the substrate 100 adjacent to the drift region 110 .

[0057] It should be noted that reducing the thickness of the gate dielectric layer 310 can enhance the control capability of the gate body 330 over the conduction channel, wherein the conduction channel is formed in the substrate 100 covered by the gate dielectric layer 310; increasing the thickness of the field dielectric layer 320 can enhance its ability to block ion injection.

[0058] In some embodiments, the gate dielectric layer 310 is thinner than the field dielectric layer 320 .

[0059] Continue to refer to Figure 2 , forming a patterned mask layer 400.

[0060] The patterned mask layer 400 covers the gate structure 300 and the drift region 110 exposed by the gate structure 300 , and exposes the substrate 100 adjacent to the gate dielectric layer 310 , which is a side of the gate dielectric layer 310 away from the field dielectric layer 320 .

[0061] Reference Figure 3 , a first body region 120 is formed in the substrate 100 .

[0062] The doping type of the first body region 120 is different from that of the drift region 110 .

[0063] Specifically, ion implantation is performed on the substrate 100 to obtain the first body region 120 on the substrate 100 adjacent to the gate dielectric layer 310 , where the adjacent side is a side of the gate dielectric layer 310 away from the field dielectric layer 320 .

[0064] Specifically, during the process of forming the first body region 120 , the patterned mask layer 400 can prevent ions from being implanted into the substrate 100 below the mask layer 400 , so that the first body region 120 is formed in the substrate 100 adjacent to the gate dielectric layer 310 .

[0065] In some embodiments, a first spacing region 101 is provided between the first body region 120 and the drift region 110 . The first spacing region 101 belongs to the substrate 100 and is located below the gate dielectric layer 310 .

[0066] Reference Figure 4 , forming a first inversion region 130.

[0067] Specifically, the step of forming the first inversion region 130 may include: removing the patterned mask layer 400 ; and performing ion implantation on the substrate 100 to obtain the first inversion region 130 in the drift region 110 exposed by the gate body 330 .

[0068] The doping type of the first inversion region 130 is different from the doping type of the drift region 110 .

[0069] Specifically, the first inversion region 130 is in the drift region 110 and has a different doping type from that of the drift region 110. Then, the first inversion region 130 forms a PN junction with the drift region 110 in the drift region 110. The first inversion region 130 can assist in depleting the drift region 110, thereby enabling the depletion region to be fully widened without reducing the doping concentration of the drift region 110. This means that the first inversion region 130 can improve the breakdown voltage of the semiconductor structure without reducing the doping concentration of the drift region 110.

[0070] In some embodiments, the gate body 330 covers a portion of the field dielectric layer 320 adjacent to the gate dielectric layer 310 and exposes another portion of the field dielectric layer 320 away from the gate dielectric layer 310 .

[0071] Specifically, after removing the patterned mask layer 400, during the ion implantation process on the substrate 100, by setting the thickness of the gate body 330 and selecting a suitable ion implantation intensity, the gate body 330 can prevent ions from being implanted into the substrate 100 below the gate body 330, so that the first inversion zone 130 is formed in the drift zone 110 exposed by the gate body 330; this means that before forming the first inversion zone 130, there is no need to form a new patterned mask layer 400 above the gate body 330 to prevent ions from being implanted into the substrate 100 below the gate body 330, thereby reducing the preparation cost of the semiconductor structure.

[0072] In some embodiments, the thickness of the gate body 330 may be greater than or equal to 100 nanometers.

[0073] It should be noted that the thickness referred to herein refers to the dimension along a direction perpendicular to the surface of the substrate 100 .

[0074] In some embodiments, during the process of performing ion implantation on the substrate 100 to obtain the first inversion region 130 , the doping concentration of the first body region 120 is increased.

[0075] Specifically, before and after removing the patterned mask layer 400 , the same type of ion implantation is performed into the substrate 100 corresponding to the first body region 120 , so that the doping concentration of the first body region 120 is increased.

[0076] In some embodiments, at least a portion of the first inversion region 130 is covered by the field dielectric layer 320 . In some embodiments, the first inversion region 130 is adjacent to the field dielectric layer 320 .

[0077] In some embodiments, a second spacing region 102 is provided between the first inversion region 130 and the field dielectric layer 320 , and the second spacing region 102 belongs to the drift region 110 .

[0078] Specifically, there is a second spacing region 102 between the first inversion region 130 and the field dielectric layer 320. The conduction path of the semiconductor structure in the drift region 110 passes through the second spacing region 102. Compared with the first inversion region 130 being adjacent to the field dielectric layer 320, the conduction path of the semiconductor structure in the drift region 110 (e.g. Figure 5 The path represented by the arrow shown in FIG) passes under the first inversion region 130, and the former has a shorter conduction path and a smaller conduction resistance.

[0079] Reference Figure 5 , forming a second body region 121.

[0080] Specifically, the step of forming the second body region 121 may include: annealing the semiconductor structure to diffuse the first body region 120 into the first spacing region 101 to obtain the second body region 121, wherein the second body region 121 is adjacent to the drift region 110, and the doping concentration of the second body region 121 below the gate dielectric layer 310 gradually decreases along the direction adjacent to the drift region 110.

[0081] Specifically, this can reduce the doping concentration of the second body region 121 adjacent to the drift region 110 , thereby increasing the width of the depletion region in the second body region 121 , and further improving the breakdown voltage of the semiconductor structure.

[0082] Continue to refer to Figure 5 , a source region 140 is formed in the second body region 121 exposed by the gate structure 300 ; and a drain region 150 is formed in the drift region 110 exposed by the gate structure 300 .

[0083] The source region 140 and the body region have different doping types, the drain region 150 and the source region 140 have the same doping type, and the doping concentration of the drain region 150 is higher than that of the drift region 110 .

[0084] In some embodiments, the source region 140 and the drain region 150 may be formed in various orders. For example, the drain region 150 may be formed during the process of forming the source region 140. For example, the source region 140 may be formed after the drain region 150. For example, the source region 140 may be formed before the drain region 150.

[0085] In some embodiments, during the process of forming the drain region 150 , the first inversion region 130 covered by the drain region 150 is secondarily inverted, and the first inversion region 130 covered by the field dielectric layer 320 forms the second inversion region 131 .

[0086] Specifically, the first inversion region 130 exposed by the field dielectric layer 320 and covered by the drain region 150 is inverted for the second time, and the remaining first inversion region 130 covered by the field dielectric layer 320 forms a second inversion region 131. The second spacing region 102 between the second inversion region 131 and the field dielectric layer 320 is the second spacing region 102 between the remaining first inversion region 130 covered by the field dielectric layer 320 and the field dielectric layer 320.

[0087] It should be pointed out that the second inversion region 131 is in the drift region 110 and has a different doping type from that of the drift region 110. The second inversion region 131 forms a PN junction with the drift region 110 in the drift region 110. The second inversion region 131 can assist in depleting the drift region 110, thereby enabling the depletion region to be fully widened without reducing the doping concentration of the drift region 110. This means that the second inversion region 131 can improve the breakdown voltage of the semiconductor structure without reducing the doping concentration of the drift region 110.

[0088] In some embodiments, the depth of the top surface of the second inversion region 131 is greater than or equal to the depth of the bottom surface of the source region 140 ; ​​and / or, the depth of the top surface of the second inversion region 131 is greater than or equal to the depth of the bottom surface of the drain region 150 .

[0089] Specifically, this can improve the breakdown voltage of the semiconductor structure along a direction parallel to the surface of the substrate 100 while preventing the second spacing region 102 from being inverted.

[0090] In some embodiments, at least a portion of the second inversion region 131 is covered by the field dielectric layer 320 .

[0091] It should be pointed out that in the process of ion implantation into the second body region 121 to form the source region 140, by setting the thickness of the field dielectric layer 320 and selecting an appropriate ion implantation intensity, the field dielectric layer 320 can prevent ions from being implanted into the substrate 100 below the field dielectric layer 320, so that the first inversion region 130 under the field dielectric layer 320 will not be inverted during this round of ion implantation.

[0092] In some embodiments, a depth of a bottom surface of the second inversion region 131 is less than or equal to a depth of a bottom surface of the second body region 121 .

[0093] Specifically, in this way, the auxiliary depletion region of the second inversion region 131 in the drift region 110 is located on one side of the second body region 121 , thereby improving the breakdown voltage of the semiconductor structure along a direction parallel to the surface of the substrate 100 .

[0094] In some embodiments, the thickness of the field dielectric layer 320 may be greater than or equal to 100 nanometers.

[0095] Continue to refer to Figure 5 , an extraction region 160 is formed in the source region 140 .

[0096] The bottom surface of the extraction region 160 covers the second body region 121 , and the extraction region 160 has the same doping type as the second body region 121 , and the doping concentration is higher than that of the second body region 121 .

[0097] Specifically, the extraction region 160 can extract the charges accumulated in the second body region 121 , thereby reducing the potential fluctuation of the second body region 121 .

[0098] In some embodiments, the semiconductor structure may be an LDMOS device, which includes a semiconductor unit, wherein the semiconductor unit may include a drift region 110 , a second body region 121 , a source region 140 , a drain region 150 , an extraction region 160 , a second inversion region 131 and a gate structure 300 .

[0099] Furthermore, the semiconductor structure may be a symmetrical LDMOS device, which includes two symmetrical semiconductor units, and the two symmetrical semiconductor units share the same second body region 121 , source region 140 , and extraction region 160 .

[0100] Specifically, sharing the same second body region 121 , source region 140 , and extraction region 160 can improve the current driving capability of the LDMOS device, while also simplifying the layout and improving the integration of the device.

[0101] It should be noted that, in addition to the shared second body region 121, source region 140 and extraction region 160, each semiconductor unit in the symmetric LDMOS device may have its own drift region 110, drain region 150 and second inversion region 131, and the above-mentioned parts may be completely consistent or not completely consistent.

[0102] Furthermore, the semiconductor unit may be located in a region surrounded by the isolation ring 200 .

[0103] As shown in the figure, the two symmetrical semiconductor units may be located in a region surrounded by the same isolation ring 200 .

[0104] Specifically, the isolation ring 200 is disposed around the semiconductor unit to achieve electrical isolation between semiconductor units of adjacent semiconductor structures. More specifically, the isolation ring 200 can be used to isolate semiconductor structures without affecting electrical conduction between two semiconductor units in the same semiconductor structure.

[0105] In an embodiment of the present invention, a semiconductor structure may also be provided. Figures 2 to 5 The semiconductor structure includes: a substrate 100, wherein the substrate 100 has a drift region 110; a gate structure 300, wherein the gate structure 300 covers a portion of the drift region 110; a second body region 121, wherein the second body region 121 is adjacent to the drift region 110, and the doping concentration of the second body region 121 below the gate structure 300 gradually decreases along a direction adjacent to the drift region 110; and a second inversion region 131, wherein the second inversion region 131 is located in the drift region 110, and at least a portion of the second inversion region 131 is covered by the gate structure 300, and the second inversion region 131 has a different doping type from that of the drift region 110.

[0106] In some embodiments, a second spacing region 102 may be provided between the second inversion region 131 and the gate structure 300 .

[0107] In some embodiments, the depth of the bottom surface of the second inversion region 131 may be less than or equal to the depth of the bottom surface of the second body region 121 .

[0108] In some embodiments, the gate structure 300 may include a gate dielectric layer 310, a field dielectric layer 320 and a gate body 330, wherein the field dielectric layer 320 covers the drift region 110, the gate dielectric layer 310 is adjacent to the field dielectric layer 320, and covers the substrate 100 adjacent to the drift region 110; the gate body 330 covers the gate dielectric layer 310 and the field dielectric layer 320. In some embodiments, the gate body 330 covers a portion of the field dielectric layer 320 adjacent to the gate dielectric layer 310 and exposes another portion of the field dielectric layer 320 away from the gate dielectric layer 310 .

[0109] In some embodiments, the second inversion region 131 is located in the drift region 110 not covered by the gate body 330 .

[0110] In some embodiments, the thickness of the gate body 330 is greater than or equal to 100 nanometers.

[0111] In some embodiments, the semiconductor structure may further include: a drain region 150 located in the drift region 110 not covered by the field dielectric layer 320 ; and a source region 140 located in the second body region 121 not covered by the gate dielectric layer 310 .

[0112] In some embodiments, the thickness of the field dielectric layer 320 is greater than or equal to 100 nanometers.

[0113] In some embodiments, the semiconductor structure may further include: an extraction region 160 , the extraction region 160 is located in the source region 140 , wherein the bottom surface of the extraction region 160 covers the second body region 121 , the extraction region 160 has the same doping type as the second body region 121 , and the doping concentration is higher than that of the second body region 121 .

[0114] In some embodiments, the semiconductor structure may be an LDMOS device, which includes a semiconductor unit, wherein the semiconductor unit may include a drift region 110 , a second body region 121 , a source region 140 , a drain region 150 , an extraction region 160 , a second inversion region 131 and a gate structure 300 .

[0115] Furthermore, the semiconductor structure may be a symmetrical LDMOS device, which includes two symmetrical semiconductor units, and the two symmetrical semiconductor units share the same second body region 121 , source region 140 , and extraction region 160 .

[0116] Specifically, sharing the same second body region 121 , source region 140 , and extraction region 160 can improve the current driving capability of the LDMOS device, while also simplifying the layout and improving the integration of the device.

[0117] It should be noted that, in addition to the shared second body region 121, source region 140 and extraction region 160, each semiconductor unit in the symmetric LDMOS device may have its own drift region 110, drain region 150 and second inversion region 131, and the above-mentioned parts may be completely consistent or not completely consistent.

[0118] In some embodiments, the semiconductor structure may further include an isolation ring 200 , and the semiconductor unit may be located in a region surrounded by the isolation ring 200 .

[0119] As shown in the figure, the two symmetrical semiconductor units may be located in a region surrounded by the same isolation ring 200 .

[0120] Specifically, the isolation ring 200 is disposed around the semiconductor unit to achieve electrical isolation between semiconductor units of adjacent semiconductor structures. More specifically, the isolation ring 200 can be used to isolate semiconductor structures without affecting electrical conduction between two semiconductor units in the same semiconductor structure.

[0121] It should be noted that the semiconductor structure in the embodiment of the present invention can be formed by the formation method described in the above embodiment, or by other formation methods. For the specific description of the semiconductor structure in the embodiment of the present invention, reference can be made to the corresponding description in the above embodiment, and this embodiment will not be repeated here.

[0122] It is understandable that the term "and / or" in this article is only a description of the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article indicates that the associated objects before and after are in an "or" relationship.

[0123] It is understood that the "multiple" mentioned herein refers to two or more than two. The first, second, etc. descriptions in the embodiments of the present application are only used for illustration and distinction of the described objects, and have no order, nor do they represent any special limitation on the number of devices in the embodiments of the present application, and cannot constitute any limitation on the embodiments of the present application.

[0124] It can be understood that the above describes multiple implementation schemes provided by the embodiments of the present invention, and the various optional methods introduced in each implementation scheme can be combined and cross-referenced with each other without conflict, thereby extending a variety of possible implementation schemes, which can all be considered as the implementation schemes disclosed and open to the public by the present invention.

[0125] Although the embodiments of the present invention are disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: providing a substrate having a drift region therein; forming a gate structure on the substrate, wherein the gate structure covers a portion of the drift region; forming a first body region in the substrate, wherein a first spacing region is provided between the first body region and the drift region, and the first body region and the drift region have different doping types; forming a first inversion region in the drift region, wherein at least a portion of the first inversion region is covered by the gate structure, and the first inversion region and the drift region have different doping types; Annealing the semiconductor structure so that the first body region diffuses into the first spacing region to obtain a second body region, wherein the second body region is adjacent to the drift region, and the doping concentration of the second body region under the gate structure gradually decreases in a direction adjacent to the drift region; A second inversion region is obtained based on the first inversion region, at least a portion of the second inversion region is covered by the gate structure, wherein the doping type of the second inversion region is consistent with that of the first inversion region.

2. The forming method according to claim 1, characterized in that: A second spacing region is provided between the second inversion region and the gate structure.

3. The forming method according to claim 2, characterized in that: The semiconductor structure is an LDMOS device; The depth of the bottom surface of the second inversion region is less than or equal to the depth of the bottom surface of the second body region.

4. The forming method according to claim 1, characterized in that: The gate structure comprises a gate dielectric layer, a field dielectric layer and a gate body, wherein the field dielectric layer covers the drift region, the gate dielectric layer is adjacent to the field dielectric layer and covers the substrate adjacent to the drift region; the gate body covers the gate dielectric layer and the field dielectric layer; Forming the first body region comprises: Ion implantation is performed on the substrate adjacent to the first spacing region to obtain the first body region, wherein the side is a side of the first spacing region away from the drift region.

5. The forming method according to claim 4, characterized in that: Performing ion implantation on the substrate adjacent to the first spacing region comprises: forming a patterned mask layer, wherein the patterned mask layer exposes the substrate adjacent to the first spacing region, wherein the side is a side of the first spacing region away from the drift region; Using the patterned mask layer as a mask, ion implantation is performed on the substrate adjacent to the first spacing region to obtain the first body region.

6. The forming method according to claim 4, characterized in that: The gate body covers a portion of the field dielectric layer adjacent to the gate dielectric layer and exposes another portion of the field dielectric layer away from the gate dielectric layer.

7. The forming method according to claim 6, characterized in that: Forming a first inversion region in the drift region comprises: Ion implantation is performed on the substrate to obtain a first inversion region in the drift region not covered by the gate body.

8. The forming method according to claim 6, characterized in that: The thickness of the gate body is greater than or equal to 100 nanometers.

9. The forming method according to claim 4, characterized in that: The method further comprises: forming a drain region in the drift region not covered by the field dielectric layer; A source region is formed in the second body region not covered by the gate dielectric layer.

10. The forming method according to claim 9, characterized in that: Obtaining a second inversion region based on the first inversion region comprises: In the process of forming the drain region, the first inversion region covered by the drain region is inverted twice, and the first inversion region covered by the field dielectric layer forms the second inversion region.

11. The forming method according to claim 9, characterized in that: The thickness of the field dielectric layer is greater than or equal to 100 nanometers.

12. A semiconductor structure, characterized in that: include: a substrate having a drift region therein; a gate structure, wherein the gate structure covers a portion of the drift region; a second body region, the second body region being adjacent to the drift region, and the doping concentration of the second body region below the gate structure gradually decreases along a direction adjacent to the drift region; A second inversion region, wherein the second inversion region is located in the drift region, at least a portion of the second inversion region is covered by the gate structure, and the second inversion region and the drift region have different doping types.

13. The semiconductor structure according to claim 12, characterized in that: A second spacing region is provided between the second inversion region and the gate structure.

14. The semiconductor structure according to claim 13, characterized in that: The semiconductor structure is an LDMOS device; The depth of the bottom surface of the second inversion region is less than or equal to the depth of the bottom surface of the second body region.

15. The semiconductor structure according to claim 12, characterized in that: The gate structure comprises a gate dielectric layer, a field dielectric layer and a gate body, wherein the field dielectric layer covers the drift region, the gate dielectric layer is adjacent to the field dielectric layer and covers the substrate adjacent to the drift region; the gate body covers the gate dielectric layer and the field dielectric layer.

16. The semiconductor structure according to claim 15, characterized in that The gate body covers a portion of the field dielectric layer adjacent to the gate dielectric layer and exposes another portion of the field dielectric layer away from the gate dielectric layer.

17. The semiconductor structure according to claim 16, characterized in that: The second inversion region is located in the drift region not covered by the gate body.

18. The semiconductor structure according to claim 16, characterized in that The thickness of the gate body is greater than or equal to 100 nanometers.

19. The semiconductor structure according to claim 15, characterized in that The semiconductor structure further comprises: a drain region, the drain region being located in a drift region not covered by the field dielectric layer; A source region is located in the second body region not covered by the gate dielectric layer.

20. The semiconductor structure according to claim 19, characterized in that The thickness of the field dielectric layer is greater than or equal to 100 nanometers.

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