Red light LED chip and manufacturing method thereof

Abstract

The invention relates to the technical field of chips, in particular to a red light LED chip and a manufacturing method thereof. The red light LED chip comprises a back electrode, a Si substrate, an Au bonding layer, an In bonding layer, a transition barrier layer, a mirror layer, a dielectric film layer, an ohmic contact layer, an Au filling barrier layer, a GaP window layer, a P-type transition layer, a P-type limiting layer, a P-type waveguide layer, a light emitting layer, an N-type semiconductor layer, a roughened spherical island, a passivation layer and a front electrode from bottom to top. The Au filling barrier layer is positioned in a chip cutting channel projection area and is coated by the dielectric film layer; the surface, protruding towards the mirror surface layer, of the ohmic contact layer is an arc-shaped surface. Pyramid suede surfaces are uniformly distributed on the surfaces of the roughened spherical islands. The manufacturing method is optimized, and the obtained red light LED chip is high in luminous efficiency, good in reliability and stable in overall performance.

Description

Technical Field

[0001] The present invention relates to the technical field of chips, and in particular to a red light LED chip and a manufacturing method thereof. Background Art

[0002] Light-emitting diodes (LEDs) have the advantages of high luminous efficiency, long service life, and green energy saving and environmental protection. They are widely used in daily life, such as primary lighting, traffic signal display, outdoor stage lighting, plant lighting, etc. As the scope of application continues to expand, higher requirements are placed on luminous efficiency and reliability. How to improve luminous efficiency while ensuring device reliability and stability has become an urgent problem to be solved. Summary of the invention

[0003] In view of the deficiencies in the prior art, the present invention provides a red light LED chip and a method for manufacturing the same. The LED chip has high luminous efficiency, good reliability, and stable overall device performance.

[0004] The present invention provides a method for manufacturing a red light LED chip, comprising the following steps: S1. On a GaAs substrate, a red LED epitaxial wafer is grown using MOCVD (metal organic chemical vapor deposition), and an N-type semiconductor layer, a light-emitting layer, a P-type semiconductor layer, and a GaP window layer are grown in sequence; S2. On the epitaxial wafer, using photolithography and etching technology, a patterned P-face pattern is formed on the surface of the GaP window layer, and etching is performed through the GaP window layer; S3. Depositing a dielectric film layer on the surface for the first time using PECVD (plasma enhanced chemical vapor deposition); S4. Using photolithography technology, inserting an Au filling barrier layer in the area corresponding to the chip cutting road by stripping; S5. Depositing a dielectric film layer on the surface for the second time using PECVD; S6. Using photolithography and etching technology, a dielectric film through hole is etched on the patterned P-face pattern step and ends at the GaP window layer, wherein the through hole pattern is consistent with the shape of the patterned P-face pattern; S7. Depositing an ohmic contact layer by thermal evaporation using a metal evaporator; S8. using electron beam evaporation to deposit a mirror layer, a transition barrier layer, and an In bonding layer; S9. Take a Si substrate and deposit an Au bonding layer on the surface of the Si substrate by electron beam evaporation; S10. Bonding the epitaxial wafer and the Si substrate together by metal bonding, and removing the GaAs substrate by chemical etching to expose the roughened layer of the N-type semiconductor layer; S11. The front electrode is fabricated by negative photolithography and lift-off process; S12. Using positive resist to make cutting path patterns, and using dry etching to etch the cutting paths to the dielectric film layer; S13. Spin-coating the surface of the roughened layer except the front electrode with a dispersant colloid, and using a heat curing method to make the dispersant colloid into uniformly distributed mask cylinders or spheres, and using dry etching and a roughening liquid to make the roughened layer into roughened spherical islands with a pyramid velvet surface, and finally using a cleaning machine to wash away the dispersant colloid; S14. Depositing a passivation layer on the area other than the front electrode and the surface treated in S13 by PECVD, and completing the patterning of the passivation layer by photolithography and etching; S15. The LED core is manufactured by mechanically thinning the Si substrate and performing back electrode fabrication, laser cutting, and testing.

[0005] The invention optimizes the manufacturing method, firstly manufactures a P-face pattern on the surface of a GaP window layer and etches through the GaP window layer, so that the current can be isolated from being horizontally extended over a long distance, so that the current is effectively injected into the light-emitting area, and the absorption of light by the GaP window layer is also reduced, thereby improving the luminous efficiency; then, an Au filling barrier layer is inserted into a dielectric film layer located in a projection area of ​​a cutting path, so that the mirror layer can be effectively protected during dry etching and laser cutting, and the reliability is good; then, AuZn is evaporated by direct thermal evaporation, which not only has a simple manufacturing process, a short time, and is easy to form an alloy, but also forms an arc surface after evaporation, thereby increasing the contact area between the mirror layer and the mirror layer, and having better stability; finally, a dispersant colloid is spin-coated on the roughened surface, and thermal curing is performed to form uniformly distributed spherical islands on the surface, and the surface presents a pyramid velvet surface, so that not only the roughening area is increased, but also the light output angle can be increased, thereby further improving the luminous efficiency.

[0006] Furthermore, in the above technical solution S1, the GaP window layer is a GaP layer with a thickness of 0.5 μm-1.0 μm; the P-type semiconductor layer is a P-type waveguide layer, a P-type confinement layer, and a P-type transition layer from bottom to top in the growth direction of the epitaxial wafer; the P-type transition layer is made of P-Al 40 GaInP to P-Al 20 GaInP is sequentially transitioned to the GaP window layer; the material of the roughening layer of the N-type semiconductor layer is composed of N-Al 60 GaInP to N-Al 20 GaInP transitions toward the GaP window layer in turn, with a thickness of 3μm-4μm. In this technical solution, both the P-type transition layer and the roughening layer of the N-type semiconductor layer use a gradient aluminum component, which can ensure lattice gradient and improve the purpose of structural adaptation.

[0007] Furthermore, in the above technical solution S2, the method for making the patterned P-face graphics is: use ICP to etch away the exposed GaP window layer, and etch down to the P-type restriction layer to stop, and then use photoresist removal liquid to remove the photoresist on the surface; the ratio of the etched area to the retained area is 3:7. Since the material of the P-type transition layer has a refractive index difference, in this technical solution, the etching of the P-type restriction layer stops after the P-face graphics, which can not only reduce the absorption of the light emitted by the light-emitting layer by the P-type restriction layer, but also reduce its absorption of the light reflected from the mirror to the front side, further improving the luminous efficiency. The photoresist removal liquid is a degumming liquid, and any existing degumming liquid that can remove photoresist can be used.

[0008] Furthermore, in the above technical solution S3, the thickness of the dielectric film layer deposited for the first time is 1500±100 angstroms; in S5, the thickness of the dielectric film deposited for the second time is 3500±200 angstroms. In this technical solution, the dielectric film layer is deposited twice, firstly, the concave position after the P-surface pattern is made can be filled to ensure the flatness of the subsequent dielectric film, and secondly, an Au filling barrier layer can be inserted into the dielectric film layer located in the projection area of ​​the cutting path to improve reliability.

[0009] Furthermore, in the above technical solution S4, the size of the Au-filled barrier layer is larger than the chip cutting road size. In this technical solution, the size of the Au-filled barrier layer is larger than the chip cutting road size, which can effectively protect the mirror layer during dry etching and laser cutting.

[0010] Furthermore, in the above technical solution S7, the material of the ohmic contact layer is AuZn, the thickness is 2000±10 angstroms, and the total thermal evaporation time is 10min-15min. In this technical solution, the ohmic contact layer alloy is made by direct thermal evaporation, which not only has a simpler process, shorter time and higher efficiency, but also increases the contact area with the mirror layer and has better stability.

[0011] Furthermore, in the above technical solution S8, the material of the mirror layer is Ag, with a thickness of 3000±100 angstroms; the materials of the transition barrier layer are Ti / Pt / Ti / Pt / Au in sequence, with a total thickness of 10000±500 angstroms; the thickness of the In bonding layer is 3±0.5μm; in S9, the thickness of the Au bonding layer is 2±0.2μm.

[0012] Furthermore, in the above technical solution S10, the bonding temperature is 200±5°C, the pressure is 2000±10kgf, and the chemical etching solution used is a mixed solution of ammonia water and hydrogen peroxide in any volume ratio, preferably 15:1. In this technical solution, bonding is performed in a low temperature and low pressure manner, which can reduce the impact on the metal mirror material and the metal layer and ensure the luminous efficiency.

[0013] Furthermore, in the above technical solution S13, the dispersant colloid is a nanoscale resin; the thermal curing method is first heating at 120°C for 300s, and then maintaining at 200°C for 30min for curing; the roughening liquid is a mixed solution of phosphoric acid, glacial acetic acid, hydrogen peroxide and water in any volume ratio.

[0014] The present invention also provides a red light LED chip manufactured by the above manufacturing method, wherein the red light LED chip comprises, from bottom to top, a back electrode, a Si substrate, an Au bonding layer, an In bonding layer, a transition barrier layer, a mirror layer, a dielectric film layer, an ohmic contact layer, an Au filling barrier layer, a GaP window layer, a P-type transition layer, a P-type restriction layer, a P-type waveguide layer, a light-emitting layer, an N-type semiconductor layer, a roughened spherical island, a passivation layer, and a front electrode; the Au filling barrier layer is located in the projection area of ​​the chip cutting path and is covered by the dielectric film layer; the surface of the ohmic contact layer convex to the mirror layer is an arc surface; and the surface of the roughened spherical island is evenly distributed with a pyramid velvet surface.

[0015] Compared with the prior art, the present invention has the following beneficial effects: The present invention optimizes the manufacturing method. By manufacturing a P-face pattern on the surface of the GaP window layer and etching through the GaP window layer and the P-type transition layer, not only can the lateral long-distance expansion of the current be isolated, and the current is effectively injected into the light-emitting area, but also the absorption of the light emitted by the light-emitting layer and the light reflected by the mirror surface to the front side by the GaP window layer and the P-type transition layer is reduced, thereby greatly improving the light-emitting efficiency. By inserting an Au-filled barrier layer into the dielectric film layer located in the projection area of ​​the cutting path, the mirror layer can be effectively protected in the process of dry etching and laser cutting, thereby improving the reliability. By adopting direct thermal The AuZn alloy is evaporated by evaporation, which is not only simple in process and time, but also easy to form an alloy. At the same time, it can form an arc surface after evaporation, which increases its contact area with the mirror layer and has better stability. By spin-coating a dispersant colloid on the surface of the roughened layer and thermally curing it, evenly distributed mask cylinders or spheres are formed on the surface, and then dry etching and roughening liquid are used to form spherical islands with a pyramid velvet surface on the surface. This not only increases the roughened area, but also increases the light output angle, further improving the luminous efficiency. The resulting red light LED chip has high luminous efficiency, good reliability, and stable overall device performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 This is a schematic structural diagram of a red light LED epitaxial wafer on a GaAs substrate according to the present invention; Figure 2 This is a schematic diagram of the structure of the red LED chip of the present invention; Figure 3It is a schematic diagram of an enlarged portion of the structure of the spherical island on the surface of the red light LED chip of the present invention.

[0017] Description of the numbers in the schematic diagram: 1. GaAs substrate; 2. N-type semiconductor layer; 3. Light-emitting layer; 4. P-type semiconductor layer; 4-1. P-type waveguide layer; 4-2. P-type confinement layer; 4-3. P-type transition layer; 5. GaP window layer; 6. Dielectric film layer; 7. Au-filled barrier layer; 8. Ohmic contact layer; 9. Mirror layer; 10. Transition barrier layer; 11. In bonding layer; 12. Au bonding layer; 13. Si substrate; 14. Front electrode; 15. Roughened spherical island; 16. Passivation layer; 17. Back electrode; 18. Pyramid velvet. DETAILED DESCRIPTION

[0018] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. The following description of at least one exemplary embodiment is actually only illustrative and is by no means intended to limit the present application and its application or use. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0019] In the description of the present application, it should be understood that the use of terms such as "first" and "second" to limit components is only for the convenience of distinguishing the corresponding components. Unless otherwise stated, the above terms have no special meaning and therefore cannot be understood as limiting the scope of protection of the present application.

[0020] In the description of the present application, it should be understood that the directions or positional relationships indicated by directional words such as "front, back, up, down, left, right", "lateral, vertical, perpendicular, horizontal" and "top, bottom" are usually based on the directions or positional relationships shown in the drawings, and are only for the convenience of describing the present application and simplifying the description. Unless otherwise specified, these directional words do not indicate or imply that the device or element referred to must have a specific direction or be constructed and operated in a specific direction, and therefore cannot be understood as limiting the scope of protection of the present application; the directional words "inside and outside" refer to the inside and outside relative to the contours of each component itself.

[0021] See also Figures 1 to 3It should be noted that the diagrams provided in this embodiment are only schematic illustrations of the basic concept of the present invention, and the diagrams only show the components related to the present invention rather than the number, shape and size of the components in actual implementation. The form, quantity and proportion of each component in actual implementation may be changed at will, and the layout of the components may be more complicated. The organic solution used for cleaning is a commonly used organic solvent such as acetone and isopropyl alcohol.

[0022] Some embodiments of the present invention provide a method for manufacturing a red LED chip, comprising the following steps: S1. On a GaAs substrate, a red LED epitaxial wafer is grown using MOCVD, and an N-type semiconductor layer, a light-emitting layer, a P-type semiconductor layer, and a GaP window layer are grown in sequence; Specifically, a GaAs substrate 1 is provided as a substrate for the growth of a red light epitaxial wafer structure. A program is first set on a MOCVD machine to sequentially grow an N-type semiconductor layer 2, a light-emitting layer 3, a P-type semiconductor layer 4, and a GaP window layer 5 on the GaAs substrate 1; wherein the GaP window layer 5 is mainly a GaP layer with a thickness of 0.5 μm-1.0 μm; the P-type semiconductor layer 4 includes a P-type waveguide layer 4-1, a P-type confinement layer 4-2, and a P-type transition layer 4-3; the P-type transition layer is composed of a P-Al 40 GaInP to P-Al 20 GaInP transitions to GaP window layer 5 in sequence; the roughened layer in the N-type semiconductor layer 2 is located on the outermost surface of the N-type semiconductor layer, and its material is N-Al 60 GaInP to N-Al 20 The GaInP layer gradually transitions to the GaP window layer, with a thickness of 3μm-4μm. The use of a gradient aluminum component is mainly to ensure a gradient lattice in order to achieve the purpose of structural adaptation.

[0023] S2. On the epitaxial wafer, use photolithography and etching technology to make a patterned P-face pattern on the surface of the GaP window layer, and etch through the GaP window layer; specifically, first use an acid-base solution to clean the epitaxial wafer, and use a positive resist mask to lithography to make a patterned P-face pattern on the surface of the epitaxial wafer, and then use ICP to etch away the exposed GaP window layer, and etch down to the P-type confinement layer to stop, and finally use a photoresist remover to remove the photoresist on the surface to obtain a patterned P-face pattern, wherein the ratio of the etched area to the retained area is 3:7, which can reduce the absorption of the light emitted by the light-emitting layer by the P-type confinement layer, reduce the absorption of the mirror-reflected light to the front side by the P-type confinement layer, and improve the luminous efficiency.

[0024] S3. Depositing a dielectric film layer on the surface for the first time by PECVD; specifically, cleaning the patterned P-side pattern surface by acid, alkali or organic solution, and depositing SiO 2The dielectric film layer has a thickness of 1500±100 angstroms and can fill the concave positions after the P-surface pattern is produced to ensure the flatness of the subsequent dielectric film.

[0025] S4. Using photolithography technology, insert an Au filling barrier layer in the area corresponding to the chip cutting path by peeling; specifically, the Au filling barrier layer is produced by negative photolithography in conjunction with the lift-off process. The Au filling barrier layer is located in the cutting path area and has a size larger than the cutting path size. This can effectively protect the mirror layer during dry etching and laser cutting, thereby improving the reliability of the chip.

[0026] S5. Deposit a dielectric film layer on the surface for the second time using PECVD; specifically, further clean the surface using an acid, alkali or organic solution, such as sulfuric acid, hydrogen peroxide or acetone, isopropanol, etc., and then deposit SiO 2 The dielectric film layer has a thickness of 3500±200 angstroms. The secondary deposited dielectric film can insert an Au filling barrier layer into the dielectric film layer located in the projection area of ​​the cutting path to improve reliability.

[0027] S6. Using photolithography and etching technology, a dielectric film through hole is etched on the patterned P-face graphic step and terminated at the GaP window layer, wherein the through hole pattern is consistent with the shape of the patterned P-face graphic; specifically, using a positive resist mask, an aligned dielectric film through hole pattern is produced, the dielectric film through hole pattern is located on the patterned P-face graphic step, and the through hole pattern is consistent with the shape of the patterned P-face graphic, which can be circular, rectangular, polygonal, etc.

[0028] S7. Use a metal evaporator to thermally evaporate the ohmic contact layer; specifically, first corrode the dielectric film material with a fluorine-containing solution, and then directly evaporate the ohmic contact layer AuZn by thermal evaporation using a metal evaporator. The thickness of AuZn is 2000±10 angstroms, and the total thermal evaporation time is 10min-15min. By using direct thermal evaporation to make the ohmic contact layer alloy, the process is simpler, the time is short, the efficiency is high, the contact area with the mirror layer is increased, and the stability is good.

[0029] S8. After cleaning with an organic solution, a mirror layer, a transition barrier layer, and an In bonding layer are respectively evaporated by electron beam evaporation. Specifically, the material of the mirror layer is Ag, and the thickness is 3000±100 angstroms. The materials of the transition barrier layer are Ti / Pt / Ti / Pt / Au in sequence, and the total thickness is 10000±500 angstroms. The thickness of the In bonding layer is 3±0.5μm.

[0030] S9. Take a Si substrate and use electron beam evaporation to evaporate a layer of Au bonding layer on the surface of the Si substrate; specifically, the thickness of the Au bonding layer is 2±0.2 μm.

[0031] S10. Bond the epitaxial wafer and the Si substrate together by metal bonding, and remove the GaAs substrate by chemical etching to expose the roughened layer of the N-type semiconductor layer; specifically, the bonding temperature is 200±5°C, the pressure is 2000±10kgf, and the chemical etching solution used is a mixed solution of ammonia water and hydrogen peroxide in a volume ratio of 15:1. By adopting low temperature and low pressure for bonding, the impact on the metal mirror material and the metal layer can be reduced, thereby ensuring the luminous efficiency.

[0032] S11. The front electrode is fabricated by negative photolithography in combination with a lift-off process and then subjected to high-temperature fusion. This step can be fabricated by conventional methods.

[0033] S12. Use positive resist to make cutting path patterns, and use dry etching to etch the cutting paths until the dielectric film layer is etched. Specifically, any conventional cutting method can be used. During the cutting and etching process, the width of the cutting path is smaller than the width of the Au-filled barrier layer and passes through the Au-filled barrier layer.

[0034] S13. Spin-coating the surface of the roughened layer except the front electrode with a dispersant colloid, and using a heat curing method to make the dispersant colloid into uniformly distributed mask cylinders or spheres, and using dry etching and a roughening liquid to make the roughened layer into roughened spherical islands with a pyramid velvet surface, and finally using a cleaning machine to wash away the dispersant colloid; S14. Deposit a passivation layer on the area other than the front electrode and the surface treated in S13 by PECVD, and complete the patterning of the passivation layer by photolithography and etching; specifically, the material of the passivation layer is SiO 2 , the thickness is consistent with that of conventional red LED chips, preferably 5000 angstroms to 6000 angstroms.

[0035] S15. The LED chip manufacturing is completed by mechanically thinning the Si substrate and performing back electrode manufacturing, laser cutting, and testing. Specifically, the above chip manufacturing processes are all conventional processes.

[0036] Some specific embodiments of the present invention also provide a red light LED chip, the structural diagram of which is as follows Figure 2As shown, the red light LED chip includes from bottom to top a back electrode 17, a Si substrate 13, an Au bonding layer 12, an In bonding layer 11, a transition barrier layer 10, a mirror layer 9, a dielectric film layer 6, an ohmic contact layer 8, an Au-filled barrier layer 7, a GaP window layer 5, a P-type transition layer 4-3, a P-type confinement layer 4-2, a P-type waveguide layer 4-1, a light-emitting layer 3, an N-type semiconductor layer 2, a roughened spherical island 15, a passivation layer 16, and a front electrode 14; the Au-filled barrier layer 7 is located in the projection area of ​​the chip cutting path and is covered by the dielectric film layer 6; the surface of the ohmic contact layer 8 convex to the mirror layer is an arc surface; the surface of the roughened spherical island 15 is evenly distributed with a pyramid velvet surface 18, and the enlarged schematic diagram of this part of the structure is shown in Figure 3 shown.

[0037] In summary, the present invention is optimized from the perspective of the manufacturing method. By etching part of the GaP window layer and the P-type transition layer, not only can the lateral long-distance expansion of the current be isolated, and the current can be effectively injected into the light-emitting area, but also the absorption of the light emitted by the light-emitting layer and the light reflected by the mirror surface to the front side by the GaP window layer and the P-type transition layer is reduced, thereby greatly improving the luminous efficiency; by inserting an Au-filled barrier layer into the dielectric film layer located in the projection area of ​​the cutting path, the mirror layer can be protected and the reliability can be improved; by directly thermally evaporating the AuZn alloy, the manufacturing process is simple, the time is short, and an arc surface can be obtained, thereby increasing the contact area with the mirror layer and improving the stability; by processing the roughened layer to form a spherical island with a pyramid velvet surface on the surface, not only the roughened area is increased, but also the light output angle can be increased, thereby further improving the luminous efficiency, and the obtained red light LED chip has high overall luminous efficiency, good reliability and stable performance.

[0038] Finally, it should be emphasized that the above is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various changes and modifications. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A method for manufacturing a red LED chip, characterized in that: The following steps are involved: S1. On a GaAs substrate, a red LED epitaxial wafer is grown using MOCVD, and an N-type semiconductor layer, a light-emitting layer, a P-type semiconductor layer, and a GaP window layer are grown in sequence; S2. On the epitaxial wafer, a patterned P-face pattern is produced on the surface of the GaP window layer using photolithography and etching technology; S3. Depositing a dielectric film layer on the surface for the first time using PECVD; S4. Using photolithography technology, inserting an Au filling barrier layer in the area corresponding to the chip cutting road by stripping; S5. Depositing a dielectric film layer on the surface for the second time using PECVD; S6. Using photolithography and etching technology, a dielectric film through hole is etched on the patterned P-face pattern step and ends at the GaP window layer, wherein the through hole pattern is consistent with the shape of the patterned P-face pattern; S7. Depositing an ohmic contact layer by thermal evaporation using a metal evaporator; S8. using electron beam evaporation to deposit a mirror layer, a transition barrier layer, and an In bonding layer; S9. Take a Si substrate and deposit an Au bonding layer on the surface of the Si substrate by electron beam evaporation; S10. Bonding the epitaxial wafer and the Si substrate together by metal bonding, and removing the GaAs substrate by chemical etching to expose the roughened layer of the N-type semiconductor layer; S11. The front electrode is fabricated by negative photolithography and lift-off process; S12. Using positive resist to make cutting path patterns, and using dry etching to etch the cutting paths to the dielectric film layer; S13. Spin-coating the surface of the roughened layer except the front electrode with a dispersant colloid, and using a heat curing method to make the dispersant colloid into uniformly distributed mask cylinders or spheres, and using dry etching and a roughening liquid to make the roughened layer into roughened spherical islands with a pyramid velvet surface, and finally using a cleaning machine to wash away the dispersant colloid; S14. Depositing a passivation layer on the area other than the front electrode and the surface treated in S13 by PECVD, and completing the patterning of the passivation layer by photolithography and etching; S15. The LED core is manufactured by mechanically thinning the Si substrate and performing back electrode fabrication, laser cutting, and testing.

2. The method for manufacturing a red LED chip according to claim 1, characterized in that: In S1, the GaP window layer is a GaP layer with a thickness of 0.5 μm-1.0 μm; the P-type semiconductor layer is a P-type waveguide layer, a P-type confinement layer, and a P-type transition layer from bottom to top in the growth direction of the epitaxial wafer; the P-type transition layer is composed of P-Al 40 GaInP to P-Al 20 GaInP transitions to the GaP window layer in sequence; the roughening layer material of the N-type semiconductor layer is composed of N-Al 60 GaInP to N-Al 20 The GaInP gradually transitions toward the GaP window layer, with a thickness of 3 μm-4 μm.

3. The method for manufacturing a red LED chip according to claim 2, characterized in that: In S2, the method for making the patterned P-side graphic is: use ICP to etch away the exposed GaP window layer, and etch down to the P-type restriction layer and stop, and then use a photoresist removal solution to remove the photoresist on the surface; the ratio of the etched area to the retained area is 3:

7.

4. The method for manufacturing a red LED chip according to claim 1, characterized in that: In S3, the thickness of the dielectric film layer deposited for the first time is 1500±100 angstroms; in S5, the thickness of the dielectric film layer deposited for the second time is 3500±200 angstroms.

5. The method for manufacturing a red LED chip according to claim 1, characterized in that: In S4, the size of the Au-filled barrier layer is larger than the chip cutting street size.

6. The method for manufacturing a red LED chip according to claim 1, characterized in that: In S7, the material of the ohmic contact layer is AuZn, the thickness is 2000±10 angstroms, and the total thermal evaporation time is 10 min-15 min.

7. The method for manufacturing a red LED chip according to claim 1, characterized in that: In S8, the material of the mirror layer is Ag, and the thickness is 3000±100 angstroms; the materials of the transition barrier layer are Ti / Pt / Ti / Pt / Au in sequence, and the total thickness is 10000±500 angstroms; the thickness of the In bonding layer is 3±0.5μm; in S9, the thickness of the Au bonding layer is 2±0.2μm.

8. The method for manufacturing a red LED chip according to claim 1, characterized in that: In S10, the bonding temperature is 200±5°C, the pressure is 2000±10kgf, and the chemical etching solution used is a mixed solution of ammonia water and hydrogen peroxide in any volume ratio.

9. The method for manufacturing a red LED chip according to claim 1, characterized in that The dispersant colloid is a nano-scale resin; the thermal curing method is to first heat at 120°C for 300s and then maintain at 200°C for 30min for curing; the roughening liquid is a mixed solution of phosphoric acid, glacial acetic acid, hydrogen peroxide and water in any volume ratio.

10. A red LED chip manufactured by the manufacturing method according to any one of claims 1 to 9.

Images