RS485 communication system
The RS485 communication system addresses master-slave delays and interface limitations by expanding serial data interfaces and control signals, enhancing real-time performance and stability through a microcontroller, decoder, and latch circuit design.
Patent Information
- Application Number
- CN202411271914.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-11
- Publication Date
- 2024-12-13
AI Technical Summary
The existing RS485 communication system faces issues such as master-slave communication delay, bus performance limitations, insufficient number of interfaces, signal interference, bus contention, and data length uncertainty, which affect real-time and stability in industrial applications.
An RS485 communication system comprising a microcontroller, address decoder, serial port expansion, latch circuit, and RS485 controller, which includes a microcontroller, an address decoder, a serial port expansion, a latch circuit, and an RS485 controller, which includes a microcontroller, an address decoder, a serial port expansion circuit, a latch circuit, and an RS485 controller, to generate multiple RS485 serial data interfaces and control signals.
The system alleviates communication delays, improves real-time performance, enhances interface channels, reduces signal interference and reflection, and ensures stable communication by managing multiple devices simultaneously.
Smart Images
Figure CN119127773A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of serial communication interface implementation, and in particular to an RS485 communication system. Background Art
[0002] RS485 bus is a serial communication protocol, which is widely used in industrial automation and monitoring systems. The status and problems of the prior art can be summarized as follows:
[0003] The existing RS485 uses two lines for communication, one is a high voltage line and the other is a low voltage line. RS485 transmits data through differential voltage, which enhances the ability to resist common mode interference. Under ideal conditions, the RS485 bus can support a communication distance of 1200 meters, and the communication rate ranges from a few Kbps to 10Mbps. The RS485 bus can connect up to 128 nodes. It is suitable for use in industrial occasions with complex environments and harsh conditions.
[0004] The prior art has the following problems:
[0005] Master-slave communication mode: In half-duplex communication mode, the master-slave communication method is adopted. The slave does not actively initiate data transmission, but responds to the host's instructions. This causes delays in the communication process and affects the real-time nature of the data.
[0006] Bus performance requirements: When the number of devices mounted on the bus increases, the performance requirements of the bus increase. A common solution is to add a 485 bus HUB for data forwarding, but this will increase the complexity of the system and the probability of failure.
[0007] Serial communication interface limitation: The host has a limited number of serial communication interfaces, and it is not possible to assign an independent 485 data interface to each slave.
[0008] Impedance discontinuity problem: When multiple serial interfaces are connected in parallel, impedance discontinuity may occur, causing signal reflection and interference, which requires impedance matching to solve.
[0009] Bus contention: When multiple devices are mounted on a terminal, bus contention may occur because the devices report data at the same time, resulting in communication abnormalities.
[0010] Data length difference: Due to the different data lengths of slave responses, the time interval for the host to poll the slave is uncertain, which may affect the stability and efficiency of the system.
[0011] These problems show that although the RS485 bus has many advantages in industrial applications, there are technical problems such as master-slave communication delay, bus performance limitation, insufficient number of interfaces, signal interference, bus contention and data length uncertainty, which affect the real-time and stability of the system. Summary of the invention
[0012] To this end, the present application provides an RS485 communication system to solve technical problems existing in the prior art, such as master-slave communication delay, bus performance limitation, insufficient number of interfaces, signal interference, bus contention and data length uncertainty.
[0013] In order to achieve the above object, the present application provides an RS485 communication system, characterized in that the system comprises: a microcontroller, an address decoder circuit, a serial port expansion circuit, a latch circuit and an RS485 controller;
[0014] The address decoder circuit includes a first decoder, a second decoder and a third decoder; the input end of the first decoder is connected to the microcontroller through a first address bus, and the first decoder is used to generate a write signal of the serial port expansion circuit; the input end of the second decoder is connected to the microcontroller through a second address bus, and the second decoder is used to generate a read signal of the serial port expansion circuit; the output end of the first decoder and the output end of the second decoder are respectively connected to the input end of the gate circuit, and the output end of the AND gate circuit is connected to the chip select signal input end of the serial port expansion circuit;
[0015] The first data interface of the serial port expansion circuit is connected to the microcontroller via a first data bus, the second data interface of the serial port expansion circuit is connected to the microcontroller via a second data bus, the read-write control input end of the serial port expansion circuit is connected to the microcontroller, and the microcontroller sends a read-write control signal to the serial port expansion circuit; the serial port expansion circuit is used to generate a multi-channel RS485 serial data interface;
[0016] The input end of the third decoder is connected to the microcontroller through a third address bus, the output end of the third decoder is connected to the latch circuit, and the third decoder is used to generate a chip select signal of the latch circuit;
[0017] The latch circuit is also connected to the microcontroller via a third data bus, and the latch circuit is used to generate multiple RS485 transceiver control signals;
[0018] The RS485 controller generates multiple RS485 communication interfaces based on multiple RS485 serial data interfaces and multiple RS485 transceiver control signals.
[0019] In the above solution, optionally, the first decoder is a 74HC138 decoder;
[0020] The MCU_A16, MCU_A17, MCU_A18, MCU_A23, and nWE signals of the address bus of the microcontroller are respectively connected to B_A16, B_A17, B_A18, B_A23, and B_WE of the first decoder. The first decoder is used to generate five write signals CH438_W_CS1, CH438_W_CS2, CH438_W_CS3, CH438_W_CS4, and CH438_W_CS5 of the serial port expansion circuit based on the MCU_A16, MCU_A17, MCU_A18, MCU_A23, and nWE signals.
[0021] In the above solution, optionally, the second decoder is a 74HC138 decoder;
[0022] The MCU_A16, MCU_A17, MCU_A18, MCU_A20, and nOE signals of the address bus of the microcontroller are respectively connected to B_A16, B_A17, B_A18, B_A20, and B_OE of the second decoder. The second decoder is used to generate five read signals CH438_R_CS1, CH438_R_CS2, CH438_R_CS3, CH438_R_CS4, and CH438_R_CS5 of the serial port expansion circuit based on the MCU_A16, MCU_A17, MCU_A18, MCU_A20, and nOE signals.
[0023] In the above solution, optionally, the AND gate circuit includes five AND gate modules;
[0024] The CH438_W_CS1, the CH438_W_CS2, the CH438_W_CS3, the CH438_W_CS4 and the CH438_W_CS5 are respectively connected to the first input ends of the five AND gate modules, the CH438_R_CS1, the CH438_R_CS2, the CH438_R_CS3, the CH438_R_CS4 and the CH438_R_CS5 are respectively connected to the second input ends of the five AND gate modules, and the output ends of the five AND gate modules are respectively connected to the input end of the serial port expansion circuit;
[0025] Among them, the output ends of the five AND gate modules respectively output five chip selection signals CH438_CS1, CH438_CS2, CH438_CS3, CH438_CS4 and CH438_CS5.
[0026] In the above solution, optionally, the serial port expansion circuit includes a first serial port expansion chip, a second serial port expansion chip, a third serial port expansion chip, a fourth serial port expansion chip and a fifth serial port expansion chip;
[0027] The first serial port expansion chip, the second serial port expansion chip, the third serial port expansion chip, the fourth serial port expansion chip and the fifth serial port expansion chip are all CH438Q serial port expansion chips.
[0028] In the above scheme, optionally, the CH438_CS1, the CH438_CS2, the CH438_CS3, the CH438_CS4, and the CH438_CS5 are respectively connected to the chip select pins of the first serial port expansion chip, the second serial port expansion chip, the third serial port expansion chip, the fourth serial port expansion chip, and the fifth serial port expansion chip;
[0029] The data interfaces B_D0 to B_D7 of the first serial port expansion chip, the second serial port expansion chip, the third serial port expansion chip, the fourth serial port expansion chip, and the fifth serial port expansion chip are respectively connected to the data buses MCU_D0 to MCU_D7 of the microcontroller;
[0030] The data interfaces B_A0 to B_A6 of the first serial port expansion chip, the second serial port expansion chip, the third serial port expansion chip, the fourth serial port expansion chip, and the fifth serial port expansion chip are respectively connected to the data buses MCU_A1 to MCU_A7 of the microcontroller;
[0031] The B_OE pins of the first serial port expansion chip, the second serial port expansion chip, the third serial port expansion chip, the fourth serial port expansion chip, and the fifth serial port expansion chip are respectively connected to the nOE pin of the microcontroller;
[0032] The B_WE pins of the first serial port expansion chip, the second serial port expansion chip, the third serial port expansion chip, the fourth serial port expansion chip, and the fifth serial port expansion chip are respectively connected to the nWE pin of the microcontroller.
[0033] In the above solution, optionally, the third decoder is a 74HC138 decoder;
[0034] The MCU_A16, MCU_A17, MCU_A18, MCU_A20, and nWE signals of the address bus of the microcontroller are respectively connected to B_A16, B_A17, B_A18, B_A20, and B_WE of the third decoder. The third decoder is used to generate five write chip select signals EX_W_CS1, EX_W_CS2, EX_W_CS3, EX_W_CS4, and EX_W_CS5 of the latch circuit based on the MCU_A16, MCU_A17, MCU_A18, MCU_A20, and nWE signals.
[0035] In the above solution, optionally, the latch circuit includes a first latch, a second latch, a third latch, a fourth latch and a fifth latch;
[0036] The first latch, the second latch, the third latch, the fourth latch and the fifth latch are all 74HC574 latches.
[0037] In the above scheme, optionally, B_D0 to B_D7 of the first latch, the second latch, the third latch, the fourth latch and the fifth latch are respectively connected to the data buses MCU_D0 to MCU_D7 of the microcontroller; the CLK pins of the first latch, the second latch, the third latch, the fourth latch and the fifth latch are respectively connected to the EX_W_CS1, the EX_W_CS2, the EX_W_CS3, the EX_W_CS4 and the EX_W_CS5.
[0038] Compared with the prior art, this application has at least the following beneficial effects:
[0039] Based on further analysis and research of the existing technical problems, this application recognizes that there are technical problems such as master-slave communication delay, bus performance limitation, insufficient number of interfaces, signal interference, bus contention and data length uncertainty. This application provides a structure of an RS485 communication system, including a microcontroller, an address decoder circuit, a serial port expansion circuit, a latch circuit and an RS485 controller. The system generates write signals and read signals through a decoder, generates multiple RS485 serial data interfaces through a serial port expansion circuit, and generates multiple RS485 transceiver control signals using a latch circuit.
[0040] The present application, by expanding multiple RS485 serial data interfaces and control signals, can alleviate the delay problem caused by the traditional master-slave communication mode, improve the real-time performance of data and the system response speed. The present system designs a serial port expansion circuit and a decoder circuit, which can support more communication interface channels, can reduce the equipment load on a single bus, and thus improve the performance and stability of the system. The present application, through the design of the serial port expansion circuit, can generate multiple RS485 serial data interfaces, break through the limit of the number of host serial port communication interfaces, and enhance the expansibility of the system. The latch circuit and the multi-channel RS485 transceiver control signal in the system can effectively manage and control the serial interface, reduce the problem of impedance discontinuity and signal reflection. Through the generation and management of the multi-channel RS485 transceiver control signal, the bus contention phenomenon caused by multiple devices reporting data at the same time can be avoided, and the stability and reliability of communication can be improved. The design of the system allows multiple RS485 communication interfaces to work in parallel, reducing the uncertainty of the host polling access to the slave, and improving the certainty and real-time performance of the overall communication. BRIEF DESCRIPTION OF THE DRAWINGS
[0041] In order to more intuitively illustrate the prior art and the present application, exemplary drawings are given below. It should be understood that the specific shapes and structures shown in the drawings should not generally be regarded as limiting conditions for implementing the present application; for example, those skilled in the art are capable of easily making conventional adjustments or further optimizations to the addition / reduction / attribution division, specific shapes, positional relationships, connection methods, dimensional ratios, etc. of certain units (components) based on the technical concepts and exemplary drawings disclosed in the present application.
[0042] Figure 1 A circuit block diagram of an RS485 communication system provided in an embodiment of the present application;
[0043] Figure 2 A circuit schematic diagram of a data bus of a microcontroller provided in an embodiment of the present application;
[0044] Figure 3 A circuit schematic diagram of an address bus of a microcontroller provided in an embodiment of the present application;
[0045] Figure 4 A circuit schematic diagram of a first decoder provided in an embodiment of the present application;
[0046] Figure 5 A circuit schematic diagram of a second decoder provided in an embodiment of the present application;
[0047] Figure 6 A circuit schematic diagram of a latch circuit provided in an embodiment of the present application;
[0048] Figure 7A circuit schematic diagram of a third decoder provided in an embodiment of the present application;
[0049] Figure 8 A circuit schematic diagram of an AND gate circuit provided in an embodiment of the present application;
[0050] Fig. 9 A circuit schematic diagram of a serial port expansion circuit provided in an embodiment of the present application. DETAILED DESCRIPTION
[0051] The present application is further described below in detail through specific embodiments in conjunction with the accompanying drawings.
[0052] In the description of this application: unless otherwise specified, the meaning of "plurality" is two or more. The terms "first", "second", "third", etc. in this application are intended to distinguish the objects referred to, and do not have special meanings in terms of technical connotations (for example, they should not be understood as emphasizing the importance or order, etc.). Expressions such as "including", "comprising", "having", etc. also mean "not limited to" (certain units, components, materials, steps, etc.).
[0053] In one embodiment, Figure 1 As shown, this embodiment provides an RS485 communication system, the system comprising: a microcontroller, an address decoder circuit, a serial port expansion circuit, a latch circuit and an RS485 controller;
[0054] The address decoder circuit includes a first decoder, a second decoder and a third decoder; the input end of the first decoder is connected to the microcontroller through a first address bus, and the first decoder is used to generate a write signal of the serial port expansion circuit; the input end of the second decoder is connected to the microcontroller through a second address bus, and the second decoder is used to generate a read signal of the serial port expansion circuit; the output end of the first decoder and the output end of the second decoder are respectively connected to the input end of the gate circuit, and the output end of the AND gate circuit is connected to the chip select signal input end of the serial port expansion circuit;
[0055] The first data interface of the serial port expansion circuit is connected to the microcontroller via a first data bus, the second data interface of the serial port expansion circuit is connected to the microcontroller via a second data bus, the read-write control input end of the serial port expansion circuit is connected to the microcontroller, and the microcontroller sends a read-write control signal to the serial port expansion circuit; the serial port expansion circuit is used to generate a multi-channel RS485 serial data interface;
[0056] The input end of the third decoder is connected to the microcontroller through a third address bus, the output end of the third decoder is connected to the latch circuit, and the third decoder is used to generate a chip select signal of the latch circuit;
[0057] The latch circuit is also connected to the microcontroller via a third data bus, and the latch circuit is used to generate multiple RS485 transceiver control signals;
[0058] The RS485 controller generates multiple RS485 communication interfaces based on multiple RS485 serial data interfaces and multiple RS485 transceiver control signals.
[0059] In this embodiment, the first decoder is a 74HC138 decoder;
[0060] The MCU_A16, MCU_A17, MCU_A18, MCU_A23, and nWE signals of the address bus of the microcontroller are respectively connected to B_A16, B_A17, B_A18, B_A23, and B_WE of the first decoder. The first decoder is used to generate five write signals CH438_W_CS1, CH438_W_CS2, CH438_W_CS3, CH438_W_CS4, and CH438_W_CS5 of the serial port expansion circuit based on the MCU_A16, MCU_A17, MCU_A18, MCU_A23, and nWE signals.
[0061] In this embodiment, the second decoder is a 74HC138 decoder;
[0062] The MCU_A16, MCU_A17, MCU_A18, MCU_A20, and nOE signals of the address bus of the microcontroller are respectively connected to B_A16, B_A17, B_A18, B_A20, and B_OE of the second decoder. The second decoder is used to generate five read signals CH438_R_CS1, CH438_R_CS2, CH438_R_CS3, CH438_R_CS4, and CH438_R_CS5 of the serial port expansion circuit based on the MCU_A16, MCU_A17, MCU_A18, MCU_A20, and nOE signals.
[0063] In this embodiment, the AND gate circuit includes five AND gate modules;
[0064] The CH438_W_CS1, the CH438_W_CS2, the CH438_W_CS3, the CH438_W_CS4 and the CH438_W_CS5 are respectively connected to the first input ends of the five AND gate modules, the CH438_R_CS1, the CH438_R_CS2, the CH438_R_CS3, the CH438_R_CS4 and the CH438_R_CS5 are respectively connected to the second input ends of the five AND gate modules, and the output ends of the five AND gate modules are respectively connected to the input end of the serial port expansion circuit;
[0065] Among them, the output ends of the five AND gate modules respectively output five chip selection signals CH438_CS1, CH438_CS2, CH438_CS3, CH438_CS4 and CH438_CS5.
[0066] In this embodiment, the serial port expansion circuit includes a first serial port expansion chip, a second serial port expansion chip, a third serial port expansion chip, a fourth serial port expansion chip and a fifth serial port expansion chip;
[0067] The first serial port expansion chip, the second serial port expansion chip, the third serial port expansion chip, the fourth serial port expansion chip and the fifth serial port expansion chip are all CH438Q serial port expansion chips.
[0068] In this embodiment, the CH438_CS1, the CH438_CS2, the CH438_CS3, the CH438_CS4, and the CH438_CS5 are respectively connected to the chip select pins of the first serial port expansion chip, the second serial port expansion chip, the third serial port expansion chip, the fourth serial port expansion chip, and the fifth serial port expansion chip;
[0069] The data interfaces B_D0 to B_D7 of the first serial port expansion chip, the second serial port expansion chip, the third serial port expansion chip, the fourth serial port expansion chip, and the fifth serial port expansion chip are respectively connected to the data buses MCU_D0 to MCU_D7 of the microcontroller;
[0070] The data interfaces B_A0 to B_A6 of the first serial port expansion chip, the second serial port expansion chip, the third serial port expansion chip, the fourth serial port expansion chip, and the fifth serial port expansion chip are respectively connected to the data buses MCU_A1 to MCU_A7 of the microcontroller;
[0071] The B_OE pins of the first serial port expansion chip, the second serial port expansion chip, the third serial port expansion chip, the fourth serial port expansion chip, and the fifth serial port expansion chip are respectively connected to the nOE pin of the microcontroller;
[0072] The B_WE pins of the first serial port expansion chip, the second serial port expansion chip, the third serial port expansion chip, the fourth serial port expansion chip, and the fifth serial port expansion chip are respectively connected to the nWE pin of the microcontroller.
[0073] In this embodiment, the third decoder is a 74HC138 decoder;
[0074] The MCU_A16, MCU_A17, MCU_A18, MCU_A20, and nWE signals of the address bus of the microcontroller are respectively connected to B_A16, B_A17, B_A18, B_A20, and B_WE of the third decoder. The third decoder is used to generate five write chip select signals EX_W_CS1, EX_W_CS2, EX_W_CS3, EX_W_CS4, and EX_W_CS5 of the latch circuit based on the MCU_A16, MCU_A17, MCU_A18, MCU_A20, and nWE signals.
[0075] In this embodiment, the latch circuit includes a first latch, a second latch, a third latch, a fourth latch and a fifth latch;
[0076] The first latch, the second latch, the third latch, the fourth latch and the fifth latch are all 74HC574 latches.
[0077] In this embodiment, B_D0 to B_D7 of the first latch, the second latch, the third latch, the fourth latch and the fifth latch are respectively connected to the data buses MCU_D0 to MCU_D7 of the microcontroller; the CLK pins of the first latch, the second latch, the third latch, the fourth latch and the fifth latch are respectively connected to the EX_W_CS1, the EX_W_CS2, the EX_W_CS3, the EX_W_CS4 and the EX_W_CS5.
[0078] The present embodiment, by expanding multiple RS485 serial data interfaces and control signals, can alleviate the delay problem caused by the traditional master-slave communication mode, improve the real-time performance of data and the system response speed. The system has designed a serial port expansion circuit and a decoder circuit, which can support more communication interface channels, can reduce the equipment load on a single bus, and thus improve the performance and stability of the system. The present application is designed through the serial port expansion circuit, and the system can generate multiple RS485 serial data interfaces, break through the limitation of the number of host serial port communication interfaces, and enhance the expansibility of the system. The latch circuit and the multiple RS485 transceiver control signal in the system can effectively manage and control the serial interface, reduce the problem of impedance discontinuity and signal reflection. Through the generation and management of the multiple RS485 transceiver control signal, the bus contention phenomenon caused by the simultaneous reporting of data by multiple devices can be avoided, and the stability and reliability of communication can be improved. The design of the system allows multiple RS485 communication interfaces to work in parallel, reduces the uncertainty of the host polling access to the slave, and improves the certainty and real-time performance of the overall communication.
[0079] In one embodiment, an RS485 communication system is provided, the system comprising: an MCU microcontroller, an address decoder circuit, a latch circuit, a serial port expansion circuit, an RS485 interface circuit, and a voltage conversion circuit.
[0080] MCU microcontroller: It uses a high-performance 32-bit ARM microprocessor. It uses the on-chip FSMC (static memory controller) bus interface, which can be connected to the pins of SRAM, ROM, NorFLASH and other memories, so that data can be easily exchanged and transmitted. It is the main controller for core algorithms, action control signal output and other functions;
[0081] Address decoder: It is implemented by 74HC138 chip, which has the characteristics of high speed, low power consumption, low noise, etc., and is suitable for various digital circuit designs. The three address encoding signals and the enable signal are used together to control the 8-way output signal to be all high level or only one of the 8-way output signal is low level. The extended chip select signal and read-write signal are realized in the circuit.
[0082] Latch circuit: It is implemented by 74HC574 chip, which is an 8-bit high-speed CMOS integrated circuit with three-state in-phase D flip-flop output, rising edge triggered. In this circuit, the chip select signal output and the serial port circuit's receiving and sending control signal are realized.
[0083] Serial port expansion circuit: It is implemented using the CH438Q chip. The CH438 is an 8-channel UART chip that contains eight asynchronous serial interfaces and supports a communication baud rate of up to 4Mbps. It has an 8-bit data bus and a 7-bit address bus. The parallel data bus enables fast data writing and reading, and is a key chip for expanding 40-channel serial circuits. Power supply unit: It provides a stable power supply for the MCU and each control unit. The voltage level and power are also different, so various voltage conversions are required. This solution uses a high-efficiency power conversion chip with a wide power supply voltage input range of 12 volts to 40 volts.
[0084] Compared with the existing technology, the system of this embodiment has the following advantages:
[0085] Each RS485 channel corresponds to a slave device, and the communication protocol is simple and easy to implement.
[0086] The communication is highly real-time and the system response speed is increased by several to dozens of times.
[0087] The number of slave nodes on the bus is reduced, reducing bus interference and signal reflection.
[0088] Applicable to devices with different communication protocols.
[0089] Each serial interface can be configured as active or passive mode at will.
[0090] The serial expansion chip has a built-in data buffer, which reduces the performance requirements for the MCU.
[0091] It is especially suitable for applications with high speed response requirements.
[0092] The key technology of this embodiment lies in the expansion of the serial bus transceiver, the switching of the transceiver status of each serial communication channel, the reading and sending of data, and the latching of the transceiver control signal.
[0093] like Figure 2-9 As shown, the system circuit is mainly composed of 1 STM32F103 microcontroller, 3 74HC138, 5 74HC574, 5 CH438 and 40 MAX485 chips and auxiliary circuits such as power supply.
[0094] The microcontroller uses the FSMC bus mode, address bus, data bus, read and write signals, chip select and other signals to output in a specific timing to achieve the purpose of data transmission and reading. It is the main control chip of this system.
[0095] The high-order address bus and write signal of the microcontroller are connected to 74HC138, which can be expanded to generate 8 channels of write enable signals. Only 5 channels are used here. The signal is marked as CH438_W_CSx, and then the write signals of these 5 channels are connected to the write enable pins of the serial data interface expansion chip respectively.
[0096] The high-order address bus and read signal of the microcontroller are connected to 74HC138, which can be expanded to generate 8 channels of read enable signals. Only 5 channels are used here. The signal is marked as CH438_R_CSx, and then the read signals of these 5 channels are connected to the read enable signal terminals of the serial data interface expansion chip.
[0097] The microcontroller's data bus and write signal are connected to the 74HC138 expansion to generate 8 channels of write enable signals. Only 5 of the channels are used here. The signal is marked as EX_W_CSx, which is connected to the latch enable control pin of the latch.
[0098] RS485 transceiver control latch 74HC574 is implemented. The MCU's data bus and EX_W_CSx signal are connected to the input and latch signal input of 74HC574 respectively. The rising edge of EX_W_CSx signal is used to latch the data to the output of 74HC574, and the output can control the RS485 transceiver function.
[0099] The address bus of CH438 is connected to the low-order address bus of MCU, and the data bus is connected to the low-order data bus of MCU.
[0100] When writing data to CH438, the MCU first outputs the address bus signal to enable the write input and chip select signal of CH438 as well as the register address. Then the MCU sends the data to the data bus, and CH438 can obtain the data on the bus, thereby realizing the control data or sending the data to the TXD pin of the serial data interface to realize the transmission of serial data.
[0101] When the serial interface expansion chip CH438 receives the data from the bus, it will generate an interrupt signal to notify the microcontroller. After receiving the interrupt signal, the microcontroller triggers the reading, thereby obtaining the data on the RS485 bus, and then performs further data processing and analysis.
[0102] Circuit connection description of this embodiment: MCU's data bus MCU_D0~D7 is connected to CH438's data interface B_D0~D7 to form a data bus connection; MCU's data bus MCU_A1~A7 is connected to CH438's data interface B_A0~A6 to form an address bus connection; MCU_A16~A18, MCU_A23 and nWE signals of the MCU address bus are respectively connected to B_A16~18, B_A23 and B_WE of the U35 chip, and 5 CH438 write signals CH438_W_CS1~5 are generated through these signals. In the same way, MCU_A16~A18, MCU_A20 and nOE signals of the MCU address bus are respectively connected to B_A16~18, B_A20 and B_OE of the U34 chip, and 5 CH438 read signals CH438_R_CS1~5 are generated through these signals. Connect CH438_W_CS1~5 and CH438_R_CS1~5 to the input of the AND gate circuit of U39 respectively, and connect the output of the AND gate CH438_CS1~5 to the chip select pin Pin43 of 5 CH438s respectively, as the chip select signal of CH438; the read and write signals nOE and nWE of MCU are connected to B_OE and B_WE of 5 CH438s respectively, as the read and write control signals of CH438; the 5 CH438 serial port expansion chips are connected to the data summary, address bus, read and write control signal chip select signal respectively, and 40 serial data interfaces can be expanded through these 5 CH438s;
[0103] RS485 transceiver control signal circuit: MCU_A16~A18, MCU_A20 and nWE signals of the MCU address bus are connected to B_A16~18, B_A20 and B_WE of the U33 chip respectively. These signals generate 5 extended write chip select signals EX_W_CS1~5. The MCU data bus MCU_D0~D7 is connected to B_D0~D7 of 5 latches (74HC574). EX_W_CS1~5 is connected to the CLK pin (Pin11) of 5 latches (74HC574) respectively. These 5 latches can generate 40 485 transceiver control signals.
[0104] The technical features of the above embodiments may be arbitrarily combined (as long as there is no contradiction in the combination of these technical features). To make the description concise, not all possible combinations of the technical features in the above embodiments are described; these embodiments that are not explicitly written should also be considered to be within the scope of this specification.
Claims
1. An RS485 communication system, characterized in that: The system comprises: a microcontroller, an address decoder circuit, a serial port expansion circuit, a latch circuit and an RS485 controller; The address decoder circuit includes a first decoder, a second decoder and a third decoder; the input end of the first decoder is connected to the microcontroller through a first address bus, and the first decoder is used to generate a write signal of the serial port expansion circuit; the input end of the second decoder is connected to the microcontroller through a second address bus, and the second decoder is used to generate a read signal of the serial port expansion circuit; the output end of the first decoder and the output end of the second decoder are respectively connected to the input end of the gate circuit, and the output end of the AND gate circuit is connected to the chip select signal input end of the serial port expansion circuit; The first data interface of the serial port expansion circuit is connected to the microcontroller via a first data bus, the second data interface of the serial port expansion circuit is connected to the microcontroller via a second data bus, the read-write control input end of the serial port expansion circuit is connected to the microcontroller, and the microcontroller sends a read-write control signal to the serial port expansion circuit; the serial port expansion circuit is used to generate a multi-channel RS485 serial data interface; The input end of the third decoder is connected to the microcontroller through a third address bus, the output end of the third decoder is connected to the latch circuit, and the third decoder is used to generate a chip select signal of the latch circuit; The latch circuit is also connected to the microcontroller via a third data bus, and the latch circuit is used to generate multiple RS485 transceiver control signals; The RS485 controller generates multiple RS485 communication interfaces based on multiple RS485 serial data interfaces and multiple RS485 transceiver control signals.
2. The system according to claim 1, characterized in that The first decoder is a 74HC138 decoder; The MCU_A16, MCU_A17, MCU_A18, MCU_A23, and nWE signals of the address bus of the microcontroller are respectively connected to B_A16, B_A17, B_A18, B_A23, and B_WE of the first decoder. The first decoder is used to generate five write signals CH438_W_CS1, CH438_W_CS2, CH438_W_CS3, CH438_W_CS4, and CH438_W_CS5 of the serial port expansion circuit based on the MCU_A16, MCU_A17, MCU_A18, MCU_A23, and nWE signals.
3. The system according to claim 2, characterized in that The second decoder is a 74HC138 decoder; The MCU_A16, MCU_A17, MCU_A18, MCU_A20, and nOE signals of the address bus of the microcontroller are respectively connected to B_A16, B_A17, B_A18, B_A20, and B_OE of the second decoder. The second decoder is used to generate five read signals CH438_R_CS1, CH438_R_CS2, CH438_R_CS3, CH438_R_CS4, and CH438_R_CS5 of the serial port expansion circuit based on the MCU_A16, MCU_A17, MCU_A18, MCU_A20, and nOE signals.
4. The system according to claim 3, characterized in that The AND gate circuit includes five AND gate modules; The CH438_W_CS1, the CH438_W_CS2, the CH438_W_CS3, the CH438_W_CS4 and the CH438_W_CS5 are respectively connected to the first input ends of the five AND gate modules, the CH438_R_CS1, the CH438_R_CS2, the CH438_R_CS3, the CH438_R_CS4 and the CH438_R_CS5 are respectively connected to the second input ends of the five AND gate modules, and the output ends of the five AND gate modules are respectively connected to the input end of the serial port expansion circuit; Among them, the output ends of the five AND gate modules respectively output five chip selection signals CH438_CS1, CH438_CS2, CH438_CS3, CH438_CS4 and CH438_CS5.
5. The system according to claim 4, characterized in that The serial port expansion circuit includes a first serial port expansion chip, a second serial port expansion chip, a third serial port expansion chip, a fourth serial port expansion chip and a fifth serial port expansion chip; The first serial port expansion chip, the second serial port expansion chip, the third serial port expansion chip, the fourth serial port expansion chip and the fifth serial port expansion chip are all CH438Q serial port expansion chips.
6. The system according to claim 5, characterized in that The CH438_CS1, the CH438_CS2, the CH438_CS3, the CH438_CS4, and the CH438_CS5 are respectively connected to the chip select pins of the first serial port expansion chip, the second serial port expansion chip, the third serial port expansion chip, the fourth serial port expansion chip, and the fifth serial port expansion chip; The data interfaces B_D0 to B_D7 of the first serial port expansion chip, the second serial port expansion chip, the third serial port expansion chip, the fourth serial port expansion chip, and the fifth serial port expansion chip are respectively connected to the data buses MCU_D0 to MCU_D7 of the microcontroller; The data interfaces B_A0 to B_A6 of the first serial port expansion chip, the second serial port expansion chip, the third serial port expansion chip, the fourth serial port expansion chip, and the fifth serial port expansion chip are respectively connected to the data buses MCU_A1 to MCU_A7 of the microcontroller; The B_OE pins of the first serial port expansion chip, the second serial port expansion chip, the third serial port expansion chip, the fourth serial port expansion chip, and the fifth serial port expansion chip are respectively connected to the nOE pin of the microcontroller; The B_WE pins of the first serial port expansion chip, the second serial port expansion chip, the third serial port expansion chip, the fourth serial port expansion chip, and the fifth serial port expansion chip are respectively connected to the nWE pin of the microcontroller.
7. The system according to claim 1, characterized in that The third decoder is a 74HC138 decoder; The MCU_A16, MCU_A17, MCU_A18, MCU_A20, and nWE signals of the address bus of the microcontroller are respectively connected to B_A16, B_A17, B_A18, B_A20, and B_WE of the third decoder. The third decoder is used to generate five write chip select signals EX_W_CS1, EX_W_CS2, EX_W_CS3, EX_W_CS4, and EX_W_CS5 of the latch circuit based on the MCU_A16, MCU_A17, MCU_A18, MCU_A20, and nWE signals.
8. The system according to claim 7, characterized in that The latch circuit comprises a first latch, a second latch, a third latch, a fourth latch and a fifth latch; The first latch, the second latch, the third latch, the fourth latch and the fifth latch are all 74HC574 latches.
9. The system according to claim 8, characterized in that B_D0 to B_D7 of the first latch, the second latch, the third latch, the fourth latch and the fifth latch are respectively connected to the data buses MCU_D0 to MCU_D7 of the microcontroller; the CLK pins of the first latch, the second latch, the third latch, the fourth latch and the fifth latch are respectively connected to the EX_W_CS1, the EX_W_CS2, the EX_W_CS3, the EX_W_CS4 and the EX_W_CS5.