Manufacturing method of electron source and electron beam direct writing machine

Abstract

The invention provides a manufacturing method of an electron source and an electron beam direct writing machine. The manufacturing method of the electron source comprises the following steps: forming a porous structure on a first main surface of an electron source substrate; forming a back electrode on the second main surface of the electron source substrate by using a first hard mask; forming an emitter electrode on the porous structure with a second hard mask; and forming an extraction electrode of the emission electrode with a third hard mask on the first main surface of the electron source substrate, in which at least one of the second hard mask and the third hard mask is made of a silicon material. According to the invention, a relatively fine electrode pattern can be obtained, a shadow effect is avoided, liquid can be prevented from entering pores of the porous silicon in an electrode forming process, and the stability and the service life of an electron source are improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a method for manufacturing an electron source and an electron beam direct writer. Background Art

[0002] High-performance electron sources are widely used in electron beam direct writing technology, flat panel displays, and X-ray sources.

[0003] The matrixization and high performance of electron sources are the requirements of many high-end applications. The electron source disclosed in reference 1 (reference 1: Japanese Journal of Applied Physics 61, SD0807 (2022), https: / / doi.org / 10.35848 / 1347-4065 / ac4ce1) is an array-type electron source that is conducive to miniaturization and high performance. The key technology of this array-type electron source is: growing a columnar polycrystalline silicon film with a high resistance on a low-resistance silicon substrate, forming a porous silicon structure on the polycrystalline silicon film by etching, and forming nanowires composed of nanosilicon grains in the pores of the porous silicon structure. When an appropriate voltage is applied between the silicon substrate and the porous silicon structure, the electrons will be accelerated to a certain energy through the nanowires, so that the electrons are emitted from the surface of the device into the atmosphere or vacuum. Reference 2 (Reference 2: Nobuyoshi Koshida, "Device Applications of Silicon Nanocrystals and Nanostructures," ISBN: 978-0-387-78688-9, e-ISBN: 978-0-387-78689-6, DOI: 10.1007 / 978-0-387-78689-6, Springer Science+Business Media, LLC 2009) discloses a technique for preparing such an electron source by forming a porous silicon structure on a columnar polycrystalline silicon film using a photoelectrochemical etching method.

[0004] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because they are described in the background technology section of the present application. Summary of the invention

[0005] The inventors have found that the existing methods for manufacturing electron sources have some limitations. For example, in the manufacturing process of the above-mentioned electron source device, if a wet process is used after the porous silicon structure is formed, chemicals or water will enter the pores of the porous silicon; and because the pores of porous silicon are mostly in the nanometer to micrometer order, and the depth is more than several hundred nanometers, the liquid that enters the pores is not easy to be cleaned. These residual liquids, especially chemicals that are corrosive to porous silicon, will affect the stability and life of the electron source. The above-mentioned wet process includes a photolithography process and a degumming process, because liquid photoresist and developer are used in the photolithography process, and liquid chemicals are also used in the degumming process to remove the photoresist. On the other hand, in order to avoid the use of photolithography in the electrode manufacturing process, a metal hard mask (also called a metal hard mask) can be used to define the pattern of the electrode. However, the thickness of the metal hard mask is difficult to make thin, and is generally thicker than 50 microns. The thick hard mask is not only not easy to make fine patterns, but also produces a large shadow effect when used, making it difficult to control the thickness and size of the electrode. Therefore, a thick hard mask not only makes it difficult to obtain a relatively fine electrode pattern, but also affects the characteristics of the device.

[0006] In order to solve the above-mentioned problems or at least similar problems, the embodiments of the present application provide a method for manufacturing an electron source and an electron beam direct writer. In the method for manufacturing the electron source, after forming a porous silicon structure, a silicon hard mask is used to pattern the electrode. Since the silicon hard mask can be prepared by a semiconductor etching method, the silicon hard mask can be obtained with sufficiently high processing accuracy, and a hard mask with a relatively small thickness (for example, less than 50 microns) can be obtained. In this way, a relatively fine electrode pattern can be obtained to avoid the shadow effect, and liquid can be prevented from entering the pores of the porous silicon during the electrode formation process, which is beneficial to improving the stability and life of the electron source.

[0007] According to one aspect of an embodiment of the present application, a method for manufacturing an electron source is provided, the method comprising:

[0008] forming a porous structure on a first main surface of the electron source substrate;

[0009] forming a back electrode on the second main surface of the electron source substrate using a first hard mask;

[0010] forming an emitter electrode on the porous structure using a second hard mask; and

[0011] An extraction electrode of the emission electrode is formed on the first main surface of the electron source substrate using a third hard mask, wherein at least one of the second hard mask and the third hard mask is made of a silicon material.

[0012] According to another aspect of an embodiment of the present application, an electron beam direct writer is provided, wherein the electron beam direct writer comprises an electron source, and the electron source is manufactured by the method for manufacturing the electron source described in the above embodiment.

[0013] The beneficial effect of the present application is that in the manufacturing method of the electron source, after the porous silicon structure is formed, the electrode is patterned using a silicon hard mask. Since the silicon hard mask can be prepared using a semiconductor etching method, the silicon hard mask can be obtained with sufficiently high processing accuracy, and a hard mask with a relatively small thickness (for example, less than 50 microns) can be obtained. In this way, a relatively fine electrode pattern can be obtained to avoid the shadow effect, and liquid can be prevented from entering the pores of the porous silicon during the electrode formation process, which is beneficial to improving the stability and life of the electron source.

[0014] With reference to the following description and accompanying drawings, the specific embodiments of the present application are disclosed in detail, indicating the way in which the principles of the present application can be adopted. It should be understood that the embodiments of the present application are not limited in scope. Within the scope of the spirit and clauses of the appended claims, the embodiments of the present application include many changes, modifications and equivalents.

[0015] Features described and / or illustrated with respect to one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.

[0016] It should be emphasized that the term “include / comprises” when used herein refers to the presence of features, integers, steps or components, but does not exclude the presence or addition of one or more other features, integers, steps or components. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The included drawings are used to provide a further understanding of the embodiments of the present application, which constitute a part of the specification, are used to illustrate the implementation methods of the present application, and together with the text description, explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. In the drawings:

[0018] Figure 1 It is a schematic diagram of a method for manufacturing an electron source;

[0019] Figure 2 yes Figure 1 Enlarged view of the F1 part;

[0020] Figure 3 yes Figure 1 A magnified view of the F2 part;

[0021] Figure 4 is a schematic diagram of a method for manufacturing an electron source back electrode;

[0022] Figure 5 It is a schematic diagram of a method for manufacturing an electron source emission electrode;

[0023] Figure 6 It is a schematic diagram of a method for manufacturing an extraction electrode of an electron source emission electrode;

[0024] Figure 7 is a schematic diagram of a second silicon hard mask manufacturing method;

[0025] Figure 8 It is a schematic diagram of a method for manufacturing an electron source according to an embodiment of the present application. DETAILED DESCRIPTION

[0026] With reference to the accompanying drawings, the above and other features of the present application will become apparent through the following description. In the description and the accompanying drawings, specific embodiments of the present application are specifically disclosed, which show some embodiments in which the principles of the present application can be adopted. It should be understood that the present application is not limited to the described embodiments. On the contrary, the present application includes all modifications, variations and equivalents falling within the scope of the attached claims.

[0027] In the description of each embodiment of the present application, for the convenience of description, the direction parallel to the first main surface of the electron source substrate is called "lateral", the direction perpendicular to the first main surface of the electron source substrate is called "longitudinal", and the longitudinal dimension of each component can be called "height" or "thickness".

[0028] It should be noted that the above-mentioned “horizontal” and “vertical” are only for the convenience of explanation and do not limit the orientation or posture of the electrochemical corrosion device of the present application during manufacture or use.

[0029] Example 1

[0030] Embodiment 1 provides a method for manufacturing an electron source. Figure 8 It is a schematic diagram of a method for manufacturing an electron source according to an embodiment of the present application.

[0031] like Figure 8 As shown, the manufacturing method of the electron source of the present application includes:

[0032] 801. Forming a porous structure on a first main surface of an electron source substrate;

[0033] 802. Forming a back electrode on the second main surface of the electron source substrate using a first hard mask;

[0034] 803. Forming an emitter electrode on the porous structure using a second hard mask; and

[0035] 804. Form an extraction electrode of the emission electrode on the first main surface of the electron source substrate using a third hard mask.

[0036] It should be noted that, in some embodiments of the above-mentioned manufacturing method, step 803 may be before step 804, and thus, the extraction electrode formed in step 804 may be partially arranged on the surface of the emission electrode formed in step 803; in some other embodiments of the above-mentioned manufacturing method, step 804 may be before step 803, that is, the extraction electrode is formed first, and then the emission electrode is formed, and thus, the emission electrode formed in step 803 may be partially arranged on the surface of the extraction electrode formed in step 804, which can reduce the possible damage to the emission electrode during the manufacturing process and improve the quality and reliability of the electron source.

[0037] The following embodiment is described by taking step 803 before step 804 as an example, and the related description is also applicable to the case where step 804 is before step 803.

[0038] In the present application, at least one of the second hard mask and the third hard mask is made of a silicon material.

[0039] In the manufacturing method of the electron source, after the porous silicon structure is formed, the electrode is patterned using a silicon hard mask. Since the silicon hard mask can be prepared using a semiconductor etching method, the silicon hard mask can be obtained with sufficiently high processing accuracy, and a hard mask with a relatively small thickness (for example, less than 50 microns) can be obtained. In this way, a relatively fine electrode pattern can be obtained to avoid the shadow effect, and liquid can be prevented from entering the pores of the porous silicon during the electrode formation process, which is beneficial to improving the stability and life of the electron source.

[0040] In the following description of this application, the second hard mask and the third hard mask are both made of silicon material. Therefore, the second hard mask is also called a second silicon hard mask, and the third hard mask is also called a third silicon hard mask. The following description is also applicable to the case where one of the second hard mask and the third hard mask is a silicon hard mask.

[0041] In some embodiments, the electron source substrate may be made of silicon material, for example, a silicon substrate.

[0042] In some embodiments, a plurality of electron source substrate insertion holes are formed on the first main surface of the electron source substrate, and a plurality of second hard mask through holes are formed in the second hard mask, penetrating the first main surface and the second main surface of the second hard mask. When forming the emission electrode, the first main surface of the second hard mask is closely contacted with the first main surface of the electron source substrate, and the pins are inserted into the electron source substrate insertion holes through the second hard mask through holes to align the second hard mask with the electron source substrate.

[0043] In some embodiments, a plurality of third hard mask through holes are formed in the third hard mask, penetrating the first main surface and the second main surface of the third hard mask. When forming the extraction electrode of the emission electrode, the first main surface of the third hard mask is closely connected with the first main surface of the electron source substrate, and the pin is inserted into the electron source substrate insertion hole through the third hard mask through hole to align the third hard mask with the electron source substrate.

[0044] In some embodiments, the electron source substrate plug hole, the second hard mask through hole and the third hard mask through hole are located in corresponding positions. The plug is made of metal, and the cross-sectional dimension of the plug is smaller than the minimum cross-sectional dimension of the electron source substrate plug hole, the second hard mask through hole and the third hard mask through hole.

[0045] In some embodiments, the cross section of the electron source substrate plug hole is a circle with a diameter of D1, the cross section of the second hard mask through hole is a circle with a diameter of D2, the cross section of the third hard mask through hole is a circle with a diameter of D3, and the cross section of the plug is a circle with a diameter of D4. Wherein, D4<D1≤D2, or, D4<D1≤D3. Wherein, D1 is in the range of 100 microns to 300 microns, and D4 is 5 microns to 20 microns smaller than D1.

[0046] In some embodiments, the second hard mask has a second hard mask support portion and a second hard mask pattern portion, the thickness of the second hard mask support portion is greater than the thickness of the second hard mask pattern portion, and the second hard mask through hole is formed in the second hard mask support portion. The third hard mask has a third hard mask support portion and a third hard mask pattern portion, the thickness of the third hard mask support portion is greater than the thickness of the third hard mask pattern portion, and the third hard mask through hole is formed in the third hard mask support portion.

[0047] In some embodiments, Figure 8 As shown, the method may further include the step of forming a second hard mask. For example, the second hard mask may be formed by the following method:

[0048] Etching the first main surface of the second hard mask to form a microstructure recess on the first main surface of the second hard mask, wherein the planar structure of the microstructure recess is the same as the pattern structure of the emitter electrode, wherein the depth of the microstructure recess is 5 micrometers to 50 micrometers; and

[0049] A recessed structure is formed on the second main surface of the second hard mask so that the fine structure recess is exposed in the direction of the second main surface of the hard mask substrate.

[0050] In addition, the third hard mask may be formed by a method similar to that of forming the second hard mask.

[0051] In the present application: the emitting electrode comprises a plurality of independent emitting electrode units, and the emitting electrode units are arranged in an array; and / or the porous structure comprises a plurality of independent porous structure units, and the porous structure units are arranged in an array.

[0052] Next, combine Figure 1-Figure 6 The example shown is used to illustrate the main steps of the electron source manufacturing method of the embodiment of the present application. Among them, Figure 1 It is a schematic diagram of a method for manufacturing an electron source; Figure 2 yes Figure 1 Enlarged view of the F1 part;

[0053] Figure 3 yes Figure 1 A magnified view of the F2 part; Figure 4 is a schematic diagram of a method for manufacturing an electron source back electrode; Figure 5 It is a schematic diagram of a method for manufacturing an electron source emission electrode; Figure 6 It is a schematic diagram of a method for manufacturing an extraction electrode of an electron source emission electrode; Figure 7 is a schematic diagram of a second silicon hard mask manufacturing method.

[0054] First, if Figure 1 As shown in A), an electron source substrate 20 made of silicon is prepared. The electron source substrate 20 can be a single crystal silicon substrate 1, or a composite substrate in which a polycrystalline silicon thin film (or epitaxial silicon thin film) 2 is formed on the first main surface 1a of the single crystal silicon substrate 1. Hereinafter, as a special example, the main steps of the electron source manufacturing method of this embodiment are explained by taking the composite substrate in which a polycrystalline silicon thin film 2 is formed on the first main surface 1a of the single crystal silicon substrate 1 as the electron source substrate 20. When the polycrystalline silicon thin film 2 is formed on the surface of the electron source substrate 20, the surface of the first main surface of the electron source substrate 20 is the first main surface 2a of the polycrystalline silicon thin film 2, and the second main surface 2b of the polycrystalline silicon thin film 2 is bonded to 1a.

[0055] The method for forming the polysilicon film 2 is, for example, a low pressure chemical vapor deposition (LPCVD) method. The resistivity of the polysilicon film 2 is more than 100 times the resistivity of the single crystal silicon substrate 1. For example, the resistivity of the polysilicon film 2 is ≥100Ω·cm, and the resistivity of the single crystal silicon substrate 1 is <1Ω·cm. An example is: the resistivity of the polysilicon film 2 is ≥100Ω·cm, and the resistivity of the single crystal silicon substrate 1 is ≤0.05Ω·cm. The thickness t of the polysilicon film 2 is 0.5-20μm (micrometers). An example is: the thickness t of the polysilicon film 2 is 3μm.

[0056] like Figure 2 As shown, a special case is that the polysilicon film 2 is a columnar polysilicon film. Figure 2yes Figure 1 A) is an enlarged schematic diagram of the microstructure of the area designated by the dotted line F1. Figure 2 As shown, the polycrystalline silicon film 2 is composed of a plurality of silicon crystal columns (2m, 2n, etc.) extending in the thickness direction of the polycrystalline silicon film 2 and arranged in a columnar shape. There are grain boundaries between the silicon crystal columns. For example, the intersection of the 2mth silicon crystal column and the 2nth silicon crystal column forms a grain boundary 2mn. The radial dimension of the cross section of the silicon crystal column perpendicular to the thickness direction of the polycrystalline silicon film 2 is about 5-100nm. An example is: the radial dimension of the silicon crystal column is about 10-30nm on average.

[0057] Then, if Figure 1 As shown in FIG. 2B , a plurality of substrate insertion holes 3 are formed on the electron source substrate 20 from the first main surface 2a. The cross section of the substrate insertion hole 3 can be any shape. A special case is that the number of substrate insertion holes 3 is 3, the cross section of the substrate insertion hole 3 is a circle with a diameter D1, D1 is in the range of 100μm-300μm, and the depth of the substrate insertion hole 3 is in the range of 50μm-400μm. A special case is that the depth of the substrate insertion hole 3 is about 200μm.

[0058] Then, if Figure 1 As shown in FIG. 3 , an insulating film 4 is formed on the first main surface 2a of the electron source substrate 20. The insulating film 4 is also formed on the inner surface of the substrate insertion hole 3. A special case is that the insulating film 4 is a silicon nitride film with a thickness in the range of 100-1000nm, formed by LPCVD.

[0059] Then, if Figure 1 As shown in FIG. 2 , the insulating film 4 is patterned on the first main surface 2a of the electron source substrate 20, and the first main surface 2a of the polysilicon is exposed at the insulating film window 4a. The patterning of the insulating film 4 can be achieved by a semiconductor processing method including photolithography and reactive ion beam etching (RIE) processes. The position of the pattern of the insulating film 4 is aligned and distributed based on the position of the substrate insertion hole 3.

[0060] Then, if Figure 1 As shown in FIG. 1 , a porous silicon structure 5 is formed in the polycrystalline silicon film 2. The depth t1 of the porous silicon structure 5 is less than the thickness t of the polycrystalline silicon film 2. For example, t1 = 0.2 μm-15 μm. At least part of the porous silicon structure 5 constitutes the electron emission region of the electron source 100. The porous silicon structure 5 is formed, for example, by photoelectrochemical etching. During the photoelectrochemical etching process, the chemical reaction starts from the first main surface 2a of the polycrystalline silicon film 2 exposed by the insulating film window 4a, and mainly proceeds along the grain boundaries (for example, Figure 2 The grain boundary 2mn) is directed toward the first main surface 1a of the single crystal silicon substrate 1. Figure 3 As shown, the porous silicon structure 5 has a plurality of pores 5a. Figure 3yes Figure 1 E) is an enlarged schematic diagram of the microstructure of the area designated by the dotted line F2. The cross-sectional dimension of the pore 5a perpendicular to the first main surface 2a (i.e., the lateral dimension of the pore 5a) is ≤100nm. Inside the pore 5a, a plurality of densely arranged silicon nanocrystalline grain units 5c are formed. The average size of the silicon nanocrystalline grain unit 5c is in the range of 2nm-10nm. An example is that the average size of the nanocrystalline grain unit 5c is in the range of 3nm-6nm. The silicon nanocrystalline grain unit 5c is composed of silicon nanocrystalline grains 5c1 and nanocrystalline grain insulating film 5c2 that wraps the silicon nanocrystalline grains 5c1. The thickness of the nanocrystalline grain insulating film 5c2 is in the range of 0.1nm-2nm. An example is that the thickness of the insulating film 5c2 is in the range of 0.5nm-1.5nm. The nanocrystalline grain insulating film 5c2 can be silicon oxide, formed by electrochemical oxidation (Electro Chemical Oxidation: ECO) and thermal oxidation methods. In addition, a porous silicon insulating film 5d is formed on the outer surface of the silicon crystal column 5b. The thickness of the porous silicon insulating film 5d is about 20nm-100nm. The porous silicon insulating film 5d is divided into two parts, first, a first thin film formed in the ECO process, and then a second thick film formed by thermal oxidation or the like.

[0061] Then, if Figure 1 As shown in FIG. 5 , a back electrode 6 is formed on the second main surface 1b of the single crystal silicon substrate 1. The material of the back electrode 6 can be metal, with a thickness of 200nm-2000nm. The long film of the back electrode 6, for example, Figure 4 As shown, the metal film growth process plus the hard mask method is used to achieve. A specific embodiment is as follows. First, as Figure 4 As shown in A), the first hard mask M1 is closely attached to the second main surface 1b, and the opening M1a of the first hard mask M1 is the same as the pattern of the back electrode 6. The first hard mask M1 can be made of metal or made of silicon. Generally speaking, the pattern of the back electrode 6 is relatively large, and a hard mask with a fine pattern is not required. Next, as shown in FIG. Figure 4 As shown in FIG. 1B , a 500 nm thick Al film is grown on the second main surface 1b through the opening M1a of the first hard mask M1 by a metal sputtering method (eg, magnetron sputtering method) to form a back electrode 6. Next, as shown in FIG. Figure 4 As shown in FIG. 3C , the first hard mask M1 is removed, and the manufacturing of the back electrode 6 is completed.

[0062] Then, if Figure 1As shown in FIG. 4 , an emitter electrode 7 is formed on the porous structure 5. A portion of the emitter electrode 7 extends above the insulating film 4. The material of the emitter electrode 7 can be a metal with a thickness of 5nm-15nm. A special case is that the emitter electrode 7 is composed of a 1nm titanium (Ti) film and a 10nm gold (Au) film stacked together, wherein the Ti film is in close contact with the surface of the porous structure 5, which plays a role in enhancing the surface adhesion of the emitter electrode 7 to the porous structure 5. The long film of the emitter electrode 7, such as Figure 5 As shown, the metal film growth process plus the hard mask method is used to achieve. A specific embodiment is as follows. First, as Figure 5 As shown in A), the second silicon hard mask M2 is closely attached to the first main surface 2a, and the pin Mb is inserted into the substrate insertion hole 3 through the second silicon hard mask through hole M2b. In this way, not only can the second silicon hard mask M2 and the composite substrate 20 be fixed together, but also the pattern (opening M2a) of the second silicon hard mask M2 can be aligned with the pattern position of the porous silicon structure 5. Such alignment accuracy depends on the size and processing accuracy of the pin Mb and the substrate insertion hole 3, and can generally be better than 30μm, for example, the alignment accuracy is 5μm. Next, as Figure 5 As shown in FIG. 2B , through the opening M2a of the second silicon hard mask M2, a 1 nm Ti film and a 10 nm Au film are successively sputtered by a metal sputtering method (for example, a magnetron sputtering method) to form an emitter electrode 7. Next, as shown in FIG. Figure 5 As shown in FIG. 3C , the second silicon hard mask M2 is removed to complete the manufacture of the emitter electrode 7.

[0063] Then, if Figure 1 As shown in FIG. 1 , an extraction electrode 8 of the emitter electrode is formed on the first main surface 2a. A portion of the extraction electrode 8 overlaps with the emitter electrode 7 and is electrically connected, and another portion extends to the insulating film 4. The material of the extraction electrode 8 can be metal with a thickness of 100nm-500nm. A special case is that the extraction electrode 8 is composed of a 5nm Ti film and a 200nm Au film stacked together, wherein the Ti film plays a role in enhancing surface adhesion. Figure 6 As shown, the length of the lead-out electrode 8 is similar to the length of the emitter electrode 7, and is realized by using a metal lengthening process plus a hard mask. A specific embodiment is as follows. First, as Figure 6 As shown in A), the third silicon hard mask M3 is closely attached to the first main surface 2a, and the pin Mb is inserted into the substrate insertion hole 3 through the third silicon hard mask through hole M3b. In this way, not only can the third silicon hard mask M3 and the composite substrate 20 be fixed together, but also the pattern (opening M3a) of the third silicon hard mask M3 can be aligned with the pattern position of the emitter electrode 7. For example, the alignment accuracy is 5 μm. Next, as Figure 6As shown in FIG. 1B , through the opening M3a of the third silicon hard mask M3, a 5 nm Ti film and a 200 nm Au film are successively sputtered to form the lead electrode 8. Next, as shown in FIG. Figure 6 As shown in FIG. 3C , the third silicon hard mask M3 is removed to complete the manufacture of the lead-out electrode 8.

[0064] After the above process, the electron source 100 is obtained. When the emission electrode 7 is composed of a plurality of independent units, and these emission electrode units are arranged in an array, the obtained electron source 100 is an array electron source with a plurality of independent electron emission units. For example, the number of emission electrodes 7 is 250,000, and the electron source 100 is an array electron source with 250,000 independent electron emission units. When the electron source structure 100 is an array electron source, a dedicated integrated circuit (ASIC) chip can be used to drive and control the electron emission of each electron emission unit. The electron source 100 of this embodiment can be applied as an electron source of a multi-beam electron beam direct writer. A special case is that a multi-beam electron beam direct writer can be installed with a plurality of array electron sources of this embodiment.

[0065] use Figures 1 to 6 The method shown in the figure is used to manufacture the electron source 100. Since the back electrode 6, the emission electrode 7, and the extraction electrode 8 are manufactured by hard mask after the porous silicon structure 5 is formed, the liquid is prevented from entering the porous silicon structure 5. In addition, since the second silicon hard mask M2 and the third silicon hard mask M3 with high pattern accuracy and two-layer pattern structure are used, a relatively fine electrode pattern can be obtained. Therefore, the electrode processing accuracy of the electron source 100 can be improved, and the stability and life of the electron source can also be improved.

[0066] It should be noted that in Figure 1 In the manufacturing method of the electron source shown in FIG. 1 , the step shown in G) is before the step shown in H), and thus, the extraction electrode 8 is partially disposed on the surface of the emission electrode 7. However, the present application is not limited thereto, and for example, the step shown in H) may be before the step shown in G), and thus, the emission electrode 7 is partially disposed on the surface of the extraction electrode 8, which can reduce possible damage to the emission electrode 7 during the manufacturing process and improve the quality and reliability of the electron source.

[0067] An embodiment of the present application also provides a method for manufacturing a silicon hard mask.

[0068] Combine the following Figure 7 The schematic diagram illustrates the main steps of the silicon hard mask manufacturing method of the present application.

[0069] In this embodiment, the manufacturing method of the second silicon hard mask M2 is briefly described by taking the manufacturing of the second silicon hard mask M2 as an example. The advantages of using a silicon substrate as a hard mask are: the processing technology of the silicon substrate is mature and suitable for the processing of fine structures; at the same time, the silicon hard mask is homogeneous with the substrate of the device to be processed (for example, the electron source here), and has good compatibility.

[0070] First, if Figure 7 As shown in A), a silicon substrate M is prepared. The silicon substrate M can be selected according to the size of the single crystal silicon substrate 1 of Example 1. For example, if the single crystal silicon substrate 1 is an 8-inch substrate, the silicon substrate M can be selected as a silicon substrate not less than 8 inches. The thickness of the silicon substrate M can be the thickness of a standard 8-inch silicon substrate. For example, the thickness t2 of the silicon substrate M is 400μm-900μm. The silicon substrate M has a first main surface Ma and a second main surface Mb.

[0071] Then, if Figure 7 As shown in FIG. 1 , a pattern Mc is processed in the direction of the first main surface Ma of the silicon substrate M. The processing of the pattern Mc can be performed using silicon processing technology commonly used in semiconductor processing. For example, silicon processing technology including photolithography and silicon reactive ion etching (RIE). Such processing technology can achieve submicron-level pattern accuracy. The minimum line width of the pattern Mc is, for example, 1 μm. The depth of the pattern Mc is d1, for example, d1 = 5 μm-100 μm.

[0072] Then, if Figure 7 As shown in C), a graphic Md is processed in the direction of the second main surface Mb of the silicon substrate M. The processing of the graphic Md can be roughly the same as the processing of the graphic Mc. When processing the graphic Md, the graphic Md and the graphic Mc are aligned in a double-sided alignment method. The depth of the graphic Md is d2, and the graphic Mc is to pass through the second silicon hard mask M2 to obtain an opening M2a of the silicon hard mask with a thickness of t3. For example, the thickness of the silicon substrate M is t2 = 750μm, the depth of the graphic Mc is d1 = 60μm, and the depth of the graphic Md is d2 = 710μm. In this way, the thickness of the opening M2a of the second silicon hard mask obtained is t3 = 40μm. That is, t3 = t2-d2, d2+d1>t2.

[0073] like Figure 7 As shown, while processing the second silicon hard mask opening M2a, a second silicon hard mask through hole M2b is formed on the second silicon hard mask M2. When the cross section of the substrate insertion hole 3 is a circle with a diameter of D1, the cross section of the through hole M2b is a circle with a diameter of D2, the cross section of the through hole M3b of the third silicon hard mask M3 is a circle with a diameter of D3, and the cross section of the plug is a circle with a diameter of D4. At this time, D4<D1≤D2, D3. D1 is in the range of 100-300μm, and D4 is 5-20 microns smaller than D1.

[0074] The silicon hard mask produced by the above embodiment can have a sub-micron level of graphic accuracy. At the same time, because the thickness of the hard mask opening can be less than 50μm (such as 10μm), the shadow effect when the silicon hard mask is used to form an electrode can be greatly reduced, so that the processing accuracy of the electron source device is greatly improved. This silicon hard mask is also suitable for electrode formation of other types of devices and patterning during thin film deposition.

[0075] The present application is described above in conjunction with specific implementation methods, but it should be clear to those skilled in the art that these descriptions are exemplary and are not intended to limit the scope of protection of the present application. Those skilled in the art can make various modifications and variations to the present application based on the spirit and principles of the present application, and these modifications and variations are also within the scope of the present application.

Claims

1. A method for manufacturing an electron source, characterized in that: The method comprises: forming a porous structure on a first main surface of the electron source substrate; forming a back electrode on the second main surface of the electron source substrate using a first hard mask; forming an emitter electrode on the porous structure using a second hard mask; and forming an extraction electrode of the emission electrode on the first main surface of the electron source substrate using a third hard mask, At least one of the second hard mask and the third hard mask is made of silicon material.

2. The method for manufacturing an electron source according to claim 1, wherein: A plurality of electron source substrate insertion holes are formed on the first main surface of the electron source substrate. A plurality of second hard mask through holes penetrating the first main surface and the second main surface of the second hard mask are formed in the second hard mask. When forming the emission electrode, the first main surface of the second hard mask is closely contacted with the first main surface of the electron source substrate, and the pin is inserted into the electron source substrate plug hole through the second hard mask through hole to align the second hard mask with the electron source substrate.

3. The method for manufacturing an electron source according to claim 2, wherein: A plurality of third hard mask through holes penetrating the first main surface and the second main surface of the third hard mask are formed in the third hard mask, When forming the lead-out electrode of the emission electrode, the first main surface of the third hard mask is closely contacted with the first main surface of the electron source substrate, and the pin is inserted into the electron source substrate plug hole through the third hard mask through the through hole to align the third hard mask with the electron source substrate.

4. The method for manufacturing an electron source according to claim 3, wherein: The electron source substrate insertion hole, the second hard mask through hole and the third hard mask through hole are located correspondingly. The plug is made of metal, and the cross-sectional dimension of the plug is smaller than the minimum cross-sectional dimension of the electron source substrate plug hole, the second hard mask through hole, and the third hard mask through hole.

5. The method for manufacturing an electron source according to claim 3, wherein: The cross section of the electron source substrate insertion hole is a circle with a diameter D1, The cross section of the second hard mask through hole is a circle with a diameter D2, The cross section of the third hard mask through hole is a circle with a diameter D3, The cross section of the latch is a circle with a diameter D4, D4<D1≤D2, or, D4<D1≤D3, Among them, D1 is in the range of 100 microns to 300 microns, and D4 is 5 microns to 20 microns smaller than D1.

6. The method for manufacturing an electron source according to claim 2, wherein: The second hard mask has a second hard mask supporting portion and a second hard mask pattern portion, the thickness of the second hard mask supporting portion is greater than the thickness of the second hard mask pattern portion, and the second hard mask through hole is formed in the second hard mask supporting portion.

7. The method for manufacturing an electron source according to claim 6, wherein: The method further comprises: Etching the first main surface of the second hard mask to form a fine structure recess on the first main surface of the second hard mask, wherein the planar structure of the fine structure recess is the same as the pattern structure of the emitter electrode; and On the second main surface of the second hard mask, a recessed structure is formed on the second main surface of the second hard mask so that the fine structure recess is exposed in the direction of the second main surface of the hard mask substrate, Wherein, the depth of the microstructure recess is 5 micrometers to 50 micrometers.

8. The method for manufacturing an electron source according to claim 3, wherein: The third hard mask comprises a third hard mask supporting portion and a third hard mask pattern portion, the thickness of the third hard mask supporting portion is greater than the thickness of the third hard mask pattern portion, and the third hard mask through hole is formed in the third hard mask supporting portion.

9. The method for manufacturing an electron source according to claim 1, wherein: The transmitting electrode includes a plurality of independent transmitting electrode units. The transmitting electrode units are arranged in an array; and / or The porous structure comprises a plurality of independent porous structure units. The porous structural units are arranged in an array.

10. An electron beam direct writing machine, characterized in that: The electron beam direct writer comprises an electron source, and the electron source is manufactured by the method for manufacturing an electron source according to any one of claims 1 to 9.

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