Micro-channel structure for high-power density packaging and preparation method of micro-channel structure

Abstract

The invention provides a micro-channel structure for high-power density packaging and a preparation method thereof, and the micro-channel structure comprises a carrier plate which is provided with a chip stacking body; the shell covers the carrier plate and accommodates the chip stacking body, the shell and the carrier plate form a heat dissipation micro-channel surrounding the chip stacking body, the heat dissipation micro-channel comprises an inlet and an outlet, the inlet and the outlet are formed in the side, away from the carrier plate, of the shell, cooling liquid enters and exits from the inlet and the outlet, the shell is provided with a slope part extending along the surface of the carrier plate, and the slope part extends along the surface of the carrier plate. The width, close to the carrier plate, of the slope part is larger than the width, away from the carrier plate, of the slope part. According to the invention, the cooling liquid pumping power can be reduced on the premise of ensuring the heat dissipation effect.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a low-resistance microchannel structure for high-power density packaging and a preparation method thereof. Background Art

[0002] At present, stacked packaging technology is becoming more and more mature, and it is possible to package more semiconductor chips in a limited space. However, because multiple chips are stacked in a limited space, the total heat generated by all components is high, and the heat is difficult to be released smoothly from the limited space, which will affect the service life and operation status of the components. In the prior art, fans are usually used to cool down semiconductor chips in a stacked packaging structure, but they can only cool down the outside, resulting in poor cooling effect.

[0003] In order to meet the demand for efficient heat dissipation in high-power, high-density packaging, liquid heat dissipation microfluidic cooling technology can be used. The thermal conductivity of liquid is 15-25 times that of air. Therefore, liquid heat dissipation is the key to high-power, high-density packaging (such as high-density integrated packaging of high-computing power chips). However, the current liquid heat dissipation microfluidic system still requires a lot of pumping power to pump the liquid. Although this means that the heat dissipation is improved, the power consumption is extremely large, which is bound to make the total system power consumption very large, leading to a further increase in the power consumption of high-computing power chips. In particular, when multiple high-computing power chips are used in servers and other fields, the pumping power consumed is even higher. Summary of the invention

[0004] The object of the present invention is to provide a microchannel structure for high power density packaging and a preparation method thereof, which are used to reduce the power of pumping coolant while ensuring the heat dissipation effect.

[0005] In order to solve the above technical problems, the present invention provides a microchannel structure for high power density packaging, comprising:

[0006] A carrier board, on which a chip stack is arranged;

[0007] A shell is covered on the carrier and accommodates the chip stack, and forms a heat dissipation microchannel surrounding the chip stack with the carrier, the heat dissipation microchannel includes an inlet and an outlet for cooling liquid to enter and exit, which are arranged on a side of the shell away from the carrier, and the shell has a slope extending along the surface of the carrier, and the width of the slope close to the carrier is greater than the width away from the carrier.

[0008] Optionally, a channel layer is provided on the top surface of the chip stack, the inlet and the outlet are provided in a shell on the channel layer, and grooves facing the inlet and the outlet are provided in the channel layer.

[0009] Optionally, the shell includes a bottom plate portion, a side wall portion and a cover plate portion, the bottom plate portion is connected to the carrier plate, the slope portion is the portion of the bottom plate portion close to the chip stack body, the side wall portion is connected to the bottom plate portion, the cover plate portion is connected to the side wall portion, and the cover plate portion is provided with the entrance and the exit.

[0010] Optionally, the shell is provided with an inlet and at least two outlets, and the at least two outlets are arranged in parallel at one end opposite to the inlet.

[0011] Optionally, the slope surface of the slope portion is a plane slope.

[0012] Optionally, the slope surface of the slope portion is at an angle of 40 to 50 degrees to the normal line of the surface of the carrier plate.

[0013] According to another aspect of the present invention, a method for preparing a low-resistance microfluidic channel structure for high power density packaging is also provided, comprising:

[0014] Providing a first substrate having a first surface and a second surface;

[0015] Etching the second surface of the first substrate to form a first groove on the second surface, and etching the first surface of the first substrate to form an inlet and an outlet on the first surface that communicate with the first groove;

[0016] Providing a second substrate and a carrier, wherein the second substrate is bonded to the carrier;

[0017] Etching the second substrate to form a second groove exposing the carrier, wherein the second substrate on the sidewall of the second groove includes a slope portion extending along the surface of the carrier, and the width of the slope portion close to the carrier is greater than the width away from the carrier;

[0018] The chip stack is bonded on the carrier in the second groove, and the second surface of the first substrate is bonded to the second substrate, so that the second groove, the first groove, the inlet and the outlet form a heat dissipation microchannel surrounding the chip stack.

[0019] Optionally, the step of forming the second groove includes:

[0020] forming a patterned mask layer on the second substrate, wherein an opening of the patterned mask layer exposes an area on the second substrate where the second groove is to be formed;

[0021] Anisotropically wet etching the second substrate to form the second groove to expose the carrier, wherein the sidewall of the second groove has the slope so that the second groove is wide at the top and narrow at the bottom;

[0022] The patterned mask layer is removed.

[0023] Optionally, the material of the second substrate includes silicon, and the etching solution for the anisotropic wet etching is an alkaline liquid.

[0024] Optionally, the first groove and the second groove have the same opening shape and opening size, and when the first substrate and the second substrate are bonded, the first groove and the second groove are aligned.

[0025] In summary, the low resistance microfluidic structure of the present invention includes a carrier and a shell. The shell cover is arranged on the carrier and accommodates the chip stack, and forms a heat dissipation microfluidic channel surrounding the chip stack with the carrier. The heat dissipation microfluidic channel includes an inlet and an outlet for the coolant to enter and exit the shell away from the carrier, and the shell has a slope extending along the surface of the carrier. In the present invention, the width of the slope close to the carrier is greater than the width away from the carrier, that is, the slope of the slope is inclined upward. When the coolant flows vertically down along the side of the chip stack from the inlet, the coolant falling on the slope of the slope can use the reflection of the slope on the liquid to guide the coolant to flow along the slope surface, so that the reflected coolant does not interfere with the coolant flowing vertically, thereby reducing the resistance of the coolant in the microfluidic channel, which is conducive to reducing the power used to pump the coolant while ensuring the heat dissipation effect. In addition, the slope provided below the outlet is conducive to transmitting (guiding) the coolant upward, and also has the effect of reducing the resistance of the coolant in the microfluidic channel. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Those skilled in the art should understand that the drawings are provided for a better understanding of the present invention, but do not constitute any limitation on the scope of the present invention.

[0027] Figure 1a is a structural schematic diagram of a microchannel heat dissipation structure provided by an embodiment of the present invention;

[0028] Figure 1b is a schematic top view of a microchannel heat dissipation structure provided by an embodiment of the present invention;

[0029] Figure 2 is a top view schematic diagram of another microchannel heat dissipation structure provided by an embodiment of the present invention;

[0030] Figure 3 A flow chart of a method for preparing a low-resistance microfluidic channel structure for high power density packaging provided in this embodiment;

[0031] Figure 4a to Figure 4g A schematic structural diagram corresponding to corresponding steps of the method for preparing a low-resistance microfluidic channel structure for high power density packaging provided in this embodiment.

[0032] In the attached figure:

[0033] 10-carrier; 11-packaging substrate; 12-conductive via; 13-metal solder ball; 14-first substrate; 14a-first surface; 14b-second surface; 15-second substrate; 41a-first patterned mask layer; 41b-first groove; 42a-second patterned mask layer; 43a-third patterned mask layer; 43b-second groove; 20-housing; 21-bottom plate portion; 22-slope portion; 23-side wall portion; 24-cover plate portion; 25-entrance; 26-exit; 30-chip stack; 31-chip; 32-channel layer. DETAILED DESCRIPTION

[0034] In order to make the purpose, advantages and features of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis of each drawing is different, and sometimes different scales are used.

[0035] As used in the present invention, the singular forms "one", "an", and "the" include plural objects, the term "or" is usually used to include the meaning of "and / or", the term "several" is usually used to include the meaning of "at least one", and the term "at least two" is usually used to include the meaning of "two or more". In addition, the terms "first", "second", and "third" are used only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined as "first", "second", and "third" may explicitly or implicitly include one or at least two of the features, unless the content clearly indicates otherwise.

[0036] This embodiment provides a low-resistance microfluidic channel structure for high power density packaging.

[0037] Figure 1a It is a structural schematic diagram of a microchannel heat dissipation structure for high power density packaging provided by an embodiment of the present invention; Figure 1b It is a top view schematic diagram of a microchannel heat dissipation structure for high power density packaging provided by an embodiment of the present invention.

[0038] like Figure 1a and Figure 1bAs shown, the low-resistance microfluidic structure for high power density packaging provided in this embodiment includes a carrier 10 and a housing 20. A chip stack 30 is provided on the carrier 10; the housing 20 is covered on the carrier 10 and accommodates the chip stack 30, and forms a heat dissipation microfluidic channel surrounding the chip stack 30 with the carrier 10, and the heat dissipation microfluidic channel includes an inlet 25 and an outlet 26 for coolant inlet and outlet provided on a side of the housing 20 away from the carrier 10, and the housing 20 has a slope 22 extending along the surface of the carrier 10, and the width of the slope 22 close to the carrier 10 is greater than the width away from the carrier 10.

[0039] In this embodiment, the carrier 10 may be an interposer, which has two opposite surfaces (i.e., a first surface 14a and a second surface 14b), and its material may be, for example, silicon or glass. The interposer is provided with a conductive through hole 12 (a silicon through hole or a glass through hole, which is filled with a metal material, such as copper), and metal solder balls 13 (such as tin solder balls) may be provided on both sides of the conductive through hole 12. The chip stack 30 is bonded to the first surface 14a on one side of the conductive through hole 12 (interposer) using the metal solder balls 13, and the second surface 14b of the interposer is connected to other packaging substrates 11 (such as PCB printed boards). The chip stack 30 may include at least two sequentially stacked chips 31, each chip 31 is provided with a silicon through hole and a pad, and the pad and the silicon through hole are provided with metal solder balls 13 for bonding the above-mentioned multi-layer chips 31.

[0040] Please continue to refer to Figure 1a The housing 20 may be made of a material that is easy to process and suitable for being sealed and connected (e.g., bonded) to the surface of the carrier 10. In this embodiment, the housing 20 may be made of silicon, that is, prepared from a silicon wafer by photolithography, etching, and bonding. The housing 20 may be in the shape of a bowl, buckled (covered) on the carrier 10 and forming a cavity for accommodating the chip stack 30. The housing 20 may include a bottom plate portion 21, a side wall portion 23, and a cover plate portion 24. The bottom plate portion 21 is connected to the carrier 10, and it protrudes relative to the side wall portion 23 and is closer to the chip stack 30. Its end close to the chip stack 30 may also contact the edge of the chip stack 30. The side wall portion 23 is connected to the bottom plate portion 21 and is perpendicular to the surface of the carrier 10. The cover plate portion 24 is connected to the side wall portion 23 and is away from the bottom plate portion 21. The cover plate portion 24 may be provided with an inlet 25 and an outlet 26 for the coolant to enter and exit. The inlet 25 and the outlet 26 may be provided at opposite ends of the cover plate portion 24. Thus, the above-mentioned cavity, inlet 25 and outlet 26 can form a heat dissipation microfluidic channel surrounding the chip stack 30, wherein the space between the side wall portion 23 of the shell 20, the bottom plate portion 21 and the side of the chip stack 30 serves as a microfluidic branch channel of the heat dissipation microfluidic channel surrounding the chip stack 30, and a channel layer 32 is provided on the top surface of the chip stack 30, and a plurality of grooves are provided on the surface of the channel layer 32 as microfluidic branches of the heat dissipation microfluidic channel covering the surface of the chip stack 30.

[0041] In particular, the end of the bottom plate portion 21 facing (close to) the chip stack 30 is sloped, and the slope is inclined toward the cover plate portion 24, that is, the width of the slope portion 22 (the end with the slope) close to the carrier 10 is greater than the width away from the carrier 10. When the coolant flows vertically down from the inlet 25 along the side wall portion 23 (or the side of the chip stack 30), the coolant falling on the slope of the slope portion 22 can use the reflection of the slope on the liquid to guide the coolant to flow along the slope surface, so that the reflected coolant does not interfere with the coolant flowing vertically, thereby reducing the resistance of the coolant in the microchannel, which is beneficial to reducing the power used to pump the coolant while ensuring the heat dissipation effect. In addition, the slope of the bottom plate portion 21 provided below the outlet 26 is beneficial to the transmission (conduction) of the coolant upward, and also has the effect of reducing the resistance of the coolant in the microchannel. It should be understood that in the related art, the vertically flowing coolant hits the surface of the carrier 10 or the bottom plate portion 21 parallel to the surface of the carrier 10, which will cause the reflected coolant to interfere with the vertically flowing coolant, increase the resistance of the coolant in the microchannel, and increase the pumping power of the additional effect coolant.

[0042] The slope surface of the above-mentioned slope portion 22 may be a plane slope or a curved slope, but in actual practice, the slope surface is usually a plane slope. In one example, the slope (slope surface) of the above-mentioned slope portion 22 and the normal line (a straight line perpendicular to the surface of the carrier 10) of the surface may preferably be 45°, but in practice, due to process limitations, the slope angle of the slope portion 22 is also feasible at about 45° (for example, 40° to 50°). It is understandable that due to the manufacturing process, a slope similar to the slope portion 22 may also be provided at the intersection of the side wall portion 23 and the cover portion 24.

[0043] Please continue to refer to Figure 1a , the channel layer 32 can also be used as a heat sink component to extract the heat of the chip stack 30. The top of the channel layer 32 is in contact with the cover portion 24 of the housing 20. The inlet 25 and the outlet 26 of the heat dissipation microchannel are opened in the cover portion 24 on the channel layer 32, so that the groove near the inlet 25 in the channel layer 32 serves as a liquid distribution branch of the heat dissipation microchannel, and the groove near the outlet 26 in the channel layer 32 serves as a liquid collection branch of the heat dissipation microchannel. Of course, in other examples of this embodiment, the cavity formed by the housing 20 and the carrier 10 can also be provided with at least two spaced-apart chip stacks 30 for simultaneously dissipating heat from multiple chip stacks 30.

[0044] It is understandable that if Figure 1aThe heat dissipation microchannel shown is only an example of this embodiment. This embodiment does not limit the structure and form of the heat dissipation microchannel formed by the housing 20, the carrier 10 and the chip stack 30. For example, it does not limit the shape and number of the inlet 25 and the outlet 26, the arrangement of the microchannel on the surface, side wall or inside of the chip stack 30, and the shape of the cavity formed by the housing 20 and the carrier 10. In another example of this embodiment, a plurality of microchannels may be provided in (inside) the chip stack 30 for cooling liquid to flow through the chip stack 30 to remove the heat inside the chip 31. In another example of this embodiment, as Figure 2 In the top view shown, the cover plate portion 24 of the housing 20 is provided with an inlet 25 and two outlets 26, and the two outlets 26 are arranged side by side at one end away from the inlet 25 and keep the same distance from the inlet 25. Of course, the side walls of the inlet 25 and the outlet 26 can be perpendicular to the surface of the cover plate portion 24 to facilitate the subsequent connection of other pipelines.

[0045] This embodiment also provides a method for preparing a low-resistance microfluidic channel structure for high power density packaging.

[0046] Figure 3 A flow chart of a method for preparing a low-resistance microfluidic channel structure for high power density packaging provided in this embodiment.

[0047] like Figure 3 As shown, the method for preparing a low-resistance microfluidic channel structure for high power density packaging provided in this embodiment includes the following steps:

[0048] S01: providing a first substrate having a first surface and a second surface;

[0049] S02: etching the second surface of the first substrate to form a first groove on the second surface, and etching the first surface of the first substrate to form an inlet and an outlet on the first surface that are connected to the first groove;

[0050] S03: providing a second substrate and a carrier, wherein the second substrate is bonded to the carrier;

[0051] S04: etching the second substrate to form a second groove exposing the carrier, wherein the second substrate on the sidewall of the second groove comprises a slope extending along the surface of the carrier, and the width of the slope close to the carrier is greater than the width away from the carrier;

[0052] S05: Bonding a chip stack onto the carrier in the second groove, and bonding the second surface of the first substrate to the second substrate, so as to form a heat dissipation microchannel surrounding the chip stack with the second groove, the first groove, the inlet and the outlet.

[0053] Figure 4a to Figure 4g The schematic diagram of the structure corresponding to the corresponding steps of the method for preparing the low-resistance microfluidic structure for high power density packaging provided in this embodiment is shown below. Figure 4a to Figure 4g The preparation method of the low-resistance microfluidic channel structure for high power density packaging is described in detail.

[0054] First, please refer to Figure 4a , perform step S01 to provide a first substrate 14 having a first surface 14a and a second surface 14b.

[0055] The material of the first substrate 14 may be a material suitable for bonding with a silicon substrate. In this embodiment, the material of the first substrate 14 may preferably be silicon, so as to be compatible with the process of integrated circuits and facilitate subsequent silicon-silicon bonding.

[0056] Next, step S02 is performed to etch the second surface 14b of the first substrate 14 to form a first groove 41b on the second surface 14b, and to etch the first surface 14a of the first substrate 14 to form an inlet 25 and an outlet 26 communicating with the first groove 41b on the first surface 14a.

[0057] For details, please refer to Figure 4b , a first patterned mask layer 41a may be formed on the second surface 14b of the first substrate 14, the opening of which exposes the area of ​​the second surface 14b where the first groove 41b is to be formed, then the second surface 14b of the first substrate 14 is etched to form the first groove 41b on the second surface 14b, the depth of the first groove 41b is less than the thickness of the first substrate, and then the first patterned mask layer 41a is removed. In one example, the thickness of the remaining first substrate 14 (i.e., the cover portion 24) on the first groove 41b may be greater than or equal to 100 microns to ensure its strength. In another example, the side wall of the first groove 41b (i.e., the side wall portion 23) and the bottom wall of the first groove 41b (i.e., the cover portion 24) may be at right angles.

[0058] Please refer to Figure 4c, a second patterned mask layer 42a may be formed on the first surface 14a of the first substrate 14, the opening of which exposes the area of ​​the first surface 14a where the inlet 25 and the outlet 26 are to be formed, then the first surface 14a (cover portion 24) of the first substrate 14 is etched to form the inlet 25 and the outlet 26 connected to the first groove 41b on the first surface 14a, and then the second patterned mask layer 42a is removed. Among them, the inlet 25 and the outlet 26 may be formed by an isotropic etching process (such as a dry etching process) so that the side walls of the inlet 25 and the outlet 26 are as perpendicular to their surfaces as possible. In one example, the shape of the inlet 25 and the outlet 26 may be circular, and the number of both is one, and the inlet 25 and the outlet 26 are respectively arranged at opposite ends of the first groove 41b. In another example, an inlet 25 and two outlets 26 are provided on the first groove 41b, and the two outlets 26 are arranged side by side at one end of the first groove 41b opposite to the inlet 25, and the two outlets 26 are kept at the same distance from the inlet 25.

[0059] Next, please refer to Figure 4d , executing step S03 , providing a second substrate 15 and a carrier 10 , and bonding the second substrate 15 to the carrier 10 .

[0060] The carrier 10 may be any suitable interposer, and a conductive through hole 12, such as a silicon through hole or a glass through hole, is provided in the interposer. The material of the second substrate 15 may include silicon, and the silicon wafer may have a (100) crystal orientation, for example. The thickness of the second substrate 15 may match the depth of the first groove 41b and the thickness of the chip stack 30, that is, the sum of the thickness of the second substrate 15 and the depth of the first groove 41b may be approximately equal to the thickness of the chip stack 30.

[0061] Next, please refer to Figure 4e , execute step S04, etching the second substrate 15 to form a second groove 43b exposing the carrier 10, the second substrate 15 on the side wall of the second groove 43b includes a slope portion 22 extending along the surface of the carrier 10, and the width of the slope portion 22 close to the carrier 10 is greater than the width away from the carrier 10.

[0062] Specifically, a third patterned mask layer 43a may be first formed on the surface of the carrier 10 and the second substrate 15, and its opening exposes the area on the second substrate 15 where the second groove 43b is to be formed. Then, the second substrate 15 is etched by anisotropic wet etching to form the second groove 43b to expose the carrier 10. The second substrate 15 of the side wall of the second groove 43b has a slope, and the width of the slope portion 22 close to the carrier 10 (bottom width) is greater than the width away from the carrier 10 (top width), that is, the formed second groove 43b is wide at the top and narrow at the bottom, and then the third patterned mask layer 43a is removed. As mentioned above, the material of the second substrate 15 is single crystal silicon, which has a (100) crystal orientation. When an alkaline liquid (such as potassium hydroxide) is used as a wet etching solution to etch the second substrate 15, the etching rate of the (100) crystal orientation is much greater than the etching rate of the (111) crystal orientation, that is, the etching rate in the direction perpendicular to the surface of the second substrate 15 is much greater than the etching rate in the direction inclined to the surface of the second substrate 15. Therefore, after the above-mentioned anisotropic wet etching, the second substrate 15 on the side wall of the second groove 43b has a slope portion 22 extending along the surface of the carrier 10, and the slope portion 22 makes the second groove 43b wide at the top and narrow at the bottom. In a preferred example, the surface (slope surface) of the above-mentioned slope portion 22 can be a plane slope, and the slope surface is 45° with the normal line of the surface of the carrier 10. Of course, the above-mentioned slope surface can also be other angles of about 45° (such as 40° to 50°), or it is also feasible to be a slope-like curved surface (curved slope).

[0063] It should be noted that the present embodiment does not limit the order of executing steps S10 and S02 and steps S03 and S04, that is, steps S10 and S02 may be executed after steps S03 and S04. Moreover, the mask plate for forming the third patterned mask layer 43a may be the same as the mask plate for forming the first patterned mask layer 41a. In particular, when the materials and crystal orientations of the first substrate and the second substrate are the same and a similar etching process is used, the bottom of the first groove 41b formed on the first substrate (the intersection of the side wall portion and the cover portion) may also have a slope similar to that of the second groove 43b.

[0064] Next, step S05 is executed to bond the chip stack 30 on the carrier 10 in the second groove 43b, and to bond the second surface 14b of the first substrate 14 to the second substrate 15, so as to form a heat dissipation microchannel surrounding the chip stack 30 with the second groove 43b, the first groove 41b, the inlet 25 and the outlet 26.

[0065] For details, please refer to Figure 4fThe chip stack 30 is bonded to the carrier 10 in the second groove 43b, and the chip stack 30 is bonded to the conductive via 12 (Through Silicon Via or Through Glass Via) on the carrier 10 in the second groove 43b. A channel layer 32 may be provided on the top surface (top wall) of the chip stack 30, and a plurality of grooves arranged along the plane direction are provided in the channel layer 32.

[0066] Please refer to Figure 4g The second surface 14 b of the first substrate 14 is bonded to the second substrate 15 , and a heat dissipation microchannel surrounding the chip stack 30 is formed by the second groove 43 b , the first groove 41 b , the inlet 25 and the outlet 26 .

[0067] In summary, the low resistance microfluidic structure of the present invention includes a carrier and a shell. The shell cover is arranged on the carrier and accommodates the chip stack, and forms a heat dissipation microfluidic channel surrounding the chip stack with the carrier. The heat dissipation microfluidic channel includes an inlet and an outlet for the coolant to enter and exit the shell away from the carrier, and the shell has a slope extending along the surface of the carrier. In the present invention, the width of the slope close to the carrier is greater than the width away from the carrier, that is, the slope of the slope is inclined upward. When the coolant flows vertically down along the side of the chip stack from the inlet, the coolant falling on the slope of the slope can use the reflection of the slope on the liquid to guide the coolant to flow along the slope surface, so that the reflected coolant does not interfere with the coolant flowing vertically, thereby reducing the resistance of the coolant in the microfluidic channel, which is conducive to reducing the power used to pump the coolant while ensuring the heat dissipation effect. In addition, the slope provided below the outlet is conducive to transmitting (guiding) the coolant upward, and also has the effect of reducing the resistance of the coolant in the microfluidic channel.

[0068] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A low-resistance microfluidic structure for high power density packaging, characterized in that: include: A carrier board, on which a chip stack is arranged; A shell is covered on the carrier and accommodates the chip stack, and forms a heat dissipation microchannel surrounding the chip stack with the carrier, the heat dissipation microchannel includes an inlet and an outlet for cooling liquid to enter and exit, which are arranged on a side of the shell away from the carrier, and the shell has a slope extending along the surface of the carrier, and the width of the slope close to the carrier is greater than the width away from the carrier.

2. The low-resistance microchannel structure for high power density packaging according to claim 1, characterized in that: A channel layer is disposed on the top surface of the chip stack, the inlet and the outlet are disposed in a housing on the channel layer, and grooves facing the inlet and the outlet are disposed in the channel layer.

3. The low-resistance microfluidic channel structure for high power density packaging according to claim 1, characterized in that: The shell includes a bottom plate portion, a side wall portion and a cover plate portion, the bottom plate portion is connected to the carrier plate, the slope portion is the portion of the bottom plate portion close to the chip stacking body, the side wall portion is connected to the bottom plate portion, the cover plate portion is connected to the side wall portion, and the cover plate portion is provided with the inlet and the outlet.

4. The low-resistance microchannel structure for high power density packaging according to claim 3, characterized in that: The shell is provided with an inlet and at least two outlets, and the at least two outlets are arranged in parallel at one end opposite to the inlet.

5. The low-resistance microfluidic channel structure for high power density packaging according to claim 1, characterized in that: The slope surface of the slope portion is a plane slope.

6. The low-resistance microchannel structure for high power density packaging according to claim 5, characterized in that: The slope surface of the slope portion is 40-50 degrees away from the normal line of the surface of the carrier plate.

7. A method for preparing a low-resistance microfluidic structure for high power density packaging, characterized in that: include: Providing a first substrate having a first surface and a second surface; Etching the second surface of the first substrate to form a first groove on the second surface, and etching the first surface of the first substrate to form an inlet and an outlet on the first surface that communicate with the first groove; Providing a second substrate and a carrier, wherein the second substrate is bonded to the carrier; Etching the second substrate to form a second groove exposing the carrier, wherein the second substrate on the sidewall of the second groove includes a slope portion extending along the surface of the carrier, and the width of the slope portion close to the carrier is greater than the width away from the carrier; The chip stack is bonded on the carrier in the second groove, and the second surface of the first substrate is bonded to the second substrate, so that the second groove, the first groove, the inlet and the outlet form a heat dissipation microchannel surrounding the chip stack.

8. The method for preparing a low-resistance microfluidic channel structure for high power density packaging according to claim 7, characterized in that: The step of forming the second groove comprises: forming a patterned mask layer on the second substrate, wherein an opening of the patterned mask layer exposes an area on the second substrate where the second groove is to be formed; Anisotropically wet etching the second substrate to form the second groove to expose the carrier, wherein the sidewall of the second groove has the slope so that the second groove is wide at the top and narrow at the bottom; The patterned mask layer is removed.

9. The method for preparing a low-resistance microfluidic structure for high power density packaging according to claim 8, characterized in that: The material of the second substrate includes silicon, and the etching solution of the anisotropic wet etching is an alkaline liquid.

10. The method for preparing a low-resistance microfluidic channel structure for high power density packaging according to claim 7, characterized in that: The opening shapes and opening sizes of the first groove and the second groove are the same, and when the first substrate and the second substrate are bonded, the first groove and the second groove are aligned.

Images