Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof. The semiconductor structure comprises a substrate; the gate structure is formed on the surface of the substrate; the pair of side walls are formed on the side walls on the two sides of the gate structure respectively; the source electrode region and the drain electrode region are respectively formed on the substrate at two sides of the gate electrode structure; the metal silicide layer is formed on the surfaces of the gate structure, the source region and the drain region; wherein for any one of the source electrode region and the drain electrode region, a non-zero gap is formed between the region and the side wall, and / or the distance from a metal silicide layer formed on the surface of the region to the gate structure is greater than the width of the side wall. According to the scheme, the voltage resistance and the electric leakage performance of the device can be reliably improved on the premise that the threshold voltage is hardly influenced.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] Metal-oxide-semiconductor field-effect transistor (MOSFET) is widely used in various fields such as industry, automobile, consumer electronics, etc. due to its advantages such as high input impedance, low noise and good thermal stability.

[0003] For some medium and large size MOSFET devices, in addition to strict requirements on the threshold voltage Vt of the device, the device's withstand voltage (BV, or BV DSS However, the existing technology cannot take into account the above-mentioned multiple requirements. For example, the device's voltage resistance and leakage performance can only be improved by sacrificing the threshold voltage. Summary of the invention

[0004] The technical problem solved by the present disclosure is to provide an improved semiconductor structure and a method for forming the same.

[0005] To solve the above technical problems, an embodiment of the present disclosure provides a semiconductor structure, comprising: a substrate; a gate structure formed on the surface of the substrate; a pair of sidewalls formed on the sidewalls on both sides of the gate structure; a source region and a drain region formed on the substrate on both sides of the gate structure; a metal silicide layer formed on the surface of the gate structure, the source region and the drain region; wherein, for any region of the source region and the drain region, there is a non-zero gap between the region and the sidewall, and / or the spacing between the metal silicide layer formed on the surface of the region and the gate structure is greater than the width of the sidewall.

[0006] Optionally, the semiconductor structure further includes: a first barrier layer covering the sidewall spacer and a surface of an adjacent substrate, and a portion of the substrate surface covered by the first barrier layer is suitable for forming the gap.

[0007] Optionally, the preparation process of the first barrier layer is prior to the preparation process of the source region and the drain region, and the first barrier layer is removed after the source region and the drain region are formed.

[0008] Optionally, the material of the first barrier layer is photoresist.

[0009] Optionally, the semiconductor structure further includes: a second barrier layer formed at least on the surface of the substrate on the side opposite to the pair of sidewalls, wherein the second barrier layer is used to block the formation of metal silicide.

[0010] Optionally, the second barrier layer is removed after forming the metal silicide layer.

[0011] Optionally, the second barrier layer and the region are adjacent to or at least partially overlap.

[0012] Optionally, the width of the side wall is from 25 to 35 nanometers; and / or, the width of the gap is from 50 to 60 nanometers; and / or, the spacing from the gate structure to the region is from 75 to 95 nanometers; and / or, the spacing from the metal silicide layer formed on the surface of the region to the gate structure is from 55 to 75 nanometers.

[0013] Optionally, a distance between the metal silicide layer formed on the surface of the region and the gate structure is greater than or equal to a distance between the region and the gate structure.

[0014] In order to solve the above technical problems, the embodiments of the present disclosure also provide a method for forming a semiconductor structure, including: providing a substrate; forming a gate structure on the surface of the substrate; forming a pair of sidewalls on the sidewalls on both sides of the gate structure; forming a source region and a drain region on the substrate on both sides of the gate structure; forming a metal silicide layer on the surface of the gate structure, the source region and the drain region; wherein, for any region of the source region and the drain region, there is a non-zero gap between the region and the sidewall, and / or the spacing between the metal silicide layer formed on the surface of the region and the gate structure is greater than the width of the sidewall.

[0015] Optionally, forming the source region and the drain region on the substrate on both sides of the gate structure respectively includes: covering the surface of the side wall and the adjacent substrate with a first barrier layer; and performing ion implantation on the substrate using the first barrier layer as a mask to form the source region and the drain region on the substrate on both sides of the gate structure respectively.

[0016] Optionally, the formation method further includes: removing the first barrier layer.

[0017] Optionally, the forming of the metal silicide layer on the surface of the gate structure, the source region and the drain region includes: covering the surface of the substrate with a metal silicide blocking layer; processing the metal silicide blocking layer using a photolithography process to obtain a second blocking layer formed at least on the surface of the substrate on the side opposite to each other of the pair of side walls; and forming the metal silicide layer on the surface of the gate structure, the source region and the drain region using the second blocking layer as a mask.

[0018] Optionally, the formation method further includes: removing the second barrier layer.

[0019] Compared with the prior art, the technical solution of the embodiment of the present disclosure has the following beneficial effects:

[0020] An embodiment of the present disclosure provides a semiconductor structure, comprising: a substrate; a gate structure formed on the surface of the substrate; a pair of sidewalls formed on the sidewalls on both sides of the gate structure; a source region and a drain region formed on the substrate on both sides of the gate structure; a metal silicide layer formed on the surfaces of the gate structure, the source region and the drain region; wherein, for any region of the source region and the drain region, there is a non-zero gap between the region and the sidewall, and / or the spacing between the metal silicide layer formed on the surface of the region and the gate structure is greater than the width of the sidewall.

[0021] By adopting this embodiment, the voltage resistance and leakage performance of the device can be reliably improved without affecting the threshold voltage. Specifically, the gap design between the source region and / or the drain region and the sidewall is conducive to increasing the channel length, increasing the equivalent resistance between the source and the drain, and reducing the gradient of the channel electric field, so that the voltage distribution is more uniform, effectively reducing the leakage current, and improving the breakdown characteristics. Further, the spacing between the metal silicide layer on the surface of the source region and / or the drain region and the gate structure is increased, which is conducive to reducing the leakage caused by the influence of the gate structure on the substrate current Isub, because the main reason for the double peak is that as the gate voltage Vg increases, the strong electric field in the channel controlled by the gate moves to the N+ edge outside the channel, thereby causing N+P-type well (PW) junction leakage. Therefore, there is no need to change the critical dimensions of the gate structure, and no significant change in the threshold voltage will be caused. On this basis, the voltage resistance and leakage performance of the device can also be effectively improved.

[0022] The embodiments of the present disclosure also provide a method for forming a semiconductor structure, comprising: providing a substrate; forming a gate structure on the surface of the substrate; forming a pair of sidewalls on the sidewalls on both sides of the gate structure; forming a source region and a drain region on the substrate on both sides of the gate structure; forming a metal silicide layer on the surface of the gate structure, the source region and the drain region; wherein, for any region of the source region and the drain region, there is a non-zero gap between the region and the sidewall, and / or the spacing between the metal silicide layer formed on the surface of the region and the gate structure is greater than the width of the sidewall.

[0023] Thus, the manufactured semiconductor structure can reliably improve the voltage resistance and leakage performance of the device without affecting the threshold voltage.

[0024] Furthermore, a first barrier layer is added during ion implantation in the source and drain regions, and the ion implantation region is controlled to increase the channel length, thereby increasing the equivalent resistance between the source and drain, reducing the gradient of the channel electric field, thereby making the voltage distribution more uniform, effectively reducing the leakage current, and improving the breakdown characteristics.

[0025] Furthermore, when forming the second barrier layer, a section of the metal silicide barrier layer is retained on both sides of the gate structure, so that the distance between the formed metal silicide layer and the gate structure is further increased, thereby greatly reducing the leakage performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 is a schematic diagram of a semiconductor structure according to the first embodiment of the present disclosure;

[0027] Figures 2 to 10 It is a schematic diagram of a device cross-sectional structure corresponding to each step in a formation process of a semiconductor structure according to an embodiment of the present disclosure;

[0028] Fig.11 is a schematic diagram of a semiconductor structure according to a second embodiment of the present disclosure;

[0029] Fig.12 It is a schematic diagram of a semiconductor structure according to the third embodiment of the present disclosure. DETAILED DESCRIPTION

[0030] Next, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The same reference numerals are used to denote the same parts in the various figures. The embodiments are merely illustrative, and of course, the structures shown in different embodiments may be partially replaced or combined. In the variants, the description of matters common to the first embodiment is omitted, and only the differences are described. In particular, the same effects produced by the same structure are no longer mentioned one by one according to each embodiment.

[0031] In order to make the above-mentioned objects, features and beneficial effects of the present disclosure more obvious and easy to understand, the specific embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0032] Figure 1 It is a schematic diagram of a semiconductor structure 1 according to the first embodiment of the present disclosure.

[0033] The semiconductor structure 1 of this embodiment may be a MOSFET device, such as CMOS (Complementary Metal Oxide Semiconductor), NMOS (N-Metal Oxide Semiconductor) or PMOS (P-Metal Oxide Semiconductor).

[0034] Specifically, refer to Figure 1 The semiconductor structure 1 may include: a substrate 100; a gate structure 101 formed on the surface of the substrate 100; a pair of sidewalls 102 formed on the sidewalls of the gate structure 101; a source region 103 and a drain region 104 formed on the substrate 100 on both sides of the gate structure 101; and a metal silicide layer 105 formed on the surfaces of the gate structure 101, the source region 103 and the drain region 104.

[0035] The semiconductor structure 1 further satisfies at least one of the following conditions 1 and 2:

[0036] Condition 1: For any region of the source region 103 and the drain region 104 , there is a non-zero gap gap between the region and the spacer 102 ;

[0037] Condition 2: for any region of the source region 103 and the drain region 104 , a distance L4 between the metal silicide layer 105 formed on the surface of the region and the gate structure 101 is greater than a width L3 of the spacer 102 .

[0038] Figure 1 The semiconductor structure 1 that satisfies both condition 1 and condition 2 is taken as an example for exemplary demonstration.

[0039] More specifically, in condition 1, there is a non-zero gap gap between the region and the sidewall 102 located on the same side. Figure 1 Taking the perspective shown as an example, there is a gap between the source region 103 on the left side of the gate structure 101 and the sidewall 102 also on the left side of the gate structure 101. Similarly, there is a gap between the drain region 104 on the right side of the gate structure 101 and the sidewall 102 also on the right side of the gate structure 101.

[0040] Furthermore, in condition 2, the distance L4 between the metal silicide layer 105 on the surface of the region and the gate structure 101 is greater than the width of the sidewall spacer 102 on the same side. Figure 1 Taking the perspective shown as an example, the distance L4 between the metal silicide layer 105 located on the surface of the source region 103 and the gate structure 101 is greater than the width L3 of the sidewall 102 located on the left side of the gate structure 101. In other words, there is a non-zero gap between the metal silicide layer 105 located on the surface of the source region 103 and the sidewall 102. Similarly, the distance L4 between the metal silicide layer 105 located on the surface of the drain region 104 and the gate structure 101 is greater than the width L3 of the sidewall 102 located on the right side of the gate structure 101. In other words, there is a non-zero gap between the metal silicide layer 105 located on the surface of the drain region 104 and the sidewall 102.

[0041] In some embodiments, the gap between the source region 103 and the sidewall spacer 102 on the same side may be the same as or different from the gap between the drain region 104 and the sidewall spacer 102 on the same side. This facilitates flexible design of the relative positions between the source region 103, the drain region 104 and the sidewall spacer 102 as needed.

[0042] In some embodiments, the distance L4 between the metal silicide layer 105 on the surface of the source region 103 and the gate structure 101 may be the same as or different from the distance L4 between the metal silicide layer 105 on the surface of the drain region 104 and the gate structure 101. This facilitates flexible design of the relative positions between the metal silicide layer 105 on the surface of the source region 103, the metal silicide layer 105 on the surface of the drain region 104, and the gate structure 101 as needed.

[0043] In some embodiments, the distance L4 between the metal silicide layer 105 formed on the surface of the region and the gate structure 101 may be greater than or equal to the distance L5 between the region and the gate structure 101. In other words, the region and the metal silicide layer 105 located on the surface thereof may be flush, or the region may be closer to the gate structure 101 than the metal silicide 105 located on the surface thereof.

[0044] Specifically, the distance L5 from the region to the gate structure 101 is equal to the sum of the width L3 of the sidewall 102 and the gap gap from the region to the sidewall 102 located on the same side. Further, the distance between the metal silicide layer 105 located on the surface of the source region 103 (or the drain region 104) and the sidewall 102 may be greater than or equal to the gap gap from the source region 103 (or the drain region 104) to the sidewall 102.

[0045] As a result, the constraints on the relative positions between the source and drain regions and the metal silicide layer 105 are reduced, which is conducive to flexibly adjusting the specific structure of the semiconductor structure 1 according to the actual application scenario of the device.

[0046] Figures 2 to 10 is a schematic diagram of the device cross-sectional structure corresponding to each step in the formation process of the semiconductor structure described in this embodiment. Among them, the formation process can be used to form the above Figure 1 The semiconductor structure 1 is shown. Next, Figures 2 to 10 Each step of the formation process of the semiconductor structure 1 is described in detail.

[0047] In one specific implementation, reference Figure 2, providing a substrate 100. The material of the substrate may include silicon, germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium. The doping type of the substrate 100 may be N-type, and accordingly, the substrate 100 may be N-type silicon. Alternatively, the doping type of the substrate 100 may be P-type, and accordingly, the substrate 100 may be P-type silicon.

[0048] In one specific implementation, reference Figure 3 , a gate structure 101 is formed on the surface of the substrate 100. Specifically, an oxide layer may be first deposited on the surface of the substrate 100, then a polysilicon layer may be deposited, and finally the gate structure 101 may be formed by etching. The gate structure 101 is suitable for serving as a gate of a MOSFET device.

[0049] In one specific implementation, reference Figure 4 , a pair of sidewalls 102 are formed on the sidewalls on both sides of the gate structure 101. Specifically, a dielectric layer can be covered on the surface of the substrate 100 and the gate structure 101, and then directional etching is performed to form sidewalls 102 on the sidewalls on both sides of the gate structure 101. The sidewalls 102 are suitable for forming an isolation layer (spacer). The material of the dielectric layer can be silicon nitride Si3N4 (abbreviated as SiN) or silicon dioxide SiO2.

[0050] In one specific implementation, reference Figure 5 , the surface of the sidewall 102 and the adjacent substrate 100 is covered with a first barrier layer 106. Specifically, the material of the first barrier layer can be photoresist. Accordingly, based on the exposure and development process in the photolithography process, a layer of photoresist layer can be specifically covered on the sidewall 102 and the surface of the surrounding substrate 100 to form the first barrier layer 106.

[0051] Further, refer to Figure 6 , ion implantation is performed on the substrate 100 using the first barrier layer 106 as a mask to form a source region 103 and a drain region 104 on the substrate 100 at both sides of the gate structure 101. For a P-type substrate 100, N+ doping can be performed to form the source region 103 and the drain region 104. For an N-type substrate 100, P+ doping can be performed to form the source region 103 and the drain region 104.

[0052] During the ion implantation, the presence of the first barrier layer 106 prevents the region of the substrate 100 close to the sidewall 102 from being directly implanted with doping ions, thereby allowing a non-zero gap to exist between the formed drain region 104 and the source region 103 and the sidewall 102 on their respective sides. In other words, the portion of the first barrier layer 106 covering the surface of the substrate 100 is suitable for forming a gap between the source region 103 and the sidewall 102 and a gap between the drain region 104 and the sidewall 102.

[0053] Further, after forming the source region 103 and the drain region 104, the first barrier layer 106 is removed to obtain Figure 7 For example, the first barrier layer 106 may be removed by a wet stripping process, such as stripping with an organic solvent or an inorganic solvent. For another example, the first barrier layer 106 may be removed by a dry stripping process, such as stripping the photoresist with plasma.

[0054] Therefore, a first barrier layer 106 is added during ion implantation in the source and drain regions, and the ion implantation region is controlled to increase the channel length L1.

[0055] The prior art usually simply forms a wider sidewall or stacks multiple sidewalls to increase the channel length. However, for a die, a single die can have multiple devices. If a wider sidewall is to be formed, all devices in the single die will form a wider sidewall, which is disadvantageous for the performance of some types of devices.

[0056] In comparison, the first barrier layer 106 formed by photoresist in this embodiment can be formed in a specified device among multiple devices in a single die through a specially designed mask pattern. In addition, the first barrier layer 106 is also a consumable material and can be removed after the gap is formed, thereby improving the leakage performance of the device while not affecting the performance of the device that does not require a wider sidewall among multiple devices in a single die.

[0057] In a specific implementation, after obtaining Figure 7 After the structure shown in FIG. 1 is formed, a metal silicide layer may be further formed on the surface of the gate structure, the source region and the drain region to obtain the structure shown in FIG. Figure 1 A semiconductor structure 1 is shown.

[0058] Specifically, refer to Figure 8 , a metal silicide barrier layer 107 is covered on the surface of the substrate 100. For example, a deposition process can be used to cover a metal silicide barrier layer 107 on the surface of the substrate 100, a pair of sidewalls 102, and the gate structure 101. The material of the metal silicide barrier layer 107 can be selected from dielectric materials such as SiO2, SiN, and SiON (intermediate phase of silicon dioxide and silicon nitride).

[0059] Further, refer to Fig. 9, the metal silicide barrier layer 107 is processed by a photolithography process to obtain a second barrier layer 108 formed at least on the surface of the substrate 100 on the opposite side of a pair of sidewalls 102. For example, a special mask pattern can be designed so that the metal silicide barrier layer 107 is retained at least on the surface of the substrate 100 around the sidewalls 102 after the etching process based on the pattern to be etched formed by exposing the metal silicide barrier layer 107 on the mask, and the retained part of the metal silicide barrier layer 107 is used as the second barrier layer 108 to block the formation of metal silicide.

[0060] Further, refer to Fig.10 , using the second barrier layer 108 as a mask, a metal silicide layer 105 is formed on the surface of the gate structure 101, the source region 103 and the drain region 104. For example, a layer of metal (titanium Ti, cobalt Co and nickel platinum target NiPt, etc.) can be deposited on the active area and the polysilicon gate by physical vapor deposition (PVD), and then a rapid thermal annealing process is performed to form the metal silicide layer 105. It should be pointed out that during ion implantation, the boundaries of the source region 103 and the drain region 104 may invade the area where the gap is located, so the second barrier layer 108 is used to prevent the substrate 100 at the gap from reacting with the metal to form a self-aligned metal silicide. Fig.10 The formation of the metal silicide layer 105 on the surface of the substrate 100 at the periphery of the active region is omitted in the figure, thereby ensuring that the distance L5 between the finally formed metal silicide layer 105 and the gate structure 101 meets expectations.

[0061] Further, after forming the metal silicide layer 105, the second barrier layer 108 can be removed to obtain Figure 1 The semiconductor structure 1 is shown. For example, the second barrier layer 108 may be removed by using an etching process (eg, a selective etching process).

[0062] Therefore, when forming the second barrier layer 108 , a section of the metal silicide barrier layer 107 is reserved on both sides of the gate structure 101 , so that the distance L4 between the formed metal silicide layer 105 and the gate structure 101 is further increased.

[0063] In one specific implementation, reference Fig. 9 , the second barrier layer 108 is adjacent to the source region 103, and similarly, the second barrier layer 108 is adjacent to the drain region 104. Figures 2 to 10 The prepared Figure 1In the semiconductor structure 1 shown, the source region 103 and the metal silicide layer 105 formed on the surface thereof are flush on the side close to the sidewall 102 . Similarly, the drain region 104 and the metal silicide layer 105 formed on the surface thereof are flush on the side close to the sidewall 102 .

[0064] From the above, the present embodiment can reliably improve the voltage resistance and leakage performance of the device without affecting the threshold voltage. Specifically, the gap design between the source region 103 and / or the drain region 104 and the sidewall 102 is conducive to increasing the channel length (i.e., the length of L1), increasing the equivalent resistance between the source and drain, and reducing the gradient of the channel electric field, thereby making the voltage distribution more uniform, effectively reducing the leakage current, and improving the breakdown characteristics. Further, the spacing L4 between the metal silicide layer 105 on the surface of the source region 103 and / or the drain region 104 and the gate structure 101 is increased, which is conducive to reducing the leakage caused by the influence of the gate structure 101 on the substrate 100 current Isub, because the main reason for the double peak is that as the gate voltage Vg increases, the strong electric field in the channel controlled by the gate moves to the N+ edge outside the channel, thereby causing N+P-type well (PW) junction leakage. Therefore, there is no need to change the critical dimension (ie, L2) of the gate structure 101, and thus no significant change in the threshold voltage will be caused. On this basis, the voltage resistance and leakage performance of the device can be effectively improved.

[0065] Fig.11 Schematic diagram of a semiconductor structure 2 according to the second embodiment of the present disclosure. Figure 1 The differences from the first embodiment are described below.

[0066] Specifically, Figure 1 The difference between the semiconductor structure 1 described in the first embodiment is that in the semiconductor structure 2 described in the second embodiment, the source region 103 is closer to the sidewall 102 than the metal silicide layer 105 formed on its surface, and similarly, the drain region 104 is closer to the sidewall 102 than the metal silicide layer 105 formed on its surface.

[0067] For example, when forming the second barrier layer 108, by adjusting the mask pattern, the second barrier layer 108 can at least partially overlap with the source region 103 and the drain region 104. In other words, the second barrier layer 108 covers the gap gap and part of the source region 103 and part of the drain region 104. As a result, the part of the sidewall 102 of the source region 103 and the drain region 104 close to the side thereof will not react with the metal to form the metal silicide layer 105.

[0068] Therefore, on the basis of increasing the channel length, further increasing the distance L4 between the metal silicide layer 105 and the gate structure 101 is beneficial to better improve the leakage performance.

[0069] Fig.12 Schematic diagram of a semiconductor structure 3 according to the third embodiment of the present disclosure. Figure 1 The differences from the first embodiment are described below.

[0070] Specifically, Figure 1 The difference between the semiconductor structure 1 described in the first embodiment is that the semiconductor structure 2 described in the second embodiment preferably satisfies condition 2, that is, the gap between the source region 103 and the sidewall 102 is zero (that is, L5=L3), and the distance L4 between the metal silicide layer 105 formed on the surface of the source region 103 and the gate structure 101 is greater than the width L3 of the sidewall 102. Similarly, the gap between the drain region 104 and the sidewall 102 is zero (that is, L5=L3), and the distance L4 between the metal silicide layer 105 formed on the surface of the drain region 104 and the gate structure 101 is greater than the width L3 of the sidewall 102.

[0071] Therefore, the metal silicide layer 105 which is farther from the gate structure 101 can be formed by simply adjusting the mask pattern when forming the second barrier layer 108. The preparation process of the entire semiconductor structure 3 is simple, which can reduce the leakage performance and the manufacturing cost at the same time.

[0072] In a variation, the semiconductor structure can preferably satisfy condition 1, that is, there is a non-zero gap gap between the source region 103 and the sidewall 102, and between the drain region 104 and the sidewall 102. Further, when the second barrier layer 108 is subsequently formed, a section of the second barrier layer 108 is not intentionally retained on the side opposite to the sidewall 102, but a conventional self-alignment process is used to form a metal silicide layer 105 on the surface of the gate structure 101, the source region 103, and the drain region 104. Therefore, the leakage performance can be reduced without changing the mask pattern when forming the second barrier layer 108.

[0073] In a common embodiment of the above embodiments, the width L3 of the spacer 102 can be in the range of 25 to 35 nanometers (nm), for example, L3 = 30 nm.

[0074] In a common embodiment of the above embodiments, the width of the gap gap can be in the range of 50 to 60 nanometers, for example, gap=50 nm.

[0075] In a common embodiment of the above embodiments, the distance L5 between the gate structure 101 and the region can be in the range of 75 to 95 nanometers, for example, L5=80 nm.

[0076] In some embodiments, the specific values ​​of the width L3 of the sidewall 102, the width of the gap gap, and the spacing L5 from the gate structure 101 to the region can be determined based on factors such as the overall size of the semiconductor structure 1 (or semiconductor structure 2, semiconductor structure 3), the short circuit limitation between adjacent semiconductor structures 1 (or semiconductor structure 2, semiconductor structure 3), and the like.

[0077] Specifically, in actual preparation, a plurality of devices may be formed in a die, wherein the structure of at least one device adopts the structure of semiconductor structure 1 (or semiconductor structure 2, semiconductor structure 3), then the values ​​of L3, gap and L5 need to take into account the short circuit problem between adjacent devices. For example, the width of the gap should not be too large, otherwise the gap between adjacent devices may be too small to easily cause a short circuit.

[0078] In a common embodiment of the above embodiments, the distance L4 between the metal silicide layer 105 formed on the surface of the region and the gate structure 101 can be 55 to 75 nanometers. Preferably, L4≥gap width.

[0079] Although the disclosure is disclosed as above, the disclosure is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the disclosure, so the protection scope of the disclosure should be based on the scope defined by the claims.

Claims

1. A semiconductor structure, It is characterized in that include: substrate; A gate structure formed on the surface of the substrate; A pair of sidewalls, respectively formed on the sidewalls of both sides of the gate structure; A source region and a drain region are respectively formed on the substrate at both sides of the gate structure; A metal silicide layer is formed on the surface of the gate structure, the source region and the drain region; wherein, for any region of the source region and the drain region, there is a non-zero gap between the region and the sidewall, and / or, the spacing between the metal silicide layer formed on the surface of the region and the gate structure is greater than the width of the sidewall.

2. The semiconductor structure according to claim 1, It is characterized in that Also includes: A first barrier layer covers the sidewall spacer and a surface of an adjacent substrate, and a portion of the substrate surface covered by the first barrier layer is suitable for forming the gap.

3. The semiconductor structure according to claim 2, It is characterized in that The preparation process of the first barrier layer is prior to the preparation process of the source region and the drain region, and the first barrier layer is removed after the source region and the drain region are formed.

4. The semiconductor structure according to claim 2, It is characterized in that The material of the first barrier layer is photoresist.

5. The semiconductor structure according to claim 1, It is characterized in that Also includes: The second barrier layer is formed at least on the substrate surface on the opposite side of the pair of sidewalls, and the second barrier layer is used to block the formation of metal silicide.

6. The semiconductor structure according to claim 5, It is characterized in that The second barrier layer is removed after forming the metal silicide layer.

7. The semiconductor structure according to claim 5, It is characterized in that The second barrier layer and the region are adjacent to or at least partially overlap.

8. The semiconductor structure according to claim 1, It is characterized in that The width of the side wall is from 25 to 35 nanometers; and / or, the width of the gap is from 50 to 60 nanometers; and / or, the distance from the gate structure to the region is from 75 to 95 nanometers; and / or, the distance from the metal silicide layer formed on the surface of the region to the gate structure is from 55 to 75 nanometers.

9. The semiconductor structure according to claim 1, It is characterized in that The distance between the metal silicide layer formed on the surface of the region and the gate structure is greater than or equal to the distance between the region and the gate structure.

10. A method for forming a semiconductor structure, It is characterized in that include: providing a substrate; forming a gate structure on the surface of the substrate; forming a pair of sidewalls on the sidewalls of both sides of the gate structure respectively; forming a source region and a drain region on the substrate at both sides of the gate structure respectively; A metal silicide layer is formed on the surface of the gate structure, the source region and the drain region; wherein, for any region of the source region and the drain region, there is a non-zero gap between the region and the side wall, and / or, the distance between the metal silicide layer formed on the surface of the region and the gate structure is greater than the width of the side wall.

11. The forming method according to claim 10, It is characterized in that The forming of a source region and a drain region on the substrate at both sides of the gate structure respectively comprises: Covering the surface of the sidewall and the adjacent substrate with a first barrier layer; Ion implantation is performed on the substrate using the first barrier layer as a mask to form the source region and the drain region on the substrate at both sides of the gate structure respectively.

12. The forming method according to claim 11, It is characterized in that Also includes: The first barrier layer is removed.

13. The forming method according to claim 10, It is characterized in that The forming of a metal silicide layer on the surface of the gate structure, the source region and the drain region comprises: Covering the surface of the substrate with a metal silicide barrier layer; Processing the metal silicide barrier layer by photolithography to obtain a second barrier layer formed at least on the surface of the substrate on the opposite side of the pair of sidewalls; A metal silicide layer is formed on the surface of the gate structure, the source region and the drain region using the second barrier layer as a mask.

14. The forming method according to claim 13, It is characterized in that Also includes: The second barrier layer is removed.

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