Formation method of semiconductor structure

Abstract

A method for forming a semiconductor structure comprises the steps that a substrate is provided, the substrate is provided with at least two selection grids, openings are formed between the adjacent selection grids, the selection grids are arranged in the first direction, and the first direction is parallel to the surface of the substrate; forming a floating gate layer on the surface of the opening and the top surface of the selection gate; forming a first sacrificial layer in the opening and on the surface of the floating gate layer at the top of the selection gate; and forming a second sacrificial layer on the first sacrificial layer. The first sacrificial layer and the second sacrificial layer are adopted as the sacrificial layers for forming the floating gate, compared with the scheme that only the first sacrificial layer is adopted as the sacrificial layer for forming the floating gate in the prior art, the thickness of the first sacrificial layer is reduced, and the second sacrificial layer with good step coverage rate and gap filling capability is formed on the first sacrificial layer; the possibility of hole occurrence is reduced, and the performance of the semiconductor device is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductors, and in particular to a method for forming a semiconductor structure. Background Art

[0002] Floating gate flash memory is the most widely used flash memory technology. It is a non-volatile memory whose basic unit is a MOS tube with a floating gate. However, as the size of flash memory cells shrinks dramatically, the proportional reduction of floating gate flash memory faces huge challenges. In floating gate flash memory, when filling amorphous carbon into deep trenches, there are vacancies and unsealed holes, resulting in a thin photoresist layer formed on the surface of the vacancies. In the subsequent photo rework process, part of the amorphous carbon will be removed, resulting in the scrapping of the wafer.

[0003] However, currently, the problem of voids in deep trenches is solved by increasing the thickness of amorphous carbon so that the voids at the top can be sealed. However, the increase in the thickness of amorphous carbon will cause over-etching of the floating gate, which in turn leads to the risk of active area damage (i.e., AA damage), affecting the performance of semiconductor devices. Summary of the invention

[0004] The technical problem solved by the present invention is how to improve the performance of semiconductor devices.

[0005] To solve the above technical problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, having at least two selection gates on the substrate, adjacent to the selection gates, with an opening between adjacent selection gates, the selection gates are arranged along a first direction, and the first direction is parallel to the surface of the substrate; forming a floating gate layer on the surface of the opening and on the top surface of the selection gate; forming a first sacrificial layer in the opening and on the surface of the floating gate layer on the top of the selection gate; forming a second sacrificial layer on the first sacrificial layer, the thickness of the first sacrificial layer ranges from 1000 angstroms to 2000 angstroms, and the thickness of the second sacrificial layer ranges from 800 angstroms to 1000 angstroms.

[0006] Optionally, the process for forming the second sacrificial layer is a chemical vapor deposition process, and the parameters of the chemical vapor deposition process are: a deposition rate of 4000 angstroms per minute to 5000 angstroms per minute, and a deposition time of 10 seconds to 15 seconds.

[0007] Optionally, after the step of forming a second sacrificial layer, the step further includes: forming a photoresist layer having a floating gate pattern on the second sacrificial layer; using an etching process with an etching selectivity ratio, sequentially etching the photoresist layer, the second sacrificial layer, the first sacrificial layer and a portion of the floating gate layer to form a plurality of floating gates, wherein the floating gates span the select gates and are arranged along a second direction, and the second direction is perpendicular to the first direction.

[0008] Optionally, before the step of forming the photoresist layer, the method further includes: forming an anti-reflection layer on the second sacrificial layer; and after forming the select gate, the method further includes: forming a third sacrificial layer on the surface of the select gate and the surface of the substrate.

[0009] Optionally, the material of the first sacrificial layer is amorphous carbon, and the material of the second sacrificial layer is silicon dioxide; the thickness of the photoresist layer ranges from 2000 angstroms to 3000 angstroms, the thickness of the third sacrificial layer ranges from 300 angstroms to 500 angstroms, and the material of the third sacrificial layer is silicon oxide.

[0010] Optionally, the substrate includes adjacent first and second regions, the select gate spans the first and second regions, and the first and second regions are arranged along the second direction.

[0011] Optionally, an etching process with an etching selectivity ratio is used to sequentially etch the photoresist layer, the second sacrificial layer, the first sacrificial layer and a portion of the floating gate layer to form a plurality of floating gates, the steps comprising: exposing and developing the photoresist until the surface of the anti-reflection layer on the second region is exposed to form a photoresist layer having a floating gate pattern; a first sub-etching process is used to etch and remove the anti-reflection layer, the second sacrificial layer, the first sacrificial layer, the floating gate layer, a portion of the third sacrificial layer, and the photoresist layer, the anti-reflection layer, and a portion of the second sacrificial layer on the first region to expose the surface of the third sacrificial layer on the second region and the surface of the second sacrificial layer on the first region; a second sub-etching process is used to etch and remove a portion of the third sacrificial layer on the second region and all of the second sacrificial layer on the first region to expose the surface of the third sacrificial layer on the second region and the surface of the first sacrificial layer on the first region; a third sub-etching process is used to etch and remove the first sacrificial layer on the first region to expose the surface of the third sacrificial layer on the second region and the surface of the floating gate layer on the first region to form a floating gate.

[0012] Optionally, the first etching process is a plasma dry etching process, and the process parameters of the first etching process include: the etching gas is CF 4 , CHF 3 , CH 3 F.O 2 , Ar, the gas flow rate of the etching gas is 100 sccm to 500 sccm, the bias voltage is 100V to 200V, the etching pressure is 30mTorr to 40mTorr, the etching time is 30 seconds to 45 seconds, and the first sub-etching process has an etching selectivity of 1:0 for the first sacrificial layer on the second zone and the second sacrificial layer on the first zone.

[0013] Optionally, the second sub-etching process is a wet etching process, and the process parameters of the wet etching process are: the etching solution includes a combination of one or more of hydrofluoric acid solution, ammonia solution and water, the reaction temperature ranges from 20 degrees Celsius to 25 degrees Celsius, and the reaction time is 3 minutes to 4 minutes. The second sub-etching process has an etching selectivity ratio of 2:1 to 2.5:1 for the second sacrificial layer on the first zone and the third sacrificial layer on the second zone.

[0014] Optionally, the third sub-etching process is a plasma stripping process, and the process parameters of the third sub-etching process include: the etching gas is a combination of one or more of CF4, CHF3, CH3F, O2, and Ar, the gas flow rate of the etching gas is 100 sccm to 500 sccm, the bias voltage is 100 V to 200 V, the etching pressure is 30 mTorr to 40 mTorr, and the etching time is 30 seconds to 45 seconds. The third sub-etching process has an etching selectivity ratio of 1:0 for the first sacrificial layer on the first zone and the third sacrificial layer on the second zone.

[0015] Compared with the prior art, the technical solution of the embodiment of the present invention has the following beneficial effects:

[0016] The present invention adopts a first sacrificial layer and a second sacrificial layer as sacrificial layers for forming a floating gate. Compared with the solution in the prior art that only uses the first sacrificial layer as the sacrificial layer for forming a floating gate, the thickness of the first sacrificial layer is reduced, and a second sacrificial layer with good step coverage and gap filling capability is formed on the first sacrificial layer, thereby reducing the possibility of voids and improving the performance of semiconductor devices.

[0017] Furthermore, since the first sacrificial layer and the second sacrificial layer are etched using an etching process with an etching selectivity ratio, the second sacrificial layer can serve as a barrier layer for the first sacrificial layer when the floating gate layer on the opening is subsequently etched, thereby avoiding damage to the active area caused by over-etching of the floating gate and ensuring the integrity of the floating gate.

[0018] Furthermore, the present invention increases the thickness of the photoresist layer and the etching time of the photoresist on the top surface of the selection gate, so that when the first sacrificial layer on the opening is subsequently etched, the second sacrificial layer on the top surface of the selection gate is not completely removed, and the second sacrificial layer serves as a blocking layer to ensure the integrity of the floating gate formed subsequently.

[0019] Furthermore, the present invention forms a third sacrificial layer on the surface of the selection gate and the surface of the substrate, so that after the floating gate is subsequently formed and the first sacrificial layer and the second sacrificial layer on the selection gate need to be removed, the third sacrificial layer can act as a barrier layer to protect the substrate from being etched, thereby avoiding damage to the active area and improving the performance of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 It is a schematic diagram of the formation process of a semiconductor structure;

[0021] Figures 2 to 22 It is a schematic diagram of the memory structure formation process in an embodiment of the present invention. DETAILED DESCRIPTION

[0022] It should be noted that the terms “surface” and “on” in this specification are used to describe relative positional relationships in space and are not limited to direct contact.

[0023] The current formation process of floating gate flash memory is as follows Figure 1 As shown, it includes: providing a substrate 100, on which at least two selection gates 101 are provided, and there is an opening between adjacent selection gates 101, and the selection gates 101 are arranged along a first direction X, and the first direction X is parallel to the surface of the substrate 100; forming a floating gate layer 102 on the surface of the opening and the top surface of the selection gate 101; forming a first sacrificial layer 103 in the opening and on the top surface of the selection gate 101; and forming a first anti-reflection layer 104 on the first sacrificial layer 103.

[0024] In the above scheme, in the process of filling amorphous carbon (i.e., the first sacrificial layer) into the opening, there is a void 105 and it is not sealed, resulting in a thin photoresist layer formed on the surface of the void 105. In the subsequent photo rework process, part of the amorphous carbon will be removed, and the first anti-reflective layer 104 is not removed in this process, resulting in the wafer being scrapped.

[0025] At present, the problem of voids in the above openings is solved by increasing the thickness of amorphous carbon so that the voids at the top can be sealed. However, the increase in the thickness of amorphous carbon will increase the amount of oxygen required to be introduced in the subsequent removal of the amorphous carbon, and the oxygen will form an oxide layer with the surface of the floating gate layer. In the subsequent process of removing the oxide layer, the amount of oxygen required to be introduced will increase. 4 The amount of the floating gate layer at the bottom of the opening is reduced, which may lead to over-etching of the floating gate, resulting in the risk of active area damage (ie, AA damage), affecting the performance of the semiconductor device.

[0026] In order to solve the above technical problems, the present invention provides a method for forming a semiconductor structure, by filling a first sacrificial layer and a second sacrificial layer with a flow ratio in an opening on a floating gate, so that the first sacrificial layer and the second sacrificial layer can better fill the opening, and the first sacrificial layer and the second sacrificial layer are used as sacrificial layers, which reduces the thickness of the first sacrificial layer, avoids the occurrence of voids, and improves the performance of the semiconductor device.

[0027] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0028] Please refer to Figure 2 , Figure 3 as well as Figure 4 , Figure 2 It is a top view. Figure 3 yes Figure 2 The cross-sectional view along line AA1 is shown in Figure 2. Figure 4 yes Figure 3 In the cross-sectional view along line BB1, a substrate 200 is provided, wherein the substrate 200 includes a first region I and a second region II adjacent to each other; a selection gate layer 2021 is formed on the substrate 200; and a selection gate dielectric layer 2022 is formed on the selection gate layer 2021.

[0029] In this embodiment, the second region II includes a plurality of separate isolation regions 201 .

[0030] In some embodiments, the material of the selection gate layer 2021 includes one or more combinations of single crystal silicon, polycrystalline silicon, amorphous silicon, hafnium oxide, iridium oxide, and ruthenium oxide, and the material of the selection gate dielectric layer 2022 is silicon dioxide.

[0031] Please refer to Figure 5 , Figure 6 as well as Figure 7 , Figure 5 It is a top view. Figure 6 yes Figure 5 The cross-sectional view along line AA1 is shown in Figure 2. Figure 7 yes Figure 5 In the cross-sectional view along line BB1, a photoresist layer (not shown) having a select gate pattern is formed on the select gate dielectric layer 2022 to form a select gate located on the substrate 200, and the select gate is arranged along a first direction X, which is parallel to the surface of the substrate 200.

[0032] In this embodiment, the selection gate 202 includes: a selection gate layer 2021 and a selection gate dielectric layer 2022 located on the selection gate layer 2021 .

[0033] In some embodiments, at least two selection gates 202 are disposed on the substrate 200 , and an opening 2023 is disposed between adjacent selection gates 202 .

[0034] Please refer to Figure 8 , Fig. 9 as well as Fig.10 , Figure 8 It is a top view. Fig. 9 yes Figure 8 The cross-sectional view along line AA1 is shown in Figure 2. Fig.10yes Figure 8 In the cross-sectional view along line BB1, a floating gate layer 205 is formed on the surface of the opening 2023 and the top surface of the select gate.

[0035] The material of the floating gate layer 205 includes: single crystal silicon, polycrystalline silicon, amorphous silicon, hafnium oxide, iridium oxide, ruthenium oxide or one or more combinations thereof.

[0036] In this embodiment, before forming the floating gate layer 205 , the process further includes: forming a spacer 203 on the sidewall of the select gate 202 .

[0037] In some embodiments, the sidewall 203 is an ONO structure, and the sidewall 203 includes a silicon oxide layer 2031 located on the sidewall of the select gate, a silicon nitride layer 2032 located on the sidewall of the silicon oxide layer 2031, and a third sacrificial layer 2033 located on the silicon nitride sidewall, the top surface of the select gate, and the surface of the substrate 200.

[0038] The material of the third sacrificial layer 2033 is silicon oxide, and the thickness of the third sacrificial layer 2033 is in a range of 300 angstroms to 500 angstroms.

[0039] In some embodiments, the process for forming the third sacrificial layer 2033 is a high temperature thermal oxidation process (HTO process), and the process parameters are a deposition rate of 1.5 angstroms per minute to 2.5 angstroms per minute and a deposition time of 12,000 seconds to 20,000 seconds.

[0040] In the above scheme, the third sacrificial layer 2033 is formed on the surface of the selection gate and the surface of the substrate 200, so that after the subsequent formation of the floating gate and the need to remove the first sacrificial layer 206 and the second sacrificial layer 207 on the selection gate, the third sacrificial layer 2033 can act as a barrier layer to protect the substrate 200 from being etched, thereby avoiding damage to the active area and improving the performance of the device.

[0041] Please refer to Fig.11 , Fig.12 as well as Fig.13 , Fig.11 It is a top view. Fig.12 yes Fig.11 The cross-sectional view along line AA1 is shown in Figure 2. Fig.13 yes Fig.11 In the cross-sectional view along line BB1 ​​in FIG. 1 , a first sacrificial layer 206 is formed in the opening 2023 and on the surface of the floating gate layer 205 at the top of the select gate, and a second sacrificial layer 207 is formed on the first sacrificial layer 206 .

[0042] In some embodiments, the material of the first sacrificial layer 206 is amorphous carbon, and the material of the second sacrificial layer 207 is silicon dioxide or TEOS.

[0043] Of course, the present invention is not limited thereto, and other materials having good gap filling and morphology planarization properties are within the protection scope of the present invention.

[0044] In this embodiment, the process for forming the first sacrificial layer 206 is a chemical vapor deposition process, and the process parameters are a deposition temperature of 400° C., a deposition rate of 3500 angstroms per minute to 4500 angstroms per minute, and a deposition time of 13 seconds to 34 seconds.

[0045] In the above scheme, a first sacrificial layer 206 and a second sacrificial layer 207 with a flow ratio are used as sacrificial layers for forming a floating gate, so that the first sacrificial layer 206 and the second sacrificial layer 207 can be better filled in the opening 2023. Compared with the scheme in the prior art that only the first sacrificial layer 206 is used as the sacrificial layer for forming a floating gate, the thickness of the first sacrificial layer 206 is reduced, and a second sacrificial layer 207 with good filling performance is formed on the first sacrificial layer 206, thereby reducing the possibility of voids and improving the performance of the semiconductor device.

[0046] In addition, since the first sacrificial layer 206 on the first region I has a high selectivity when etching the floating gate layer 205 on the second region II, that is, the first sacrificial layer 206 on the first region I is basically not etched when etching the floating gate layer 205 on the second region II, the first sacrificial layer 206 can be used as a hard mask layer for the floating gate layer 205, thereby ensuring that the floating gate layer 205 under the first sacrificial layer 206 on the first region I is not affected by the etching, thereby ensuring the integrity of the subsequently formed floating gate.

[0047] In this embodiment, the process for forming the second sacrificial layer 207 is a chemical vapor deposition process, and the parameters of the chemical vapor deposition process are: a deposition rate of 4000 angstroms per minute to 5000 angstroms per minute, and a deposition time of 10 seconds to 15 seconds.

[0048] In this embodiment, after forming the second sacrificial layer 207 , the method further includes: forming an anti-reflection layer 208 on the second sacrificial layer 207 ; and forming a photoresist layer 209 on the anti-reflection layer 208 .

[0049] Please refer to Fig.14 as well as Fig.15 , Fig.14 It is a top view. Fig.15 yes Fig.14 In the cross-sectional view along line BB1, the photoresist layer 209 is exposed and developed to expose the anti-reflection layer 208 in the second region II, thereby forming a photoresist layer 209 on the first region I, wherein the photoresist layer 209 has a floating gate pattern.

[0050] In some embodiments of the present invention, an etching process with an etching selectivity ratio will be subsequently used to sequentially etch the photoresist layer 209, the anti-reflection layer 208, the second sacrificial layer 207, the first sacrificial layer 206, the third sacrificial layer 2033 on the second region II, and the floating gate layer 205 on the second region II to form a plurality of floating gates 2051.

[0051] The thickness of the photoresist layer 209 is in a range of 2000 angstroms to 3000 angstroms.

[0052] In the above scheme, by increasing the thickness of the photoresist layer 209 and increasing the etching time of the photoresist on the top surface of the selection gate, the second sacrificial layer 207 on the top surface of the selection gate is not completely removed while the first sacrificial layer 206 on the opening 2023 is subsequently etched. The second sacrificial layer 207 serves as a blocking layer to ensure the integrity of the floating gate 2051 formed subsequently.

[0053] Please refer to Fig.16 as well as Fig.17 , Fig.16 The viewing direction and Fig.12 The viewing direction is the same as Fig.17 The viewing direction and Fig.15 The viewing direction is the same, and a first sub-etching process is used to etch and remove the anti-reflection layer 208, the second sacrificial layer 207, the first sacrificial layer 206, the floating gate layer 205 on the second region II, and the photoresist layer 209, the anti-reflection layer 208, and part of the second sacrificial layer 207 on the first region I, until the surface of the third sacrificial layer 2033 on the second region II and the surface of the second sacrificial layer 207 on the first region I are exposed.

[0054] In this embodiment, the first etching process is a plasma dry etching process, and the process parameters of the first etching process include: the etching gas is CF 4 , CHF 3 , CH 3 F.O 2 , Ar or one or more combinations thereof, the gas flow rate of the etching gas is 100 sccm to 500 sccm, the bias voltage is 100V to 200V, the etching pressure is 30mTorr to 40mTorr, the etching time is 30 seconds to 45 seconds, and the first sub-etching process has an etching selectivity of 1:0 for the first sacrificial layer 206 on the second region II and the second sacrificial layer 207 on the first region I.

[0055] Specifically, the photoresist layer 209 on the first region I is etched while the anti-reflection layer 208 on the second region II is etched, and the anti-reflection layer 208 on the first region I is etched while the second sacrificial layer 207 on the second region II is etched. However, since the thickness of the filled second sacrificial layer 207 is relatively thick, the second sacrificial layer 207 located on the lower surface of the anti-reflection layer 208 on the first region I will continue to be etched after the anti-reflection layer 208 on the first region I is etched. After the second sacrificial layer 207 on the first region I is etched, when the first sacrificial layer 206 on the second region II is etched, there is no second sacrificial layer 207 on the first region I as a hard mask to block, and thus the floating gate layer 205 on the first region I is also etched. Therefore, the present invention increases the thickness of the photoresist layer 209, so that when the first sacrificial layer 206 in the second region II is subsequently etched, the second sacrificial layer 207 is still retained on the first region I as a hard mask to block, so as to ensure the integrity of the floating gate layer 205 on the first region I.

[0056] Please refer to Fig.18 as well as Fig.19 , Fig.18 The viewing direction and Fig.16 The viewing direction is the same as Fig.19 The viewing direction and Fig.17 The second sub-etching process is used to etch away a portion of the third sacrificial layer 2033 on the second region II and all of the second sacrificial layer 207 on the first region I, until the surface of the third sacrificial layer 2033 on the second region II and the surface of the first sacrificial layer 206 on the first region I are exposed.

[0057] In this embodiment, the second sub-etching process is a wet etching process, and the process parameters of the wet etching process are: the etching solution includes a combination of one or more of a hydrofluoric acid solution, an ammonia solution and water, the reaction temperature ranges from 20 degrees Celsius to 25 degrees Celsius, and the reaction time is 3 minutes to 4 minutes. The second sub-etching process has an etching selectivity ratio of 2:1 to 2.5:1 for the second sacrificial layer 207 on the first region I and the third sacrificial layer 2033 on the second region II.

[0058] In the above scheme, since the second sacrificial layer 207 on the first area I and the third sacrificial layer 2033 on the second area II have an etching selectivity ratio in the second sub-etching process, that is, the etching rate of the second sacrificial layer 207 on the first area I is greater than the etching rate of the third sacrificial layer 2033 on the second area II, while the second sacrificial layer 207 on the first area I is etched, the third sacrificial layer 2033 always exists on the second area II as an etching stop layer to protect the substrate 200 on the second area II from damage.

[0059] Please refer to Fig. 20 , Fig.21 as well as Fig. 22 , Fig. 22 It is a top view. Fig. 20 yes Fig. 22 The cross-sectional view along line AA1 is shown in Figure 2. Fig.21 yes Fig. 22 In the cross-sectional view along line BB1, the first sacrificial layer 206 on the first region I is etched away by a third etching process until the surface of the third sacrificial layer 2033 on the second region II and the surface of the floating gate layer 205 on the first region I are exposed to form a floating gate.

[0060] In this embodiment, the third etching process is a plasma dry etching process, and the process parameters of the third etching process include: the etching gas is CF 4 , CHF 3 , CH 3 F.O 2 , Ar or one or more combinations thereof, the gas flow rate of the etching gas is 100 sccm to 500 sccm, the bias voltage is 100V to 200V, the etching pressure is 30mTorr to 40mTorr, the etching time is 30 seconds to 45 seconds, and the third sub-etching process has an etching selectivity of 1:0 for the first sacrificial layer 206 on the first region I and the third sacrificial layer 2033 on the second region II.

[0061] In this embodiment, the floating gate crosses the select gate, and the floating gate is arranged along a second direction Y, and the second direction Y is perpendicular to the first direction X.

[0062] In the above scheme, since the third sub-etching process has an etching selectivity ratio for the first sacrificial layer 206 on the first region I and the third sacrificial layer 2033 on the second region II, that is, the etching rate of the first sacrificial layer 206 on the first region I is greater than the etching rate of the third sacrificial layer 2033 on the second region II, while the first sacrificial layer 206 on the first region I is etched, the third sacrificial layer 2033 always exists on the second region II as an etching stop layer to protect the substrate 200 on the second region II from damage.

[0063] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of the present invention should be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, wherein the substrate has at least two selection gates, the selection gates are adjacent to each other, an opening is provided between the adjacent selection gates, the selection gates are arranged along a first direction, and the first direction is parallel to a surface of the substrate; forming a floating gate layer on the opening surface and the top surface of the select gate; forming a first sacrificial layer in the opening and on the surface of the floating gate layer at the top of the select gate; A second sacrificial layer is formed on the first sacrificial layer, wherein the thickness of the first sacrificial layer is in a range of 1000 angstroms to 2000 angstroms, and the thickness of the second sacrificial layer is in a range of 800 angstroms to 1000 angstroms.

2. The method for forming a semiconductor structure according to claim 1, wherein: The process for forming the second sacrificial layer is a chemical vapor deposition process, and the parameters of the chemical vapor deposition process are: a deposition rate of 4000 angstroms per minute to 5000 angstroms per minute, and a deposition time of 10 seconds to 15 seconds.

3. The method for forming a semiconductor structure according to claim 1, wherein: After the step of forming the second sacrificial layer, the method further comprises: forming a photoresist layer having a floating gate pattern on the second sacrificial layer; The photoresist layer, the second sacrificial layer, the first sacrificial layer and part of the floating gate layer are sequentially etched using an etching process with an etching selectivity ratio to form a plurality of floating gates, wherein the floating gates span the selection gates and are arranged along a second direction perpendicular to the first direction.

4. The method for forming a semiconductor structure according to claim 3, wherein: Before the step of forming the photoresist layer, the method further includes: forming an anti-reflection layer on the second sacrificial layer; and after forming the selection gate, the method further includes: forming a third sacrificial layer on the surface of the selection gate and the surface of the substrate.

5. The method for forming a semiconductor structure according to claim 4, wherein: The material of the first sacrificial layer is amorphous carbon, and the material of the second sacrificial layer is silicon dioxide; the thickness of the photoresist layer ranges from 2000 angstroms to 3000 angstroms, the thickness of the third sacrificial layer ranges from 300 angstroms to 500 angstroms, and the material of the third sacrificial layer is silicon oxide.

6. The method for forming a semiconductor structure according to claim 4, wherein: The substrate includes a first region and a second region adjacent to each other, the select gate spans across the first region and the second region, and the first region and the second region are arranged along a second direction.

7. The method for forming a semiconductor structure according to claim 6, wherein: The step of sequentially etching the photoresist layer, the second sacrificial layer, the first sacrificial layer and a portion of the floating gate layer using an etching process with an etching selectivity ratio to form a plurality of floating gates comprises: Performing exposure and development processing on the photoresist until the surface of the anti-reflection layer on the second area is exposed, so as to form a photoresist layer having a floating gate pattern; Using a first sub-etching process, the anti-reflection layer, the second sacrificial layer, the first sacrificial layer, the floating gate layer, a portion of the third sacrificial layer on the second region, and the photoresist layer, the anti-reflection layer, and a portion of the second sacrificial layer on the first region are etched away until a surface of the third sacrificial layer on the second region and a surface of the second sacrificial layer on the first region are exposed; Using a second partial etching process, etching away a portion of the third sacrificial layer on the second region and all of the second sacrificial layer on the first region until a surface of the third sacrificial layer on the second region and a surface of the first sacrificial layer on the first region are exposed; A third sub-etching process is adopted to etch and remove the first sacrificial layer on the first region until a surface of the third sacrificial layer on the second region and a surface of the floating gate layer on the first region are exposed, thereby forming a floating gate.

8. The method for forming a semiconductor structure according to claim 7, wherein: The first sub-etching process is a plasma dry etching process, and the process parameters of the first sub-etching process include: the etching gas is a combination of one or more of CF4, CHF3, CH3F, O2, and Ar, the gas flow rate of the etching gas is 100 sccm to 500 sccm, the bias voltage is 100 V to 200 V, the etching pressure is 30 mTorr to 40 mTorr, and the etching time is 30 seconds to 45 seconds. The first sub-etching process has an etching selectivity ratio of 1:0 for the first sacrificial layer on the second area and the second sacrificial layer on the first area.

9. The method for forming a semiconductor structure according to claim 7, wherein: The second sub-etching process is a wet etching process, and the process parameters of the wet etching process are: the etching solution includes a combination of one or more of hydrofluoric acid solution, ammonia solution and water, the reaction temperature ranges from 20 degrees Celsius to 25 degrees Celsius, and the reaction time is 3 minutes to 4 minutes. The second sub-etching process has an etching selectivity ratio of 2:1 to 2.5:1 for the second sacrificial layer on the first area and the third sacrificial layer on the second area.

10. The method for forming a semiconductor structure according to claim 7, wherein: The third sub-etching process is a plasma stripping process, and the process parameters of the third sub-etching process include: the etching gas is a combination of one or more of CF4, CHF3, CH3F, O2, and Ar, the gas flow rate of the etching gas is 100 sccm to 500 sccm, the bias voltage is 100V to 200V, the etching pressure is 30mTorr to 40mTorr, and the etching time is 30 seconds to 45 seconds. The third sub-etching process has an etching selectivity ratio of 1:0 for the first sacrificial layer on the first zone and the third sacrificial layer on the second zone.

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