High-speed direct digital frequency synthesizer of optimized CORDIC algorithm

Abstract

The invention discloses a high-speed direct digital frequency synthesizer based on an optimized CORDIC algorithm. The high-speed direct digital frequency synthesizer comprises a phase accumulator, a CORDIC converter and a digital-to-analog converter (DAC). Wherein the phase accumulator is responsible for accumulating input phases and properly intercepting the input phases. The CORDIC converter is based on an optimized CORDIC algorithm. The CORDIC converter is composed of a small-angle extraction module, a lookup table module, a rotation calculation module and a domain folding reduction module. The small angle extraction module converts a phase angle into a small angle within pi / 12, and the lookup table module only stores 11 groups of sine and cosine values divided for pi / 12. And the data after meter reading is firstly subjected to scaling-free processing, then is subjected to parallel three-group rotation calculation processing of a remainder four algorithm, finally, a signal is restored in the domain folding and restoring module through a sum angle formula, and finally, a digital signal is converted into an analog signal by a DAC (Digital-to-Analog Converter). By optimizing the CORDIC algorithm, the precision and speed of the frequency synthesizer are remarkably improved, and the storage requirement is greatly reduced, so that the production cost in large-scale chip manufacturing is greatly reduced.

Description

Technical Field

[0001] The present invention relates to a direct digital frequency synthesizer (DDS) based on the CORDIC (Coordinate Rotation Digital Computer) algorithm, and in particular to a high-speed DDS system that optimizes ROM usage and improves computational efficiency. The present invention particularly focuses on rapidly converging the angle to within π / 12 through fast domain folding technology, and combining with optimized lookup table compression technology to significantly reduce ROM consumption, thereby improving the accuracy and efficiency of the system. Background Art

[0002] Direct Digital Synthesis (DDS) technology is widely used to generate precise frequency and waveform signals. Its main advantages include high frequency resolution, fast conversion speed, good stability, the ability to generate a variety of waveforms, and phase continuity. The core components of a DDS system usually include a phase accumulator, a phase-to-amplitude converter, and a digital-to-analog converter (DAC). The phase accumulator is responsible for generating a phase signal that is gradually accumulated, the phase-to-amplitude converter converts these phase signals into the corresponding waveform amplitude, and the digital-to-analog converter (DAC) converts the generated digital amplitude signal into an analog signal for external use.

[0003] In traditional designs, phase-to-amplitude converters often rely on the CORDIC algorithm to achieve efficient angle calculation and waveform generation. The CORDIC algorithm iteratively calculates sine and cosine values ​​to complete the conversion of angle to amplitude. However, in order to achieve higher calculation accuracy, traditional DDS systems usually need to rely on ROM to store a large amount of lookup table data in order to quickly find the required sine and cosine values. However, this method leads to a high dependence on ROM resources, and the limited ROM resources directly limits the further improvement of the overall performance of the DDS system. In addition, the CORDIC algorithm also has bottlenecks in computational efficiency and accuracy. Especially in high-precision applications, higher phase noise and spurious signals may appear, thus affecting the quality of the output signal.

[0004] With the continuous advancement of technology and the increasing demand for high-precision applications, the calculation speed and accuracy of the traditional CORDIC algorithm can no longer meet the requirements of modern DDS systems. Researchers have proposed a variety of optimization schemes to reduce the number of iterations, reduce ROM resource consumption, and remove scaling factors. These improvements have alleviated the shortcomings of the traditional algorithm to a certain extent, but there is still room for further optimization in terms of ROM resource utilization and calculation efficiency.

[0005] In response to this challenge, the present invention proposes a high-speed direct digital frequency synthesizer based on an optimized CORDIC algorithm. The frequency synthesizer consists of a phase accumulator, a CORDIC converter and a digital-to-analog converter (DAC). The phase accumulator is responsible for accumulating the input phase and performing appropriate interception to generate an accurate phase signal. The CORDIC converter adopts an optimized CORDIC algorithm, converts the input phase angle into a small angle within π / 12 through a small angle extraction module, and uses a lookup table module to store only 11 groups of sine and cosine values ​​corresponding to the π / 12 division. This design significantly reduces the dependence on ROM and optimizes the utilization of storage resources. Subsequently, the data is processed without scaling and processed by three parallel rotation calculation modules of the remainder four algorithm, and finally the signal is restored by the sum angle formula in the domain folding restoration module. Finally, the generated digital signal is converted into an analog signal through a digital-to-analog converter (DAC).

[0006] The entire frequency synthesizer system adopts a pipeline architecture, which not only improves computational efficiency, but also significantly improves the accuracy and speed of the frequency synthesizer by optimizing the CORDIC algorithm, while significantly reducing storage requirements. This improvement greatly reduces production costs in large-scale chip manufacturing, allowing the design to better meet the needs of modern high-precision, low-spurious DDS systems. Summary of the invention

[0007] The invention provides a high-speed direct digital frequency synthesizer (DDS) based on an optimized CORDIC algorithm, aiming to solve the problems of large ROM resource consumption, low calculation efficiency and poor output signal quality in a traditional DDS system.

[0008] In order to achieve the above object, the present invention provides a high-speed direct digital frequency synthesizer based on an optimized CORDIC algorithm, comprising:

[0009] Phase accumulator, responsible for accumulating the input phase and performing appropriate interception;

[0010] A CORDIC converter for converting a phase signal into a digital amplitude signal;

[0011] A digital-to-analog converter (DAC), used to convert the digital amplitude signal output by the CORDIC converter into an analog signal;

[0012] Wherein, the CORDIC converter includes the following modules:

[0013] Small angle extraction module, used to parse the input angle information, extract quadrant, area data and corresponding small angle information;

[0014] The lookup table module uses streamlined lookup table resources to pre-store accurate sine and cosine values ​​under small angle conditions, and determines the query address by obtaining high-bit information of small angles to achieve fast retrieval;

[0015] The rotation calculation module improves the rotation matrix of the traditional CORDIC algorithm. Based on the small angle information and the sine and cosine values ​​provided by the lookup table module, it uses an iterative method without scaling factors to perform rotation approximation calculations, thus achieving efficient rotation calculations.

[0016] The angle restoration module receives the quadrant and area data provided by the small angle extraction module, generates a full range of angles through positive and negative relationships and coordinate exchange, and completes the angle restoration.

[0017] As a further improvement of the present invention, the phase accumulator includes an adding unit and an accumulating register. The adding unit is used to combine the frequency control word with the accumulated value of the previous cycle to generate a new phase value. The accumulating register is used to store the generated phase value in each clock cycle and use it as the input of the next cycle to ensure that the frequency synthesizer maintains the consistency of phase accumulation and the stable operation of the system during continuous operation. In addition, the phase accumulator also appropriately intercepts the input phase signal to meet specific accuracy requirements.

[0018] As a further improvement of the present invention, the small angle extraction module further includes an angle decoder for decoding the input phase information into quadrant, region and small angle information to guide the subsequent operations of the lookup table module and the rotation calculation module. Each quadrant is divided into six regions (A, B, C, D, E, F), and the range of each region is π / 12. The angle decoder determines the quadrant and region of the angle by parsing the high five bits of the phase information, and quickly corrects the small angle through the regional correction factor M, thereby achieving rapid convergence to less than π / 12, simplifying the amount of calculation and the scale of the lookup table.

[0019] As a further improvement of the present invention, the lookup table module is optimized by lookup table compression technology, and the sine and cosine values ​​in a small angle range (0 to π / 12) are pre-calculated and stored. By effectively dividing π / 12 into 11 groups of sine and cosine values, a small lookup table is designed. At small angles, the storage bit width of the sine and cosine values ​​can further omit the high-order 1s and 0s. This optimization significantly reduces the use of lookup tables and ROM resources, while ensuring that reference values ​​can be provided quickly and accurately during the rotation calculation process, thereby improving the overall efficiency of the system.

[0020] As a further improvement of the present invention, the optimized CORDIC algorithm is an improvement based on the traditional CORDIC algorithm. The formula of the traditional CORDIC algorithm is as follows:

[0021]

[0022] Where L is the total number of rotations; X L : The horizontal coordinate after L rotations, representing the final cosine value; Y L : The ordinate after L rotations, representing the final sine value; cosθ n and sinθ n : are the cosine and sine values ​​of the nth rotation angle respectively; x 0 and 0 : The horizontal and vertical coordinates of the initial input vector. The rotation matrix is θ is a small angle between [0,π / 12], and the corresponding formula is:

[0023]

[0024] Among them, T n ∈{0,1}, indicating the binary coding of the polarization at that angle.

[0025] The optimized CORDIC algorithm is implemented at a small angle. The rotation matrix is ​​optimized. The sixth and seventh rotation matrices use cosθ n and sinθ n The Taylor expansion of the non-scaling strategy is as follows:

[0026]

[0027] In the subsequent rotation stage, cosθ is used n and tanθ n Equivalent approximation, variation:

[0028]

[0029] As a further improvement of the present invention, the rotation calculation module uses Taylor series expansion method for approximate calculation, and optimizes the rotation matrix of each stage by combining the scaling-free algorithm and the residual four-step algorithm. In each calculation stage, the range of the rotation angle is gradually narrowed by the sine and cosine values ​​provided by the lookup table module to improve the calculation accuracy. In the middle two rotations, cosθ is used n and sinθ n Taylor expansion, and all subsequent rotation stages use cosθ n and tanθ n In addition, the rotation calculation module adopts pipeline and parallel computing architecture, which enables multi-step rotation calculation to be performed in parallel, thus significantly improving the computing efficiency and system response speed.

[0030] As a further improvement of the present invention, the angle restoration module includes an angle converter, which is used to expand the sine value of the small angle calculated within π / 12 to the full angle range through the sum angle formula of π / 6, the positive and negative relationship and the coordinate exchange, so as to ensure the rotation and transformation accuracy of the CORDIC algorithm within the full angle range.

[0031] As a further improvement of the present invention, the digital-to-analog converter (DAC) is used to convert the digital amplitude signal generated by the CORDIC converter into an analog signal to achieve final output of the signal.

[0032] Compared with the prior art, the advantages of the present invention are as follows:

[0033] The present invention achieves the following significant technical effects by using an optimized CORDIC algorithm:

[0034] 1. Improve computing efficiency and signal quality: By introducing a small-angle extraction module and an iterative rotation method without scaling factors, combined with the Taylor series expansion method and parallel computing architecture, the rotation calculation process is optimized and the calculation speed is significantly improved. In addition, through the small-angle extraction design and rotation matrix optimization, longer data bit widths can be processed, thereby effectively reducing the spurious signals and phase noise caused by phase accumulator truncation, improving the quality of the DDS output signal, and enabling the system to provide faster, more stable response capabilities and high-quality output in high-speed digital signal processing applications.

[0035] 2. Reduce ROM resource consumption: The use of lookup table compression technology and small lookup table design effectively reduces the use of ROM resources. This not only reduces the hardware cost and power consumption of the system, but also provides more resource space for high-precision calculations and optimizes the overall performance of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 The regional division and quadrant symmetry model diagram provided in the embodiment of the present application is as follows:

[0037] Figure 2 The present application embodiment provides a schematic diagram of the DDS process.

[0038] Figure 3 The CORDIC phase-to-amplitude converter flow chart provided in the embodiment of the present application is as follows:

[0039] Figure 4 This is a specific implementation diagram of the lookup table. DETAILED DESCRIPTION

[0040] In order to more clearly illustrate the technical solution of the embodiment of the present invention, the specific implementation of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that the accompanying drawings are only used to illustrate some embodiments of the present invention, and those skilled in the art can also make other similar embodiments based on these drawings without creative work.

[0041] Example: Figures 1 to 4 As shown, the present invention discloses a high-speed direct digital frequency synthesizer based on an optimized CORDIC algorithm. The direct digital frequency synthesizer includes a phase accumulator, a CORDIC converter and a digital-to-analog converter. The phase accumulator is responsible for accumulating the input phase and performing appropriate interception, the CORDIC converter converts the phase signal into a digital amplitude signal, and the digital-to-analog converter is responsible for converting the digital amplitude signal into an analog signal.

[0042] The innovation of the present invention is that, by optimizing each key module of the CORDIC algorithm, the calculation interval is quickly converged to within π / 12, and a lookup table that only needs to store 11 groups of sine and cosine values ​​is designed. Through the scaling-free processing, combined with the parallel three-group rotation calculation of the remaining four algorithm, the signal is finally restored by the sum angle formula in the domain folding restoration module, and finally the digital signal is converted into an analog signal through a digital-to-analog converter (DAC). The whole process adopts a pipeline architecture to achieve efficient signal processing. By optimizing the CORDIC algorithm, the present invention not only significantly improves the accuracy and speed of the frequency synthesizer, but also greatly reduces the storage requirements, greatly reducing the production cost in large-scale chip manufacturing.

[0043] The phase accumulator includes a 24-bit full adder and a 24-bit accumulation register. At the rising edge of each clock cycle, the 24-bit full adder adds the phase data stored in the accumulation register to the input frequency control word (Frequency Control Word, FCW), and the addition result is stored in the accumulation register so that the accumulation operation can continue at the next clock rising edge. Through this linear accumulation operation, the phase accumulator can generate a gradually increasing phase signal, and its increasing speed is determined by the size of the frequency control word. In order to ensure the accuracy of the phase signal and optimize the utilization of system resources, the accumulation result is processed by 19-bit truncation, retaining the most representative high-bit phase information while removing redundant low-bit information. This truncation process effectively reduces the data width of the accumulator output while maintaining the phase accuracy required by the system.

[0044] Specifically, after the 24-bit accumulation result is truncated by 19 bits, the high-bit portion is retained for subsequent processing, such as the sine or cosine calculation of the signal. The truncation operation of the phase accumulator is implemented through a hardware logic circuit, and a simple bit selection module is introduced in the design to ensure that the high 19-bit phase information output by the 24-bit accumulator is accurately transmitted to the subsequent signal processing unit.

[0045] In applications, phase accumulators are often used in direct digital synthesizers (DDS), and the phase signal they output is used to control the output frequency of the DDS. The bit width selection and truncation strategy of the phase accumulator are one of the key design factors to ensure the accuracy of the DDS output signal and system efficiency. Due to the symmetry of the sinusoidal signal, the upper two bits of the phase signal are used for quadrant selection, and each quadrant is further divided into six regions, each corresponding to an angle of π / 12. Through the third to fifth bits of information in the phase accumulator result, combined with the correction factor M, the system can quickly determine the quadrant and region it is in.

[0046] The CORDIC converter is used to convert the phase signal output by the phase accumulator into an accurate digital amplitude signal. The CORDIC converter includes the following four functional modules, which work together to achieve efficient signal processing and frequency synthesis:

[0047] In order to more clearly illustrate the technical solution of the present invention, the small angle extraction module in the CORDIC converter is described in detail below. The main function of this module is to quickly determine the quadrant and region where the phase signal is located, and convert the angle to a small angle within π / 12. This process is crucial to the execution efficiency of the subsequent CORDIC algorithm.

[0048] In an embodiment of the present invention, the phase signal is first processed by quadrant and region division. The phase of the signal is usually divided into multiple quadrants and regions to simplify the calculation process. In this design, each quadrant is further divided into six regions, each covering an angle range of π / 12. Through this division, the calculation complexity can be effectively reduced and the processing speed can be improved.

[0049] Specifically, the angle value of π / 12 is represented as the binary number 0000101010101010101, and the corresponding angle values ​​of π / 6 and π / 3 can be obtained through simple shift operations. For example, π / 6 can be obtained by shifting the binary value of π / 12 left by one bit, while π / 3 can be obtained by shifting left by two bits. This numerical representation method not only simplifies the hardware implementation, but also makes the rapid judgment and conversion of the area more efficient.

[0050] In order to improve the accuracy and speed of calculation, the system also stores a constant correction factor M=14'b0101010101010101. This correction factor plays a key role in determining the region where the phase signal is located. By combining the third to fifth bits of information output by the phase accumulator, the system can quickly determine the specific region where the phase signal is located. Among the eight possible regions (000 to 111) initially divided, this embodiment only processes six of them (A, B, C, D, E, F), of which the four key regions are 001, 010, 101 and 110. These regions have higher computing requirements and require more computing resources, so an optimized logical judgment method is adopted.

[0051] The specific process of region judgment includes comparing the phase accumulator output P[13:0] with the correction factor M, or with the result of M shifted right by one bit (M>>1), to determine the specific region the signal is in. This design greatly simplifies the judgment logic and improves the overall operating speed and efficiency of the system.

[0052] After the regional judgment, the system enters the regional calculation logic processing stage. According to the six regions (A, B, C, D, E, F) in which it is located, the signal processing logic of each region is different to ensure the accuracy of the extracted small angle σ.

[0053] For regions A and F, the small angle σ is extracted by intercepting the high bits and inverting them. This method is concise and efficient, and is suitable for the signal processing requirements of these regions. For regions B and D, the small angle σ is calculated using the expression ~P[14:0]+{~M,1'b1}, where ~P represents the bitwise inversion of P, M is the correction factor, and the addition operation is used to adjust the result to meet the specific calculation requirements in the region.

[0054] For regions C and E, the extraction of the small angle σ is achieved by the expression P[15:0]±{2'b01,M}. The addition and subtraction operations here ensure that the 16th bit of the calculation result is 0, and only the last 15 bits are retained to ensure calculation accuracy. This method better adapts to the phase signal characteristics in regions C and E.

[0055] Regardless of the region, all of these computational logics rely on basic arithmetic operations such as addition, bitwise XOR, bit concatenation, and shift operations. These operations are efficiently implemented in hardware, further improving the overall processing speed of the system.

[0056] In an embodiment of the present invention, the lookup table module of the CORDIC converter is optimized by lookup table compression technology, and the sine and cosine values ​​in a small angle range (0 to π / 12) are pre-calculated and stored. By effectively dividing the π / 12 angle into 11 groups of sine and cosine values, a small lookup table is designed. When processing small angles, the storage bit width of the sine and cosine values ​​can further omit the high-order 1s and 0s. This optimization significantly reduces the use of lookup tables and ROM resources, while ensuring that reference values ​​can be provided quickly and accurately during the rotation calculation process, thereby improving the overall efficiency of the system.

[0057] In this design, the input of the lookup table module is derived from the upper four bits of the small angle. Since the binary representation of the π / 12 angle is 15'b101010101010101, the range of its upper four bits is limited to 0000 to 1010, so the lookup table only needs to contain 11 addresses. In these 11 addresses, the corresponding cosine and sine values ​​are pre-stored, and these values ​​are represented in unsigned 16-bit binary form.

[0058] In order to simplify the subsequent selection process and optimize the data storage structure, the present invention selects a specific format for the actual angle in the storage part, that is, it uses the form of XXXX01100100100 for calculation. Based on the limitation of π / 12, the high four bits of the decimal part of the cosine value are always 1111, while the high bit of the decimal part of the sine value is always 0. This feature allows further streamlining of the storage bit width and reducing the amount of memory used.

[0059] During the reading process, the actual storage format of the cosine value is {4'b1111,cos rom}, and the actual storage format of the sine value is {1'b0,sin rom}. Among them, cos rom Represents the cosine value stored in the lookup table, sin rom Represents the sine value stored in the lookup table. This storage method not only greatly reduces the storage bit width requirement, but also provides sufficient flexibility to further adjust the storage bit width according to the accuracy requirements.

[0060] In the embodiment of the present invention, the rotation calculation module in the CORDIC converter significantly improves the efficiency of the rotation calculation by combining the scale-free CORDIC algorithm and the remainder four algorithm, avoiding the deficiency of the traditional CORDIC algorithm that needs to introduce a scaling factor. Specifically, in the rotation iteration process, the first five rotation calculations use domain restoration and symmetry processing, and a small lookup table is established to quickly find the required sine and cosine values. In the sixth and seventh rotations, the scale-free CORDIC algorithm is used, and the Taylor expansion of cosθ is used. n and sinθ nPerform approximate calculations.

[0061] The formula of the traditional CORDIC algorithm is as follows:

[0062]

[0063] Where L is the total number of rotations; X L : The horizontal coordinate after L rotations, representing the final cosine value; Y L : The ordinate after L rotations, representing the final sine value; cosθ n and sinθ n : are the cosine and sine values ​​of the nth rotation angle respectively; x 0 and 0 : The horizontal and vertical coordinates of the initial input vector. The rotation matrix is θ is a small angle between [0,π / 12], and the corresponding formula is:

[0064]

[0065] Among them, T n ∈{0,1}, indicating the polarization recoding at the angle.

[0066] The optimized CORDIC algorithm proposed in the present invention is implemented at a small angle. The rotation matrix is ​​optimized. The sixth and seventh rotation matrices use cosθ n and sinθ n The Taylor expansion of is used to perform a scaling-free strategy, avoiding the introduction of scaling factors in traditional algorithms, thereby improving calculation accuracy and efficiency. The optimized rotation matrix is ​​as follows:

[0067]

[0068] In the subsequent rotation stage, cosθ is used n and tanθ n Equivalent approximation, variation:

[0069]

[0070] Table 1 shows the approximate values ​​for common rotation angles, where i is the number of rotations.

[0071] Table 1: Common rotation angles and their approximate values

[0072] i <![CDATA[2 -i ]]> <![CDATA[cos(2 -i )]]> <![CDATA[tan(2 -i )]]> <![CDATA[sin(2 -i )]]> 5 0.03125 0.999512 0.031260 0.031245 6 0.015625 0.999878 0.015626 0.015624 7 0.007812 0.999969 0.007813 0.007812 8 0.003906 0.999992 0.003906 0.003906 9 0.001953 0.999998 0.001953 0.001953

[0073] Assuming that T7 and T8 have been determined, the rotation calculation process can be divided into four encoding cases, each of which is optimized:

[0074] Code 00:

[0075] X 00 =X d

[0076] Y 00 =Y d

[0077] Code 01:

[0078] X 00 =X d -(X d >>15)-(Y d >>7)

[0079] Y 00 =Y d -(Y d >>15)+(X d >>7)

[0080] Code 10:

[0081] X 00 =X d -(X d >>13)-(Y d >>6)

[0082] Y 00 =Y d -(Y d >>13)+(X d >>6)

[0083] Code 11:

[0084] X 00 =X d -(X d >>13)-(X d >>15)-(Y d >>6)-(Y d >>7)

[0085] Y 00 =Y d -(Y d >>13)-(Y d >>15)+(X d >>6)+(X d >>7)

[0086] In these formulas, X 00 and Y 00 represents the rotation result of the scaling and rotation module under different encoding conditions, while X d and Y dare the input results of the lookup table in the pre-rotation stage, corresponding to the cosine value and sine value respectively.

[0087] At the same time, for the eighth rotation and beyond, it can be expanded into this formula:

[0088]

[0089] During this process, T n It is the binary corresponding bit of the input angle polarization recoding. The specific method of rotation compensation is to compare the difference between the fifth and sixth bits of the extracted binary small angle and "00", and the difference between every three groups from the seventh bit and "100" for rotation compensation. The calculation of rotation compensation only relies on simple adders and shifters, making the rotation calculation more flexible and efficient.

[0090] The rotation calculation module uses Taylor series expansion method for approximate calculation, and combines the scaling-free algorithm and the cosine algorithm to optimize the rotation matrix at each stage. At each calculation stage, the range of the rotation angle is gradually narrowed by the sine and cosine values ​​provided by the lookup table module to improve the calculation accuracy. In the middle two rotations, cosθ n and sinθ n Taylor expansion, and all subsequent rotation stages use cosθ n and tanθ n In addition, the rotation calculation module adopts pipeline and parallel computing architecture, which enables multi-step rotation calculation to be performed in parallel, thus significantly improving the computing efficiency and system response speed.

[0091] In an embodiment of the present invention, the angle restoration module in the CORDIC converter is responsible for performing logical operations and conversions on small angles σ (ranging from 0 to π / 12) according to quadrant and region information to ensure accurate calculation of the final sine and cosine values ​​within the full angle range. The module uses the sine and cosine angle formulas to achieve conversion and restoration between different angle regions through a variety of combinations of small angles σ, including σ, π / 6-σ, π / 6+σ, π / 3-σ, π / 3+σ, and π / 2-σ.

[0092] Specifically, the angle restoration module combines the input small angles σ to obtain the sine and cosine values ​​in different regions. The following table shows the specific division of these angle regions and their corresponding sine and cosine value restoration formulas: Table: Angle division and restoration comparison table

[0093]

[0094] In the above formula, the key coefficient is Its value is 0.8660254038. In order to simplify the hardware implementation and improve the calculation efficiency, the present invention adopts the following approximation formula to implement:

[0095]

[0096] Through this approximation formula, a result very close to the theoretical value is obtained, thereby ensuring the accuracy of the calculation. Of course, according to the accuracy requirements, different approximation methods can also be selected or multipliers can be used to implement the coefficient.

[0097] The angle restoration module further includes an angle converter, which is used to expand the sine and cosine values ​​of the small angle calculated within π / 12 to the full angle range through the π / 6 sum angle formula and its positive and negative relationship and coordinate exchange. This transformation ensures the accuracy of the rotation and transformation of the CORDIC algorithm within the full angle range, avoiding calculation errors caused by quadrant and area changes.

[0098] Through the above design, the angle restoration module can accurately restore and calculate the sine and cosine values ​​within the full angle range, thus ensuring the high-precision output of the CORDIC converter. This module works closely with the aforementioned lookup table module, rotation calculation module, and small angle extraction module to further optimize the overall performance and efficiency of the CORDIC algorithm.

[0099] In an embodiment of the present invention, the digital-to-analog converter (DAC) is used to convert the digital amplitude signal generated by the CORDIC converter into an analog signal to achieve the final output of the signal. Specifically, the 16-bit digital signal output by the CORDIC converter will be appropriately adapted before being transmitted to the DAC to ensure the accuracy and stability of the signal. Since the digital amplitude signal generated by the CORDIC converter in the present invention is 16 bits wide, and the selected DAC is 14 bits, it is necessary to adapt the 16-bit digital signal. This processing mainly includes signal interception and scaling to ensure that the signal at the DAC input can meet its receiving capacity while retaining the accuracy of the signal to the maximum extent.

[0100] Specifically, during the signal adaptation process, the 16-bit digital signal output by the CORDIC converter is intercepted, the highest 14 bits of valid information are retained, and the lowest 2 bits of secondary information are discarded. This interception method ensures that the main information in the signal is retained, while being able to adapt to the input limitations of the 14-bit DAC. In addition, in order to further optimize the quality of the output signal, the signal may also be scaled and adjusted accordingly during the adaptation process to ensure the consistency and stability of the output signal in amplitude. The 14-bit digital signal after the adaptation process is input to the DAC, and the DAC generates a corresponding analog signal according to the input signal to complete the conversion process from digital to analog. The analog signal will be used as the final output and applied to various electronic devices or systems that require analog signals. By adopting a 14-bit DAC, the present invention not only ensures the accuracy of the output signal, but also ensures the high efficiency and low power consumption characteristics of the signal processing process.

[0101] The design concept and processing method of this digital-to-analog conversion are consistent with the overall optimization strategy of the present invention, further reducing the hardware resource consumption of the system and ensuring high-precision output of the signal, thus meeting the high-performance requirements in large-scale chip manufacturing.

[0102] The high-speed direct digital frequency synthesizer of the present invention significantly improves the computing efficiency and accuracy compared with the traditional technology by adopting the optimized CORDIC algorithm. The core of the frequency synthesizer is to gradually process the input phase data through four modules: small angle extraction, lookup table matching, scaling-free rotation calculation, and domain folding restoration, so as to achieve efficient and accurate digital amplitude signal generation. During the processing, the lookup table module only stores 11 groups of sine and cosine values. After the scaling-free processing and the optimized rotation of the four-cosine algorithm, the final signal restoration is performed through the domain folding restoration module. Due to the introduction of the pipeline architecture and parallel computing strategy, the entire system has been significantly optimized in terms of computing speed and storage requirements.

[0103] The CORDIC converter of the present invention effectively reduces the consumption of hardware resources by reducing the size of the lookup table and the number of iterations, and improves the signal generation accuracy through fine rotation calculation. This optimization not only shortens the signal processing time, but also reduces the system power consumption, and is particularly suitable for high-precision frequency synthesis in large-scale chip manufacturing.

[0104] It should be noted that the above embodiments do not limit the present invention in any form, and any technical solutions obtained by equivalent replacement or equivalent transformation shall fall within the protection scope of the present invention.

Claims

1. A high-speed direct digital frequency synthesizer based on an optimized CORDIC algorithm, characterized in that: include: Phase accumulator, responsible for accumulating the input phase and performing appropriate interception; A CORDIC converter for converting a phase signal into a digital amplitude signal; A digital-to-analog converter (DAC), used to convert the digital amplitude signal output by the CORDIC converter into an analog signal; Wherein, the CORDIC converter includes the following modules: Small angle extraction module, used to parse the input angle information, extract quadrant, area data and corresponding small angle information; The lookup table module uses streamlined lookup table resources to pre-store accurate sine and cosine values ​​under small angle conditions, and determines the query address by obtaining high-bit information of small angles to achieve fast retrieval; The rotation calculation module uses a scaling-free iterative method to perform rotation approximation calculation based on small angle information and the sine and cosine values ​​provided by the lookup table module, thereby achieving efficient rotation calculation. The angle restoration module receives the quadrant and area data provided by the small angle extraction module, generates a full range of angles through positive and negative relationships and coordinate exchange, and completes the angle restoration.

2. The high-speed direct digital frequency synthesizer based on the optimized CORDIC algorithm according to claim 1, characterized in that: The phase accumulator includes an adding unit and an accumulating register. The adding unit is used to combine the frequency control word with the accumulated value of the previous cycle to generate a new phase value. The accumulating register is used to store the generated phase value in each clock cycle and use it as the input of the next cycle to ensure that the frequency synthesizer maintains the consistency of phase accumulation and the stable operation of the system during continuous operation.

3. The high-speed direct digital frequency synthesizer based on the optimized CORDIC algorithm according to claim 1, characterized in that: The small angle extraction module includes an angle decoder, which is used to decode the input phase information into quadrant, region and small angle information to guide the subsequent operations of the lookup table module and the rotation calculation module. Each quadrant is divided into six regions (A, B, C, D, E, F), and the range of each region is π / 12. The angle decoder determines the quadrant and region of the angle by parsing the high five bits of the phase information, and quickly corrects the small angle through the region correction factor M, so as to achieve rapid convergence to below π / 12, simplifying the calculation amount and the scale of the lookup table.

4. The high-speed direct digital frequency synthesizer based on the optimized CORDIC algorithm according to claim 1, characterized in that: The lookup table module is optimized by lookup table compression technology, and pre-calculates and stores sine and cosine values ​​within a small angle range (0 to π / 12). By effectively dividing π / 12 into 11 groups of sine and cosine values, a small lookup table is designed. At small angles, the storage bit width of the sine and cosine values ​​can further omit the high-order 1s and 0s.

5. The high-speed direct digital frequency synthesizer based on the optimized CORDIC algorithm according to claim 1, characterized in that: The optimized CORDIC algorithm is an improvement based on the traditional CORDIC algorithm. The formula of the traditional CORDIC algorithm is as follows: Where L is the total number of rotations; X L : The horizontal coordinate after L rotations, representing the final cosine value; Y L : The ordinate after L rotations, representing the final sine value; cosθ n and sinθ n : The cosine and sine values ​​of the nth rotation angle respectively; x0 and y0: the horizontal and vertical coordinates of the initial input vector, the rotation matrix is θ is a small angle between [0,π / 12], and the corresponding formula is: Among them, T n ∈{0,1}, indicating the binary code of the polarization at the angle, The optimized CORDIC algorithm is implemented at a small angle. The rotation matrix is ​​optimized to achieve this. The sixth and seventh rotation matrices use cosθ n and sinθ n The Taylor expansion of the non-scaling strategy is as follows: In the subsequent rotation stage, cosθ is used n and tanθ n Equivalent approximation, variation:

6. The high-speed direct digital frequency synthesizer based on the optimized CORDIC algorithm according to claim 1, characterized in that: The rotation calculation module uses the Taylor series expansion method for approximate calculation, and optimizes the rotation matrix of each stage by combining the scaling-free algorithm and the cosine algorithm. In each calculation stage, the range of the rotation angle is gradually narrowed by the sine and cosine values ​​provided by the lookup table module to improve the calculation accuracy. In the middle two rotations, cosθ is used. n and sinθ n Taylor expansion, and all subsequent rotation stages use cosθ n and tanθ n An equivalent approximation of .

7. The high-speed direct digital frequency synthesizer based on the optimized CORDIC algorithm according to claim 1, characterized in that: The angle restoration module includes an angle converter, which is used to expand the sine value of the small angle calculated within π / 12 to the full angle range through the π / 6 sum angle formula, positive and negative relationships, and coordinate exchange, thereby ensuring the rotation and transformation accuracy of the CORDIC algorithm within the full angle range.

8. The high-speed direct digital frequency synthesizer based on the optimized CORDIC algorithm according to claim 1, characterized in that: The digital-to-analog converter (DAC) is used to convert the digital amplitude signal generated by the CORDIC converter into an analog signal.

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