Bonding method

Abstract

The invention provides a bonding method, which comprises the following steps of: providing a first silicon substrate which comprises a central region and an edge region, and forming a step at the joint of the edge region and the central region; forming a getter layer on the edge area, wherein the getter layer covers the surface and the side wall of the step; forming a plurality of cavities in a blank area of the central area; providing a second silicon substrate, and directly bonding the second silicon substrate with the surface, provided with the getter layer, of the first silicon substrate; and carrying out annealing treatment. According to the method, the first silicon substrate and the second silicon substrate are activated, so that the first silicon substrate and the second silicon substrate can realize high-quality bonding at a relatively low annealing temperature, and relatively high bonding force is kept. By forming a plurality of concave cavities and getter layers, gas such as water vapor and the like generated in a low-temperature annealing process can be quickly and effectively absorbed during escape and diffusion in any direction, so that accumulation of the gas at a bonding interface is effectively avoided, formation of holes is effectively prevented, and the reliability and stability of direct bonding are improved.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductors and relates to a bonding method. Background Art

[0002] In the field of semiconductor technology, direct bonding is a key technology for achieving high-strength and high-reliability connections between silicon wafers, and plays an irreplaceable role in improving the overall performance and stability of microelectronic and optoelectronic devices. This process uses precise mechanical alignment and hot pressing bonding technology to directly bond two or more silicon wafers without an intermediate layer, and is widely used in integrated circuits, high-precision sensors, and micro-electromechanical systems (MEMS) and other fields with extremely high precision requirements.

[0003] In the prior art, the direct bonding process between silicon wafers mainly includes two key steps: pre-bonding and annealing. In the pre-bonding stage, the surface of the silicon wafer must maintain sufficient smoothness and be free of organic contamination to facilitate precise alignment and tight fitting between silicon wafers. The subsequent annealing process is usually carried out at a high temperature of more than 800°C, the purpose of which is to promote the polymerization reaction of hydroxyl groups (-OH) on the surface of the silicon wafer, thereby forming a stable covalent bond (Si-O-Si) structure. This polymerization reaction can be represented by the following reaction formula:

[0004] Si-OH+HO-Si→Si-O-Si+H2O

[0005] This reaction helps to enhance the bonding strength between silicon wafers and provides the necessary chemical stability and mechanical strength for direct bonding between silicon wafers. As for the water molecules generated during the reaction, they will further react with the silicon wafers under high temperature conditions to generate silicon dioxide and hydrogen. The specific reaction formula is as follows:

[0006] Si+2H2O→SiO2+2H2

[0007] The water vapor and hydrogen generated during the annealing process will form voids or microgaps on the bonding interface, which will have a serious impact on the bonding quality. Therefore, annealing is usually required in a high temperature environment of more than 800°C to promote the rapid escape and diffusion of water molecules. In this high temperature environment, water molecules in the voids and gaps of the bonding interface can diffuse into the surrounding silicon dioxide, thereby generating a local vacuum. This local vacuum causes the silicon wafer to undergo plastic deformation, thereby eliminating the voids on the interface and improving the bonding quality. At the same time, high temperature will also reduce the viscosity of silicon dioxide, causing it to flow viscously, which helps to fill and eliminate microgaps, further improving the uniformity and reliability of bonding.

[0008] However, if the annealing temperature is lowered, it may not be enough to activate the chemical reaction between the hydroxyl groups (-OH) on the surface of the silicon wafer, which will not only slow down the rate of covalent bond formation, weaken the chemical bonding force between the silicon wafers, and lead to unstable bonding interfaces. At the same time, it will also limit the escape and diffusion ability of water molecules at the bonding interface, and it is very easy to form difficult-to-eliminate voids between silicon wafers. These voids will weaken the mechanical strength of the bond and may become a potential source of electrical performance degradation, seriously damaging the reliability and service life of the device.

[0009] In addition, although high-temperature annealing can enhance the bonding strength between silicon wafers, for silicon wafers containing temperature-sensitive components such as CMOS, high-temperature conditions may cause thermal stress changes in the microstructure of the device, resulting in electrical properties such as threshold voltage drift and increased leakage current, reducing the reliability of the device structure, thereby further limiting the application potential of the silicon-silicon direct bonding process in the manufacture of a wider range of semiconductor devices.

[0010] Therefore, how to provide a new bonding method to overcome the technical problems of insufficient bonding strength, poor stability and void formation at the bonding interface between silicon wafers under low-temperature annealing conditions, as well as the technical problem of thermal stress damage to temperature-sensitive components under high-temperature annealing conditions, and improve the quality and reliability of silicon-silicon direct bonding has become an important technical problem that needs to be urgently solved by technical personnel in this field.

[0011] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present application and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because they are described in the background technology section of the present application. Summary of the invention

[0012] In view of the shortcomings of the prior art described above, the object of the present invention is to provide a bonding method for solving the technical problems encountered in the prior art of silicon-silicon direct bonding, such as insufficient bonding strength, poor stability and void formation at the bonding interface between silicon wafers under low-temperature annealing conditions, and the technical problem of thermal stress damage to temperature-sensitive components under high-temperature annealing conditions.

[0013] To achieve the above object and other related objects, the present invention provides a bonding method, comprising the following steps:

[0014] Providing a first silicon substrate, the first silicon substrate comprising a central region and an edge region located outside the central region, a step is formed at a connection between the edge region and the central region, and a plane where the edge region is located is lower than a plane where the central region is located;

[0015] forming a getter layer in the edge region, the getter layer covering the surface and sidewalls of the step, and the top surface of the getter layer and the top surface of the first silicon substrate in the central region are at the same level;

[0016] forming a plurality of spaced-apart concave cavities in the blank area of ​​the central region, wherein the concave cavities open from the top surface of the first silicon substrate and extend downward to a preset depth;

[0017] Providing a second silicon substrate, and directly bonding the second silicon substrate to a side of the first silicon substrate having the getter layer;

[0018] The first silicon substrate and the second silicon substrate that have been bonded are annealed.

[0019] Optionally, the formation of the getter layer comprises the following steps:

[0020] forming a getter film layer on the first silicon substrate, wherein the getter film layer covers the central area and the edge area;

[0021] The getter film layer is planarized to expose the surface of the first silicon substrate located in the central area, and a portion of the getter film layer located in the edge area serves as the getter layer.

[0022] Optionally, the thickness of the getter film layer is greater than the height of the step.

[0023] Optionally, before planarizing the getter film layer, a step of heat treating the getter film layer is also included.

[0024] Optionally, the temperature range of the heat treatment is 300° C. to 400° C., and the time range of the heat treatment is 2 hours to 4 hours.

[0025] Optionally, the forming of the cavity comprises the following steps:

[0026] forming a photoresist layer on the first silicon substrate;

[0027] Patterning the photoresist layer to form an opening exposing the surface of the first silicon substrate, wherein the opening is located in a blank area of ​​the central region;

[0028] The first silicon substrate is etched based on the opening to form the cavity.

[0029] Optionally, before directly bonding the second silicon substrate to the side of the first silicon substrate having the getter layer, the method further includes performing an activation treatment on the surface of the first silicon substrate and the surface of the second silicon substrate.

[0030] Optionally, the activation treatment includes any one of plasma activation treatment and wet activation treatment.

[0031] Optionally, the getter layer includes any one of a TEOS layer, a metal nickel layer and a TiZrV alloy layer.

[0032] Optionally, the temperature of the annealing treatment does not exceed 400°C.

[0033] As described above, the present invention provides a bonding method, which includes the following steps: providing a first silicon substrate, the first silicon substrate including a central area and an edge area located outside the central area, a step is formed at the connection between the edge area and the central area, and the plane where the edge area is located is lower than the plane where the central area is located; forming a getter layer in the edge area, the getter layer covers the surface and sidewalls of the step, and the top surface of the getter layer is at the same level as the top surface of the first silicon substrate in the central area; forming a plurality of spaced cavities in the blank area of ​​the central area, the cavities open from the top surface of the first silicon substrate and extend downward to a preset depth; providing a second silicon substrate, directly bonding the second silicon substrate to the side of the first silicon substrate having the getter layer; and annealing the bonded first silicon substrate and the second silicon substrate. The bonding method of the present invention activates the first silicon substrate and the second silicon substrate to be bonded, so that the two can achieve high-quality bonding under low annealing temperature conditions and maintain strong bonding force. At the same time, by forming a plurality of cavities in the central area of ​​the first silicon substrate and a getter layer in the edge area, it is ensured that the gas such as water vapor generated during the low-temperature annealing process can be quickly and effectively absorbed in any direction of escape and diffusion, thereby effectively avoiding the accumulation of gas at the bonding interface, effectively preventing the formation of voids, and improving the reliability and stability of direct bonding. In addition, the bonding method of the present invention effectively avoids thermal damage or defects to semiconductor devices caused by high-temperature annealing by achieving bonding under low temperature conditions. This low-temperature bonding technology has broad application value and market prospects in precision manufacturing fields such as micro-electromechanical system devices, silicon-on-insulator devices, and piezoelectric and acousto-optic devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 Shown is a process flow chart of a bonding method of the present invention.

[0035] Figure 2 It is a schematic diagram of a cross-sectional structure after a photoresist layer is formed on the first silicon substrate in a bonding method of the present invention.

[0036] Figure 3It is a schematic diagram of a cross-sectional structure after an edge opening is formed to expose the edge region of the first silicon substrate in a bonding method of the present invention.

[0037] Figure 4 It is a schematic diagram of a cross-sectional structure after the first silicon substrate is etched based on the edge opening to form the step in a bonding method of the present invention.

[0038] Figure 5 It is a schematic diagram of the cross-sectional structure after removing the photoresist layer in a bonding method of the present invention.

[0039] Figure 6 It is a schematic diagram of a cross-sectional structure after a getter film layer is formed on the first silicon substrate in a bonding method of the present invention.

[0040] Figure 7 It is a schematic diagram of the cross-sectional structure after the getter film layer is planarized in a bonding method of the present invention.

[0041] Figure 8 It is a schematic diagram of a cross-sectional structure after a photoresist layer is formed on the first silicon substrate in a bonding method of the present invention.

[0042] Fig. 9 It is a schematic diagram of a cross-sectional structure after an opening exposing the surface of the first silicon substrate is formed in a bonding method of the present invention.

[0043] Fig.10 It is a schematic diagram of the cross-sectional structure after the cavity is formed in a bonding method of the present invention.

[0044] Fig.11 It is a schematic diagram of the cross-sectional structure after the photoresist layer is removed in a bonding method of the present invention.

[0045] Fig.12 It is a schematic diagram of a cross-sectional structure after the second silicon substrate is directly bonded to the side of the first silicon substrate having the getter layer in a bonding method of the present invention.

[0046] Component number description

[0047] 1 The first silicon substrate

[0048] 11 Central Area

[0049] 111 Cavity

[0050] 12 Marginal Area

[0051] 13 steps

[0052] 2 Photoresist layer

[0053] 21 Edge opening

[0054] 3 Photoresist layer

[0055] 31 Opening

[0056] 4 Getter film layer

[0057] 41 Getter layer

[0058] 5 Second silicon substrate

[0059] Steps S1 to S5 DETAILED DESCRIPTION

[0060] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0061] See also Figures 1 to 12 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0062] This embodiment provides a bonding method. Figure 1 , shown as a process flow chart of the method, comprising the following steps:

[0063] S1: providing a first silicon substrate, wherein the first silicon substrate comprises a central region and an edge region located outside the central region, a step is formed at a connection between the edge region and the central region, and a plane where the edge region is located is lower than a plane where the central region is located;

[0064] S2: forming a getter layer in the edge region, the getter layer covers the surface and sidewalls of the step, and the top surface of the getter layer is at the same level as the top surface of the first silicon substrate in the central region;

[0065] S3: forming a plurality of spaced-apart concave cavities in the blank area of ​​the central region, wherein the concave cavities open from the top surface of the first silicon substrate and extend downward to a preset depth;

[0066] S4: providing a second silicon substrate, and directly bonding the second silicon substrate to a surface of the first silicon substrate having the getter layer;

[0067] S5: performing annealing treatment on the first silicon substrate and the second silicon substrate after bonding.

[0068] Combine the following Figure 2-Figure 12 The specific technical scheme of each step of the bonding method of the present invention is described in detail.

[0069] First see Figure 2-Figure 5 , perform step S1: provide a first silicon substrate 1, the first silicon substrate 1 includes a central area 11 and an edge area 12 located outside the central area 11, a step 13 is formed at the connection between the edge area 12 and the central area 11, and the plane where the edge area 12 is located is lower than the plane where the central area 11 is located.

[0070] As an example, the first silicon substrate 1 may be a silicon wafer commonly used in the semiconductor manufacturing field or a silicon wafer with an insulating layer, ie, Silicon On Insulator (SOI).

[0071] Specifically, in some embodiments, the first silicon substrate 1 includes a silicon wafer and semiconductor devices fabricated on the surface of the silicon wafer, and includes various films and various structures required for these semiconductor devices. In this embodiment, the size, thickness, etc. of the first silicon substrate 1 are not excessively restricted and can be selected according to actual needs.

[0072] Specifically, the edge region 12 of the first silicon substrate 1 is a non-device area, and the size of the edge region 12 and the radial dimension of the edge region 12 from the center of the first silicon substrate 1 can be selected according to actual design and are not excessively restricted herein.

[0073] As an example, the formation of the step 13 includes the following steps:

[0074] (1) Figure 2 As shown, a photoresist layer 2 is formed on the first silicon substrate 1;

[0075] (2) Figure 3 As shown, the photoresist layer 2 is patterned to form an edge opening 21 exposing the edge region 12 of the first silicon substrate 1;

[0076] (3) Figure 4 As shown, the first silicon substrate 1 is etched based on the edge opening 21 to form the step 13 .

[0077] Specifically, the method of forming the photoresist layer 2 includes spraying, spin coating or other suitable methods.

[0078] Specifically, the photoresist layer 2 may be patterned by conventional photolithography and development processes, and the edge opening 21 exposes the surface of the first silicon substrate 1 in the edge region 12 .

[0079] Specifically, the first silicon substrate 1 may be etched by a wet etching process, a dry etching process or other suitable methods.

[0080] As an example, the height of the step 13 is in the range of 2 micrometers to 3 micrometers, that is, the thickness of the first silicon substrate 1 removed by etching in this embodiment is in the range of 2 micrometers to 3 micrometers.

[0081] As an example, the bonding method further comprises a step of removing the photoresist layer 2 .

[0082] Specifically, Figure 5 As shown, the photoresist layer 2 is removed by a stripping method or other suitable methods.

[0083] Please see again Figure 6-Figure 7 , perform the step S2: form a getter layer 41 in the edge area 12, the getter layer 41 covers the surface and sidewalls of the step 13, and the top surface of the getter layer 41 is at the same level as the top surface of the first silicon substrate 1 in the central area 11.

[0084] As an example, the formation of the getter layer 41 includes the following steps:

[0085] (1) Figure 6 As shown, a getter film layer 4 is formed on the first silicon substrate 1, and the getter film layer 4 covers the central area 11 and the edge area 12;

[0086] (2) Figure 7 As shown, the getter film layer 4 is planarized to expose the surface of the first silicon substrate 1 located in the central area 11 , and the portion of the getter film layer 4 located in the edge area 12 serves as the getter layer 41 .

[0087] As an example, the getter film layer 4 includes but is not limited to any one of a TEOS (tetraethyl orthosilicate) layer, a metal nickel layer and a TiZrV (titanium zirconium vanadium) alloy layer.

[0088] Specifically, the method for forming the getter film layer 4 includes chemical vapor deposition, physical vapor deposition, magnetron sputtering, evaporation or other suitable methods. In this embodiment, chemical vapor deposition is preferably used to form the getter film layer 4. The getter film layer 4 not only has good coverage, but also can be deposited at a lower temperature. This low-temperature deposition process helps to reduce film stress and improve the overall quality of the film.

[0089] As an example, the thickness of the getter film layer 4 is greater than the height of the step 13 .

[0090] As an example, the thickness of the getter film layer 4 is in the range of 5 micrometers to 6 micrometers.

[0091] Specifically, the getter film layer 4 covers the surface and sidewalls of the step 13 in the central region 11 and the edge region 12. That is, in this embodiment, the getter film layer 4 forms a continuous covering layer on the surface of the first silicon substrate 1, ensuring full coverage of the central region 11 and the edge region 12 of the first silicon substrate 1.

[0092] As an example, before planarizing the getter film layer 4 , the method further includes a step of heat treating the getter film layer 4 .

[0093] As an example, the temperature range of the heat treatment is 300° C. to 400° C., and the time range of the heat treatment is 2 hours to 4 hours.

[0094] Specifically, in this embodiment, the temperature for heat treatment of the getter film is preferably 400°C, and the time for heat treatment is preferably 3 hours. Through the heat treatment, on the one hand, it helps to reduce the porosity of the getter film layer 4 and eliminate possible microscopic defects, thereby ensuring the formation of a uniform and dense film structure. On the other hand, the heat treatment promotes the volatilization of water vapor and effectively prevents the formation of bubbles in the getter film layer 4 during the deposition process. These bubbles will affect the adsorption and stability of the getter film layer 4. Therefore, in this embodiment, by heat treating the getter film layer 4, it is possible to ensure that the getter film layer 4 maintains excellent adsorption performance while having good physical and chemical stability.

[0095] Specifically, the getter film layer 4 may be planarized by using a CMP (Chemical Mechanical Polishing) process or other suitable processes. In this embodiment, it is preferred to planarize the getter film layer 4 by using a CMP process. The CMP process can accurately control the removal process of the getter film layer 4, ensuring that there is no residual getter film layer 4 on the central area 11, while avoiding any damage to the surface of the first silicon substrate 1. In addition, the polishing effect of the CMP process can also significantly improve the surface quality of the first silicon substrate 1, while reducing surface defects and surface roughness, effectively eliminating particles or impurities, and providing a high cleanliness and high flatness surface for subsequent process steps.

[0096] As an example, the getter layer 41 includes but is not limited to any one of a TEOS layer, a metal nickel layer and a TiZrV alloy layer. The getter layer 41 has excellent adsorption performance and can absorb water vapor and gases such as hydrogen released during the annealing process after the first silicon substrate 1 is bonded to other silicon substrates. In this embodiment, the getter layer 41 is taken as a TEOS layer.

[0097] Please see again Figure 8-Figure 11 , executing the step S3: forming a plurality of spaced-apart concave cavities 111 in the blank area of ​​the central region 11 , wherein the concave cavities 111 open from the top surface of the first silicon substrate 1 and extend downward to a preset depth.

[0098] As an example, the formation of the cavity 111 includes the following steps:

[0099] (1) Figure 8 As shown, a photoresist layer 3 is formed on the first silicon substrate 1;

[0100] (2) Fig. 9 As shown, the photoresist layer 3 is patterned to form an opening 31 exposing the surface of the first silicon substrate 1, and the opening 31 is located in the blank area of ​​the central area 11;

[0101] (3) Fig.10 As shown, the first silicon substrate 1 is etched based on the opening 31 to form the cavity 111 .

[0102] Specifically, the method of forming the photoresist layer 3 includes spraying, spin coating or other suitable methods.

[0103] Specifically, the photoresist layer 3 is patterned by conventional photolithography and development processes to form the opening 31 . The opening 31 is located in the blank area of ​​the central region 11 , that is, the opening 31 is located in the non-device area of ​​the first silicon substrate 1 .

[0104] Specifically, the method of etching the first silicon substrate 1 includes wet etching, dry etching or other suitable methods.

[0105] As an example, the depth of the cavity 111 ranges from 2 micrometers to 5 micrometers.

[0106] As an example, the cavity 111 includes a conical cavity, a rectangular cavity, a polygonal cavity or a cavity of other suitable shapes. In this embodiment, the cavity 111 is preferably a conical cavity, and the top diameter of the cavity is greater than the bottom diameter of the cavity.

[0107] As an example, the top diameter of the cavity 111 ranges from 10 micrometers to 20 micrometers.

[0108] Specifically, the number of the concave cavities 111 can be selected according to the amount of water vapor generated during the bonding process, the wafer size, the bonding process requirements, etc., and is not limited here.

[0109] As an example, Fig.11 As shown, after forming the cavity 111, a step of removing the photoresist layer 3 is also included. Specifically, the photoresist layer 3 can be removed by a stripping method or other suitable methods.

[0110] Please see again Fig.12 , performing the step S4: providing a second silicon substrate 5, and directly bonding the second silicon substrate 5 to a side of the first silicon substrate 1 having the getter layer 41.

[0111] Specifically, the second silicon substrate 5 may also be a silicon wafer commonly used in the semiconductor manufacturing field or a silicon wafer with an insulating layer, ie, Silicon On Insulator (SOI for short).

[0112] Specifically, in some embodiments, the second silicon substrate 5 may also include a silicon wafer and semiconductor devices fabricated on the surface of the silicon wafer, and include various films and various structures required for these semiconductor devices. The size, thickness, etc. of the second silicon substrate 5 are not excessively limited here.

[0113] As an example, before directly bonding the second silicon substrate 5 to the surface of the first silicon substrate 1 having the getter layer 41 , the method further includes a step of activating the surface of the first silicon substrate 1 and the surface of the second silicon substrate 5 .

[0114] As an example, before the activation treatment is performed on the surface of the first silicon substrate 1 and the surface of the second silicon substrate 5 , the step of performing RCA standard cleaning on the first silicon substrate 1 and the second silicon substrate 5 is also included.

[0115] Specifically, in this embodiment, the first silicon substrate 1 and the second silicon substrate 5 are cleaned according to the RCA standard to remove organic or inorganic pollutants on the surfaces of the first silicon substrate 1 and the second silicon substrate 5 and provide a clean surface for subsequent activation treatment.

[0116] As an example, the activation process includes any one of a plasma activation process and a wet activation process.

[0117] Specifically, in this embodiment, the activation treatment is preferably a plasma activation treatment. The plasma activation treatment is performed to enhance the hydrophilicity of the surfaces of the first silicon substrate 1 and the second silicon substrate 5 and improve the surface energy.

[0118] As an example, the plasma activation process includes an oxygen plasma activation process.

[0119] Specifically, in this embodiment, oxygen plasma is used to activate the surface of the first silicon substrate 1 and the surface of the second silicon substrate 5 to remove organic pollutants on the surface of the first silicon substrate 1 and the second silicon substrate 5, and further activate the surface of the first silicon substrate 1 and the second silicon substrate 5. Hydroxyl groups (-OH) are formed on the surface of the first silicon substrate 1 and the surface of the second silicon substrate 5 after oxygen plasma activation treatment. These hydroxyl groups (-OH) greatly increase the hydrophilicity of the surface of the first silicon substrate 1 and the second silicon substrate 5, and significantly improve the surface energy. This enhanced hydrophilicity and improved surface energy significantly optimize the interface characteristics between the first silicon substrate 1 and the second silicon substrate 5, and provide a more compact, firm and stable bonding surface for the direct bonding of the two. At the same time, the improvement of the surface energy and hydrophilicity of the first silicon substrate 1 and the second silicon substrate 5 helps to promote viscous flow during the bonding process, thereby improving the uniformity and strength of the direct bonding of the first silicon substrate 1 and the second silicon substrate 5. In addition, a plurality of the concave cavities 111 are provided on the surface of the first silicon substrate 1. After oxygen plasma activation treatment, active sites such as hydroxyl groups (-OH) are formed on the inner surfaces of the plurality of concave cavities 111. These active sites have strong hydrophilicity. The enhanced hydrophilicity enables the concave cavities 111 to effectively absorb gases such as water vapor.

[0120] Furthermore, the oxygen plasma activation treatment can effectively improve the surface properties of the first silicon substrate 1 and the second silicon substrate 5, so that the bonding process that originally needed to be performed under high-temperature annealing can now be achieved at a lower annealing temperature, and the bonding strength meets the product's requirements for bonding strength.

[0121] Please perform the step S5: perform annealing treatment on the first silicon substrate 1 and the second silicon substrate 5 after bonding (not shown).

[0122] Specifically, the first silicon substrate 1 and the second silicon substrate 5 after bonding are annealed in a furnace tube.

[0123] As an example, the temperature of the annealing process does not exceed 400°C.

[0124] Specifically, in this embodiment, the first silicon substrate 1 and the second silicon substrate 5 treated by plasma activation can be directly bonded under low temperature annealing conditions not exceeding 400° C. and maintain strong bonding strength. This embodiment not only avoids thermal damage or defects that may be caused by high temperature annealing to the semiconductor devices in the first silicon substrate 1 and the second silicon substrate 5, but also ensures high quality of bonding.

[0125] Specifically, the water vapor and hydrogen generated during the annealing process have two diffusion paths: one is to diffuse into the inside of the first silicon substrate 1 and the second silicon substrate 5; the other is to diffuse to the edge of the substrate along the bonding interface between the two. In this embodiment, by forming the getter layer 41 that can absorb gas in the edge region 12, the water vapor and hydrogen generated at the bonding interface can diffuse to the edge of the first silicon substrate 1 and the second silicon substrate 5 along the bonding interface and be absorbed by the getter layer 41 in the edge region 12, thereby preventing the generation of edge voids. At the same time, by forming a plurality of spaced cavities 111 in the central area 11 of the first silicon substrate 1, the cavities 111 have strong hydrophilicity after plasma activation treatment, so that the water vapor and other gases generated during the annealing process can not only be absorbed by the getter layer 41 in the edge area 12, but can also be further stored or absorbed by the cavities 111 inside the first silicon substrate 1, thereby effectively improving the absorption efficiency of water vapor and other gases during silicon-silicon direct bonding under low-temperature annealing conditions, and significantly reducing the generation of bonding interface voids.

[0126] In summary, the present invention provides a bonding method, which includes the following steps: providing a first silicon substrate, the first silicon substrate including a central area and an edge area located outside the central area, a step is formed at the connection between the edge area and the central area, and the plane where the edge area is located is lower than the plane where the central area is located; forming a getter layer in the edge area, the getter layer covers the surface and sidewalls of the step, and the top surface of the getter layer is at the same level as the top surface of the first silicon substrate in the central area; forming a plurality of spaced cavities in the blank area of ​​the central area, the cavities open from the top surface of the first silicon substrate and extend downward to a preset depth; providing a second silicon substrate, directly bonding the second silicon substrate to the side of the first silicon substrate having the getter layer; and annealing the bonded first silicon substrate and the second silicon substrate. The bonding method of the present invention activates the first silicon substrate and the second silicon substrate to be bonded, so that the two can achieve high-quality bonding under low annealing temperature conditions and maintain strong bonding force. At the same time, by forming a plurality of cavities in the central area of ​​the first silicon substrate and a getter layer in the edge area, it is ensured that the gas such as water vapor generated during the low-temperature annealing process can be quickly and effectively absorbed in any direction of escape and diffusion, thereby effectively avoiding the accumulation of gas at the bonding interface, effectively preventing the formation of voids, and improving the reliability and stability of direct bonding. In addition, the bonding method of the present invention effectively avoids thermal damage or defects to semiconductor devices caused by high-temperature annealing by achieving bonding under low temperature conditions. This low-temperature bonding technology has broad application value and market prospects in precision manufacturing fields such as micro-electromechanical system devices, silicon-on-insulator devices, and piezoelectric and acousto-optic devices. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has a high industrial utilization value.

[0127] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A bonding method, characterized in that: The following steps are involved: Providing a first silicon substrate, the first silicon substrate comprising a central region and an edge region located outside the central region, a step is formed at a connection between the edge region and the central region, and a plane where the edge region is located is lower than a plane where the central region is located; forming a getter layer in the edge region, the getter layer covering the surface and sidewalls of the step, and the top surface of the getter layer and the top surface of the first silicon substrate in the central region are at the same level; forming a plurality of spaced-apart concave cavities in the blank area of ​​the central region, wherein the concave cavities open from the top surface of the first silicon substrate and extend downward to a preset depth; Providing a second silicon substrate, and directly bonding the second silicon substrate to a side of the first silicon substrate having the getter layer; The first silicon substrate and the second silicon substrate that have been bonded are annealed.

2. The bonding method according to claim 1, characterized in that: The formation of the getter layer comprises the following steps: forming a getter film layer on the first silicon substrate, wherein the getter film layer covers the central area and the edge area; The getter film layer is planarized to expose the surface of the first silicon substrate located in the central area, and a portion of the getter film layer located in the edge area serves as the getter layer.

3. The bonding method according to claim 2, characterized in that: The thickness of the getter film layer is greater than the height of the step.

4. The bonding method according to claim 2, characterized in that: Before planarizing the getter film layer, the method further includes a step of heat treating the getter film layer.

5. The bonding method according to claim 4, characterized in that: The temperature range of the heat treatment is 300° C. to 400° C., and the time range of the heat treatment is 2 hours to 4 hours.

6. The bonding method according to claim 1, characterized in that: The formation of the cavity comprises the following steps: forming a photoresist layer on the first silicon substrate; Patterning the photoresist layer to form an opening exposing the surface of the first silicon substrate, wherein the opening is located in a blank area of ​​the central region; The first silicon substrate is etched based on the opening to form the cavity.

7. The bonding method according to claim 1, characterized in that: Before directly bonding the second silicon substrate to the surface of the first silicon substrate having the getter layer, the method further includes a step of activating the surface of the first silicon substrate and the surface of the second silicon substrate.

8. The bonding method according to claim 7, characterized in that: The activation treatment includes any one of plasma activation treatment and wet activation treatment.

9. The bonding method according to claim 1, characterized in that: The getter layer includes any one of a TEOS layer, a metal nickel layer and a TiZrV alloy layer.

10. The bonding method according to claim 1, characterized in that: The temperature of the annealing treatment does not exceed 400°C.

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