Input signal processing device and method, and test system
By using the combination of input signal delay module and sampling module in Timing Generator, the complexity of traditional design is solved, and the ability to adjust the sampling time without changing the clock phase is realized, reducing the design complexity and improving the signal Sampling efficiency.
Patent Information
- Application Number
- CN202310713735.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-06-15
- Publication Date
- 2024-12-27
AI Technical Summary
When changing signal sampling points, the traditional Timing Generator has a complex design and cannot be implemented using general FPGA, which has the problem of high design complexity.
Using the combination of the input signal delay module and the sampling module, the signal delay and sampling are realized through at least two basic delay units in series, reducing the design complexity and allowing the sampling time to be adjusted without changing the driving clock phase.
The use of a general-purpose chip for input signal processing is realized, which reduces design complexity, improves the flexibility and efficiency of signal sampling, and can sample at any position within the clock cycle.
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Figure CN119210446A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of signal processing technology, and in particular to an input signal processing device, method and test system. Background Art
[0002] Timing Generator (TG) is an important component of the tester, responsible for synthesizing the output waveform according to the user's requirements and sampling the input signal according to the sampling time configured by the user. When changing the signal sampling point, the traditional Timing Generator controls the input signal sampling time by adjusting the clock phase, which must use a dedicated IC (Integrated Circuit), and the implementation structure is complex, which has the disadvantage of high design complexity. Summary of the invention
[0003] Based on this, it is necessary to provide a universal input signal processing device, method and test system that can reduce the design complexity in order to solve the above problems.
[0004] An input signal processing device, comprising:
[0005] An input signal delay module, connected to the PE module, for delaying the comparison signal output by the PE module to obtain a delayed comparison signal;
[0006] An input signal sampling module, connected to the input signal delay module, for sampling the delayed comparison signal to obtain a sampling signal;
[0007] A comparison processing module, connected to the input signal sampling module, used to determine the actual sampling value according to the sampling signal analysis, and compare and judge the actual sampling value with a preset expected value to obtain a comparison result;
[0008] Among them, the input signal delay module includes at least two basic delay units, each of the basic delay units is connected in series in sequence, the basic delay unit at the head end is connected to the PE module, and the basic delay unit at the tail end is connected to the input signal sampling module.
[0009] In one embodiment, the basic delay unit includes a direct line, a basic logic unit and a data selector. The direct line is connected in parallel with the basic logic unit, and one end is connected to the data selector, and the other end is connected to the basic delay unit of the previous level or the PE module. The data selector is connected to the basic delay unit of the next level or the input signal sampling module.
[0010] In one of the embodiments, the data selectors of adjacent basic delay units are arranged in adjacent resource blocks to achieve a minimum sampling resolution.
[0011] In one embodiment, the input signal processing device further comprises:
[0012] An input configuration module is connected to the data selector in each of the basic delay units and the input signal sampling module.
[0013] In one embodiment, the sampling signal includes a first signal and a second signal, and the comparison processing module performs a table lookup analysis based on the first signal and the second signal to determine the actual sampling value, and performs a parallel comparison and judgment based on the actual sampling value and a preset expected value to obtain a comparison result and output it.
[0014] A method for processing an input signal, comprising:
[0015] The input signal delay module delays the comparison signal output by the PE module to obtain a delayed comparison signal;
[0016] The input signal sampling module samples the delayed comparison signal to obtain a sampling signal;
[0017] The comparison processing module determines the actual sampling value according to the sampling signal analysis, and compares and judges the actual sampling value with the preset expected value to obtain a comparison result;
[0018] Among them, the input signal delay module includes at least two basic delay units, each of the basic delay units is connected in series in sequence, the basic delay unit at the head end is connected to the PE module, and the basic delay unit at the tail end is connected to the input signal sampling module.
[0019] In one embodiment, the basic delay unit includes a direct line, a basic logic unit and a data selector. The direct line is connected in parallel with the basic logic unit, and one end is connected to the data selector, and the other end is connected to the basic delay unit of the previous level or the PE module. The data selector is connected to the basic delay unit of the next level or the input signal sampling module. The input signal delay module delays the comparison signal output by the PE module, including:
[0020] The data selector of each basic delay unit selects, according to the configured parameters, to transmit the signal transmitted by the basic logic unit or the direct line in the basic delay unit to the next basic delay unit or the input signal sampling module.
[0021] In one embodiment, the sampling signal includes a first signal and a second signal, and the comparison processing module determines the actual sampling value based on the sampling signal analysis, and compares and judges based on the actual sampling value and a preset expected value to obtain a comparison result, including: performing a table lookup analysis based on the first signal and the second signal to determine the actual sampling value, and performing a parallel comparison and judgment based on the actual sampling value and the preset expected value to obtain and output the comparison result.
[0022] In one embodiment, the input signal delay module delays the comparison signal output by the PE module, and before obtaining the delayed comparison signal, it also includes:
[0023] The input configuration module sets parameters for the input signal delay module and the input signal sampling module.
[0024] A test system comprises a PE module and the above-mentioned input signal processing device.
[0025] In one of the embodiments, the PE module compares and judges the input signal fed back by the device to be tested according to a preset level threshold value, and outputs a comparison signal to the input signal delay module.
[0026] The above-mentioned input signal processing device, method and test system first delay the comparison signal output by the PE module through the input signal delay module to obtain the delayed comparison signal, and then sample the delayed comparison signal through the input signal sampling module to obtain the sampling signal. The input signal delay module includes at least two basic delay units, each of which is connected in series in sequence. The basic delay unit at the head end is connected to the PE module, and the basic delay unit at the tail end is connected to the input signal sampling module. Finally, the comparison processing module determines the actual sampling value based on the sampling signal analysis, and compares and judges the actual sampling value and the preset expected value to obtain the comparison result. By adopting the method of signal delay first and then signal sampling, the sampling time of the input signal can be adjusted without changing the driving clock phase. The input signal processing function can be implemented with a general chip, which reduces the design complexity. BRIEF DESCRIPTION OF THE DRAWINGS
[0027] Figure 1 is a structural block diagram of a test system in one embodiment;
[0028] Figure 2 It is a structural block diagram of an input signal delay module, an input signal sampling module and an input configuration module in one embodiment;
[0029] Figure 3 A schematic diagram of signal conversion of a PE module in one embodiment;
[0030] Figure 4A comparison truth table and a comparison processing principle diagram in one embodiment. DETAILED DESCRIPTION
[0031] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.
[0032] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.
[0033] It can be understood that the “connection” in the following embodiments should be understood as “electrical connection”, “communication connection”, etc. if the connected circuits, modules, units, etc. have electrical signals or data transmission between each other.
[0034] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" etc. specify the presence of stated features, wholes, operations, components, parts or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, operations, components, parts or combinations thereof.
[0035] In the current Timing Generator, if you want to sample the chip output signal at different positions, you usually need to adjust the sampling clock phase first, and then sample the chip output signal. You must design a dedicated chip to implement it, and you cannot use a general FPGA to implement it. In addition, the dedicated chip has a complex structure. Based on this, the present application provides an input signal processing device, which first delays the comparison signal output by the PE module through an input signal delay module to obtain a delayed comparison signal, and then samples the delayed comparison signal through an input signal sampling module to obtain a sampling signal. The input signal delay module includes at least two basic delay units, each of which is connected in series in sequence. The basic delay unit at the head end is connected to the PE module, and the basic delay unit at the tail end is connected to the input signal sampling module. Finally, the comparison processing module determines the actual sampling value based on the sampling signal analysis, and compares and judges the actual sampling value and the preset expected value to obtain a comparison result. By adopting the method of first signal delay and then signal sampling, the sampling moment of the input signal can be adjusted without changing the driving clock phase. The input signal processing function can be implemented using a general chip, which reduces the design complexity.
[0036] In one embodiment, Figure 1As shown, an input signal processing device is provided, including an input signal delay module 220, an input signal sampling module 230 and a comparison processing module 240, the input signal delay module 220 is connected to the PE (Pin Electronics Driver / Comparator) module 210 and the input signal sampling module 230, and the input signal sampling module 230 is connected to the comparison processing module 240.
[0037] Among them, the PE module 210 compares and judges the input signal fed back by the device under test DUT according to the preset level threshold value, and outputs the comparison signal to the input signal delay module 220. The device under test DUT can be a chip under test or other devices. The input signal delay module 220 is used to delay the comparison signal output by the PE module 210 to obtain the delayed comparison signal; the input signal sampling module 230 is used to sample the delayed comparison signal to obtain the sampling signal; the comparison processing module 240 is used to determine the actual sampling value according to the sampling signal analysis, and compare and judge according to the actual sampling value and the preset expected value to obtain the comparison result. The delay time of the input signal delay module 220 is not unique, and can be set according to the sampling time of the input signal sampling module 230. Further, the input signal processing device also includes an input configuration module 250, which is connected to the input signal delay module 220 and the input signal sampling module 230, and is used to set parameters for the input signal delay module 220 and the input signal sampling module 230.
[0038] The value of the preset level threshold value is not unique and can be adjusted during the test process. The way in which the PE module 210 compares and judges the input signal fed back by the device under test DUT according to the preset level threshold value is not unique. In one embodiment, the preset level threshold value includes a threshold value VOH and a threshold value VOL. The values of the threshold value VOH and the threshold value VOL are not unique and can be set according to actual needs, and it is only necessary to satisfy that the threshold value VOH is greater than the threshold value VOL. The PE module 210 compares and judges the input signal in combination with the threshold value VOH\threshold value VOL, and outputs the corresponding output signal CA\output signal CB. The output signal of the PE module 210 is delayed by the input signal delay module 220, and the delayed signal is sent to the input signal sampling module 230. The input signal sampling module 230 samples the two input signals based on the main sampling clock frequency, and obtains the sampled signal and sends it to the comparison processing module 240. Among them, the delay span of the input signal delay module 220 can cover the clock cycle range, ensuring that any position within the clock cycle can be sampled.
[0039] Specifically, the signal delay function of the input signal delay module 220 can be realized by the logic resources inside the FPGA. In this embodiment, the input signal delay module 220 includes at least two basic delay units, and the total delay span of all basic delay units can cover the clock cycle range, so that the sampling position can be set to any position in the clock. The basic delay units are connected in series in sequence, and the basic delay unit at the head end is connected to the PE module 210, and the basic delay unit at the tail end is connected to the input signal sampling module 230.
[0040] Further, the comparison signal output by the PE module 210 includes two output signals, the number of the input signal delay module 220 and the input signal sampling module 230 are both two, the setting parameters of the two input signal delay modules 220 may be the same or different, and the setting parameters of the two input signal sampling modules 230 may be the same or different. Through the two input signal delay modules 220 and the two input signal sampling modules 230, the two output signals of the PE module 210 are synchronously delayed and sampled. Specifically, the basic delay units connected in series in each input signal delay module 220 are respectively used as a delay chain to delay one output signal output by the PE module 210, and then each input signal sampling module 230 samples one delayed signal. Further, the sampling signal includes a first signal and a second signal, and the comparison processing module 240 performs a table lookup analysis based on the first signal and the second signal to determine the actual sampling value, and performs a parallel comparison and judgment based on the actual sampling value and the preset expected value to obtain a comparison result. Among them, the specific value of the expected value is not unique and can be changed during the test process.
[0041] Specifically, the output signal CA and the output signal CB of the PE module 210 are delayed by a delay chain respectively, and the two delayed signals are sampled by a corresponding input signal sampling module 230 respectively, and the two sampled signals are sent to the comparison processing module 240. The comparison processing module 240 can analyze the two sampled signals according to the set comparison truth table to determine the actual sampled values, and then compare and judge according to the actual sampled values and the preset expected values, and output the comparison results after obtaining them for data storage or analysis.
[0042] It can be understood that the specific structure of the basic delay unit is not unique. In this embodiment, Figure 2As shown, the input signal delay module 220 may include a basic delay unit 1, a basic delay unit 2, ..., a basic delay unit n. Each basic delay unit includes a direct line, a basic logic unit and a data selector MUX. After the direct line is connected in parallel with the basic logic unit, one end is connected to the data selector MUX, and the other end is connected to the basic delay unit or PE module 210 of the previous level. The data selector MUX is connected to the basic delay unit or input signal sampling module 230 of the next level. Specifically, in the basic delay unit located at the head end, the basic logic unit is connected to the PE module 210, and the data selector MUX is connected to the basic delay unit of the next level. In the basic delay unit located at the end, the basic logic unit is connected to the basic delay unit of the previous level, and the data selector MUX is connected to the input signal sampling module 230. In addition, the data selector MUX of each basic logic unit can also be connected to the input signal sampling module 230. The direct line delay and basic logic unit delay of each basic delay unit are both in the ps level, and there are slight differences. By connecting multiple basic delay units in series in a delay chain, the cumulative difference can cover the signal test cycle with a resolution of ps level.
[0043] The input configuration module 250 connects the data selector MUX in each basic delay unit and the input signal sampling module 230, and configures the path setting parameter sel corresponding to the required signal delay and the signal sampling selection parameter num according to the current sampling position requirement. The input signal delay module 220 delays the two output signals of the PE module 210 for a corresponding time according to the path setting parameter sel, and the input signal sampling module 230 outputs the sampling values of the two signals according to the signal sampling selection parameter num. Among them, the data selector MUX of each basic delay unit in the input signal delay module 220 selects the signal transmitted by the basic logic unit or the direct line in the basic delay unit according to the configured parameters, and transmits it to the next basic delay unit or the input signal sampling module 230, thereby controlling whether each basic delay unit delays the signal through the basic logic unit or directly transmits the signal through the direct line.
[0044] Further, in one embodiment, the data selectors of adjacent basic delay units are arranged in adjacent resource blocks. Specifically, during FPGA layout and routing, the logic of the data selector MUX of the adjacent basic delay unit is arranged in the adjacent resource block to achieve the minimum resolution. It can be understood that if the resolution requirement is not high, it is not necessary to arrange the logic of the data selector MUX of the adjacent basic delay unit in the adjacent resource block.
[0045] In addition, the comparison processing module 240 is also connected to the input configuration module 250, and after analyzing and obtaining the comparison result, the comparison result is fed back to the input configuration module 250. The input configuration module 250 adjusts the setting parameters of the input signal delay module 220 according to the comparison result, until the signal acquisition results of the two delay chains can stably feedback the time value difference corresponding to the acquisition signal jump edge to be minimized, and outputs the sampling point value at this time, so as to realize more efficient signal jump edge detection through the general chip.
[0046] For example, the input configuration module 250 can adjust the delay parameter of the input signal delay module 220 according to the comparison result and the set target comparison result until the signal transition edge is detected, and determine the performance indicator data of the input signal according to the delay parameter analysis of the input signal delay module 220. Among them, the input configuration module 250 adjusts the delay parameter of the input signal delay module 220 once and obtains the comparison result obtained by one sampling comparison. The input configuration module 250 detects two consecutive samplings according to the received comparison result, in which the first signal and the second signal are both low level in one sampling and the first signal and the second signal are both high level in the other sampling, and then determines that the signal transition edge is detected.
[0047] In this embodiment, the first signal is a signal obtained by sampling the output signal CA, and the second signal is a signal obtained by sampling the output signal CB. The target comparison result can be that the first signal and the second signal are both low level, or the first signal and the second signal are both high level. According to the comparison result output by the comparison processing module 240, it can be determined whether the first signal and the second signal are high level or low level. If both signals are high level, adjust the delay parameter of the input signal delay module 220, and expect the next comparison result to be that both signals are low level; if the first signal is low level and the second signal is high level, adjust the delay parameter of the input signal delay module 220, and expect the next comparison result to be that both signals are low level or both are high level; if both signals are low level, adjust the delay parameter of the input signal delay module 220, and expect the next comparison result to be that both signals are high level.
[0048] Taking the current comparison result that both signals are high level and the next comparison result that both signals are low level as an example, if the input signal is low level first and high level later, the delay time of the input signal delay module 220 can be reduced to detect the low level part of the input signal; if the input signal is high level first and low level later, the delay time of the input signal delay module 220 can be increased to detect the low level part of the input signal. It can be understood that according to different input signals, the input configuration module 250 will adjust the delay parameters of the input signal delay module 220 according to the comparison result and the set target comparison result, and will not be elaborated on here.
[0049] In two consecutive samplings, if the first signal and the second signal change from low level to high level at the same time, or change from high level to low level at the same time, it is considered that a signal transition edge is detected. Depending on the purpose of analysis, the input configuration module 250 determines the performance indicator data of the input signal according to the delay parameter analysis of the input signal delay module 220 in a different manner. For example, the input configuration module 250 may be to subtract the delay parameter of the input signal delay module 220 when the first signal and the second signal are both high level from the delay parameter when the first signal and the second signal are both low level, and use the difference as the performance indicator data of the input signal, which is used to analyze the duration of the input signal changing from high level to low level, or from low level to high level; the input configuration module 250 may also be to determine the range of the delay parameter of the input signal delay module 220 when the first signal and the second signal are continuously and stably detected to be both low level, and use it as the performance indicator data of the input signal, which is used to analyze the duration of the low level of the input signal; the input configuration module 250 may also be to determine the range of the delay parameter of the input signal delay module 220 when the first signal and the second signal are continuously and stably detected to be both high level, and use it as the performance indicator data of the input signal, which is used to analyze the duration of the high level of the input signal.
[0050] The above-mentioned input signal processing device first delays the comparison signal output by the PE module 210 through the input signal delay module 220 to obtain the delayed comparison signal, and then samples the delayed comparison signal through the input signal sampling module 230 to obtain the sampling signal. The input signal delay module 220 includes at least two basic delay units, each of which is connected in series in sequence. The basic delay unit at the head end is connected to the PE module 210, and the basic delay unit at the tail end is connected to the input signal sampling module 230. Finally, the comparison processing module 240 determines the actual sampling value based on the sampling signal analysis, and compares and judges the actual sampling value and the preset expected value to obtain the comparison result. By adopting the method of signal delay first and then signal sampling, the sampling time of the input signal can be adjusted without changing the driving clock phase, and a general chip can be used to implement the input signal processing function, which reduces the design complexity.
[0051] In one embodiment, an input signal processing method is also provided, including: an input signal delay module delays the comparison signal output by the PE module to obtain a delayed comparison signal; an input signal sampling module samples the delayed comparison signal to obtain a sampling signal; a comparison processing module determines the actual sampling value according to the sampling signal analysis, and compares and judges the actual sampling value and the preset expected value to obtain a comparison result. Among them, the input signal delay module includes at least two basic delay units, each basic delay unit is connected in series in sequence, the basic delay unit at the head end is connected to the PE module, and the basic delay unit at the tail end is connected to the input signal sampling module.
[0052] In one embodiment, the basic delay unit includes a direct line, a basic logic unit and a data selector. The direct line is connected in parallel with the basic logic unit, and one end is connected to the data selector, and the other end is connected to the basic delay unit or PE module of the previous level. The data selector is connected to the basic delay unit or input signal sampling module of the next level. The input signal delay module delays the comparison signal output by the PE module, including:
[0053] The data selector of each basic delay unit selects the signal transmitted by the basic logic unit or the direct line in the basic delay unit to be transmitted to the next basic delay unit or the input signal sampling module according to the configured parameters.
[0054] In one embodiment, the sampling signal includes a first signal and a second signal, and the comparison processing module determines the actual sampling value based on the sampling signal analysis, and compares and judges based on the actual sampling value and a preset expected value to obtain a comparison result, including: performing a table lookup analysis based on the first signal and the second signal to determine the actual sampling value, and performing a parallel comparison and judgment based on the actual sampling value and the preset expected value to obtain and output the comparison result.
[0055] In one embodiment, the input signal delay module delays the comparison signal output by the PE module, and before obtaining the delayed comparison signal, it also includes: an input configuration module sets parameters for the input signal delay module and the input signal sampling module.
[0056] It can be understood that the specific implementation of the above-mentioned input signal processing method has been explained in detail in the above-mentioned input signal processing device, and will not be repeated here.
[0057] In one embodiment, continue to refer to Figure 1 , a test system is also provided, including a PE module 210 and the above-mentioned input signal processing device. Among them, the PE module 210 compares and judges the input signal fed back by the device to be tested according to the preset level threshold value, and outputs the comparison signal to the input signal delay module 220. Further, the preset level threshold value includes a threshold value VOH and a threshold value VOL. The PE module 210 compares and judges the input signal in combination with the threshold value VOH\threshold value VOL, and outputs the corresponding output signal CA\output signal CB.
[0058] Specifically, the specific execution flow of input signal processing is as follows:
[0059] 1) Drive the device under test (DUT) to output signals.
[0060] 2) The PE module converts the signal output by the device under test (DUT) into output signal CA and output signal CB. Output signal CA and output signal CB are standard high and low level digital signals, such as Figure 3 As shown, when the input signal is less than the threshold value VOL, the output signal CA is at a low level and the output signal CB is at a low level; when the input signal is between the threshold value VOL and the threshold value VOH, the output signal CA is at a low level and the output signal CB is at a high level; when the input signal is greater than the threshold value VOH, the output signal CA is at a high level and the output signal CB is at a high level.
[0061] 3) According to the set sampling position information, the input configuration module calculates and outputs the path setting parameter sel of the data selector MUX of each basic delay unit and the signal sampling selection parameter num of the input signal sampling module.
[0062] 4) The input signal delay module performs delay processing on the input signal according to the path setting parameter sel to ensure that the sampling time of the input signal sampling module is the set sampling time.
[0063] 5) The input signal sampling module samples the delayed signal.
[0064] 6) The comparison processing module uses the matching comparison truth table to determine the actual sampling value according to the state value of the output signal CA\output signal CB, and then uses the actual sampling value to compare and judge with the expected value in parallel, outputs the corresponding comparison matching result, and outputs the corresponding comparison result. Figure 4 , and give the corresponding comparison result according to the actual sampling value of the output signal CA\output signal CB.
[0065] 7) The input configuration module adjusts the sent path setting parameter sel according to the matching result.
[0066] 8) Repeat steps 1 to 6 until the signal acquisition results of the two delay chains can stably feedback the time value difference corresponding to the acquisition signal jump edge to the minimum, and output the sampling point value at this time to complete the detection of the signal jump edge.
[0067] By delaying the input signal fed back by the device under test (DUT) before sampling the signal, the signal sampling position can be dynamically controlled. The signal delay does not require the clock phase switch, which reduces the complexity of the design. The delay chain is implemented using the logic resources of the FPGA. The number of delay chains that can be implemented in one FPGA is greatly increased, and the resolution of the signal transition edge detection is high, with a resolution of up to ps level. Moreover, the parallel matching truth table method is used to implement the signal parallel comparison and judgment processing. There is no need to decompose the output signal CA\output signal CB to gradually determine whether the output signal CA is consistent with the expected value, and then determine whether the output signal CB is consistent with the expected value. Instead, the actual value is determined by matching and comparing directly through the table lookup method, and then the actual value and the expected value are matched and compared to analyze whether the output result is consistent with the expectation, and the detection efficiency is high.
[0068] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0069] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.
Claims
1. An input signal processing device, characterized in that: include: An input signal delay module, connected to the PE module, for delaying the comparison signal output by the PE module to obtain a delayed comparison signal; An input signal sampling module, connected to the input signal delay module, for sampling the delayed comparison signal to obtain a sampling signal; A comparison processing module, connected to the input signal sampling module, used to determine the actual sampling value according to the sampling signal analysis, and compare and judge the actual sampling value with a preset expected value to obtain a comparison result; Among them, the input signal delay module includes at least two basic delay units, each of the basic delay units is connected in series in sequence, the basic delay unit at the head end is connected to the PE module, and the basic delay unit at the tail end is connected to the input signal sampling module.
2. The input signal processing device according to claim 1, characterized in that: The basic delay unit includes a direct line, a basic logic unit and a data selector. After the direct line is connected in parallel with the basic logic unit, one end is connected to the data selector, and the other end is connected to the basic delay unit of the previous level or the PE module. The data selector is connected to the basic delay unit of the next level or the input signal sampling module.
3. The input signal processing device according to claim 2, characterized in that: The data selectors of adjacent basic delay units are arranged in adjacent resource blocks.
4. The input signal processing device according to claim 2, characterized in that: Also includes: An input configuration module is connected to the data selector in each of the basic delay units and the input signal sampling module.
5. The input signal processing device according to claim 1, characterized in that: The sampling signal includes a first signal and a second signal. The comparison processing module performs a table lookup analysis based on the first signal and the second signal to determine the actual sampling value, and performs a parallel comparison and judgment based on the actual sampling value and a preset expected value to obtain a comparison result and output it.
6. A method for processing an input signal, characterized in that: include: The input signal delay module delays the comparison signal output by the PE module to obtain a delayed comparison signal; The input signal sampling module samples the delayed comparison signal to obtain a sampling signal; The comparison processing module determines the actual sampling value according to the sampling signal analysis, and compares and judges the actual sampling value with the preset expected value to obtain a comparison result; Among them, the input signal delay module includes at least two basic delay units, each of the basic delay units is connected in series in sequence, the basic delay unit at the head end is connected to the PE module, and the basic delay unit at the tail end is connected to the input signal sampling module.
7. The method according to claim 6, characterized in that The basic delay unit includes a direct line, a basic logic unit and a data selector. The direct line is connected in parallel with the basic logic unit, and one end of the direct line is connected to the data selector, and the other end is connected to the basic delay unit of the previous level or the PE module. The data selector is connected to the basic delay unit of the next level or the input signal sampling module. The input signal delay module delays the comparison signal output by the PE module, including: The data selector of each basic delay unit selects, according to the configured parameters, to transmit the signal transmitted by the basic logic unit or the direct line in the basic delay unit to the next basic delay unit or the input signal sampling module.
8. The method according to claim 6, characterized in that The sampling signal includes a first signal and a second signal. The comparison processing module determines the actual sampling value based on the sampling signal analysis, and compares and judges the actual sampling value with a preset expected value to obtain a comparison result, including: performing a table lookup analysis based on the first signal and the second signal to determine the actual sampling value, and performing a parallel comparison and judgment based on the actual sampling value and the preset expected value to obtain and output the comparison result.
9. The method according to any one of claims 6 to 8, characterized in that: The input signal delay module delays the comparison signal output by the PE module to obtain the delayed comparison signal, and also includes: The input configuration module sets parameters for the input signal delay module and the input signal sampling module.
10. A testing system, characterized in that: It comprises a PE module and the input signal processing device according to any one of claims 1 to 5.
11. The test system according to claim 10, characterized in that: The PE module compares and judges the input signal fed back by the device to be tested according to a preset level threshold value, and outputs a comparison signal to the input signal delay module.