N-type solar cell and preparation method thereof
By combining alkali polishing and CMP fine-polishing during the preparation of solar cells, the problem of insufficient polysilicon layer thickness is solved, the battery efficiency and production efficiency are improved, and the cost is reduced.
Patent Information
- Application Number
- CN202310788456.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-06-29
- Publication Date
- 2024-12-31
AI Technical Summary
In the prior art, the thickness of the polysilicon layer (Poly layer) cannot be made very thin, resulting in increased parasitic light absorption, reducing light utilization and cell efficiency. At the same time, the over-thick Poly layer increases raw material and preparation costs.
By combining alkaline polishing and chemical mechanical polishing (CMP) fine polishing, a smoother and smoother silicon wafer back surface is obtained, reducing the thickness of the N+Poly layer and improving its density, reducing parasitic light absorption and shortening preparation time.
It improves the light utilization rate and efficiency of solar cells, reduces raw material costs, shortens production time, and improves the passivation contact and contact performance of the battery.
Smart Images
Figure CN119230647A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of solar cells, and in particular to an N-type solar cell and a preparation method thereof. Background Art
[0002] The passivation layer on the back surface of the TOPCon cell - the Poly layer (i.e., polycrystalline silicon layer) is a parasitic light absorbing material and does not contribute to the photocurrent. However, the thickness of the Poly layer cannot be made very thin because it is necessary to ensure that the tunneling layer is not damaged during the subsequent N-type impurities (such as phosphorus doping), sputtering or injection, and printing and sintering to form metal electrodes. A thicker Poly layer will increase parasitic light absorption, reduce light utilization, and thus affect photocurrent and cell efficiency. An overly thick Poly layer will also increase raw material costs and preparation time costs.
[0003] To solve the above problems, the compactness of the Poly layer can be improved. The denser the Poly layer, the more damage it can withstand, and the better the protection for the ultra-thin tunneling layer (thickness of 1-2nm).
[0004] In the prior art, alkaline polishing is usually used to polish the back surface of the battery to obtain a flat back surface; then a method such as low-pressure chemical deposition (LPCVD) is used to prepare the Poly layer. However, the Poly layer grown using this technology cannot be dense enough and still requires a certain thickness (the thickness of the Poly layer prepared by LPCVD is 100-120nm) to resist the damage to the tunneling layer in subsequent processes. The main reason is that the alkaline polishing technology cannot achieve the ideal flatness of the back of the silicon wafer. This is because:
[0005] For the back surface of silicon wafers with low flatness, during the growth of the Poly layer, the reactants will first form a layered Poly film on the back surface of the silicon wafer; as the growth continues, heteroepitaxial growth will cause the lattice mismatch between the silicon wafer and the growing film, causing the continuously accumulated stress to reach a critical value, causing the Poly film to split and form small islands; this process is repeated many times, and eventually a thicker Poly layer is formed.
[0006] Chemical Mechanical Polishing (CMP) is a technology used in integrated circuit (IC) manufacturing to flatten the surface of wafers globally, achieving ultra-high atomic-level flatness. The chemical reagents in the CMP polishing liquid will oxidize the polishing base material to form a softer oxide film, which is then removed by mechanical friction. In this way, the purpose of efficient polishing is achieved through repeated oxidation film formation and mechanical removal. Therefore, the surface of the material treated with CMP can achieve atomic-level flatness.
[0007] However, CMP technology is rarely used in solar cell manufacturing. As shown in CN104032376A, CMP technology is mostly used in the texturing process of solar cell silicon wafers, and there is no technology for obtaining a dense and thinned Poly layer. Moreover, CMP technology usually requires three stages: rough polishing, fine polishing, and precision polishing, which is time-consuming and will greatly reduce the production efficiency of the battery. Summary of the invention
[0008] The purpose of the present invention is to overcome the deficiencies of the prior art and to provide an N-type solar cell and a method for preparing the same.
[0009] Based on this, the present invention discloses a method for preparing an N-type solar cell, comprising the following steps:
[0010] S1, doping and diffusion are performed on the silicon wafer after texturing to prepare a P+ emitter on the front side of the silicon wafer; wherein the diffusion forms borosilicate glass on both the front and back sides of the silicon wafer;
[0011] S2, single-sided pickling of the back side of the silicon wafer to remove the borosilicate glass on the back side of the silicon wafer;
[0012] S3, performing alkali polishing on the back of the silicon wafer for 150-200 seconds, so that the back of the silicon wafer forms a planar morphology and the borosilicate glass on the front of the silicon wafer is retained;
[0013] S4, using silicon polishing liquid to perform CMP fine polishing on the back of the silicon wafer, the CMP fine polishing time is 60-90s, so that the plane morphology of the back of the silicon wafer becomes more flat and smooth;
[0014] S5, sequentially preparing a tunneling layer and an N+Poly layer on the back side of the silicon wafer;
[0015] S6, cleaning the silicon wafer to remove residual organic matter, impurities on the surface of the silicon wafer and the borosilicate glass on the front side;
[0016] S7, passivating the front and back sides of the silicon wafer to prepare a front passivation anti-reflection film and a back passivation film, respectively;
[0017] S8. Metallize the front and back sides of the silicon wafer to obtain front metal electrodes and back metal electrodes, respectively.
[0018] Preferably, in step S3, the alkali polishing is performed using a KOH solution, wherein the KOH solution is prepared by mixing water and KOH in a volume ratio of 18-25:1; and the temperature of the alkali polishing is 45-65°C.
[0019] Preferably, in step S4, the silicon polishing liquid has a raw material ratio, calculated by volume fraction, of:
[0020]
[0021] Water balance.
[0022] Further preferably, in step S4, the process conditions of the CMP fine polishing are: the rotation speed of the polishing disc is 26-33r / min, the temperature is maintained at 25-30°C, the polishing rate is 0.4-0.6um / min, and the polishing pressure is 0.8-1.2N / cm 2 , the polishing pad should be made of non-woven fabric with fluff;
[0023] The polishing amount of the CMP fine polishing is 0.1-0.3 um.
[0024] More preferably, in step S5, after preparing the tunneling layer, an amorphous silicon layer doped with an N-type material is prepared on the back of the tunneling layer, and then the silicon wafer is annealed to obtain an N+Poly layer with a thickness of 75-90 nm;
[0025] The annealing treatment temperature is 800-1000° C., and the holding time is 0.5-1.5 h.
[0026] More preferably, in step S6, the silicon wafer is cleaned in sequence with a hydrogen peroxide solution, an HF solution, and a mixture of HCl and HF to remove organic matter and impurities remaining on the surface of the silicon wafer, BSG retained on the front side, and an annealed oxide layer formed by annealing.
[0027] Preferably, in step S7, the front passivation anti-reflection film comprises an Al2O3 film and a front silicon nitride film deposited in sequence; and the back passivation film is a back silicon nitride film.
[0028] Preferably, step S2 further includes using the single-sided pickling to remove the wrap-around plating caused by doping diffusion at the edge of the silicon wafer;
[0029] In step S2, the single-side pickling is performed using an HF solution, wherein the HF solution is prepared by mixing HF and water in a volume ratio of 1:1.5-2.
[0030] Preferably, in step S1, before doping and diffusion, the silicon wafer is textured to form a textured light-trapping structure on the surface of the silicon wafer.
[0031] The present invention also discloses an N-type solar cell, which is manufactured by using the method for manufacturing an N-type solar cell described above in the present invention.
[0032] Compared with the prior art, the present invention has at least the following beneficial effects:
[0033] The present invention can obtain a flatter and smoother back surface by combining the alkali polishing of step S3 with the CMP fine polishing of step S4, which can not only reduce the dangling bonds on the back surface of the silicon wafer, but also provide a better growth environment for subsequent film layers such as the tunneling layer and the N+Poly layer, so that the subsequent film layers can become flatter and smoother, thereby increasing the reflection of light by each film layer, so that the light that would have been transmitted can be reflected back to the battery again, increasing the light utilization rate. Moreover, in the subsequent preparation process of the TOPCon structure (passivation contact structure, including the tunneling layer and the N+Poly layer), the flatter and smoother back surface can also reduce the generation of anisotropic dislocations and stresses during the growth of the N+Poly layer, so that a denser and thinner N+poly layer can be obtained on the back surface of the silicon wafer; the N+poly layer can not only reduce parasitic light absorption, but also reduce the raw material cost investment of the N+Poly layer, and can also protect the tunneling layer in the subsequent steps, reduce recombination, and improve the passivation performance and contact performance of the passivation contact structure.
[0034] Therefore, the preparation method of the present invention can improve battery efficiency and reduce raw material cost input; moreover, compared with the existing CMP, it can also shorten the total time spent on polishing and improve battery production efficiency. BRIEF DESCRIPTION OF THE DRAWINGS
[0035] Figure 1 PL brightness comparison data of the batteries of Example 1 and Comparative Example 1.
[0036] Figure 2 This is a data chart comparing the thickness of the N+Poly layer in the batteries of Example 1 and Comparative Example 1.
[0037] Figure 3 It is a comparative data diagram of the battery efficiency of Example 1 and Comparative Example 1.
[0038] Figure 4 This is a schematic diagram of the cross-sectional structure of an N-type solar cell of Example 1.
[0039] Description of the accompanying drawings: silicon wafer 1; P+ emitter 2; Al2O3 film 3; front silicon nitride film 4; front metal electrode 5;
[0040] Tunneling layer 6; N+Poly layer 7; back silicon nitride film 8; back metal electrode 9. DETAILED DESCRIPTION
[0041] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.
[0042] Example 1
[0043] A method for preparing an N-type solar cell in this embodiment is shown in Figure 4 , comprising the following steps in sequence:
[0044] Step 1, texturing: texturing the silicon wafer 1 so as to form a textured light-trapping structure on the surface of the silicon wafer 1 .
[0045] In one example of this embodiment, the solution used for the texturing treatment is a mixed solution of water: KOH: ADD configured at a volume ratio of 200-250: 3: 1. For example, in the mixed solution used for the texturing treatment, the volume ratio of water: KOH: ADD is preferably 230: 3: 1. The water used in the mixed solution is preferably deionized water.
[0046] Specifically, ADD is an additive, such as isopropyl alcohol, etc. The main function of ADD is to promote the reaction between the base (such as KOH) and the surface of the silicon wafer 1, and the separation of the reaction product.
[0047] Of course, in other examples of this embodiment, other existing solutions may also be used to texture the surface of the silicon wafer 1 .
[0048] Step 2: Diffusion: doping and diffusion are performed on the silicon wafer 1 to prepare a P+ emitter 2 on the front side of the silicon wafer 1 .
[0049] The doping source for doping diffusion is preferably a boron source, such as BrCl 3. The doping diffusion process of the boron source is a prior art, so it will not be described in detail.
[0050] During the doping diffusion process, in addition to forming a P+ emitter 2 on the front side of the silicon wafer 1 , borosilicate glass (BSG) will also be formed on the front side of the P+ emitter 2 and the back side of the silicon wafer 1 , and wrap-around plating will be formed on the edge of the silicon wafer 1 .
[0051] Step 3, single-side pickling: single-side pickling is performed on the doped and diffused silicon wafer 1 to remove the borosilicate glass (BSG) on the back of the silicon wafer 1 and the wrap-around plating on the edge of the silicon wafer 1 .
[0052] In one example of this embodiment, the doped and diffused silicon wafer 1 is pickled on one side using an HF solution, wherein the HF solution is prepared by mixing HF and water in a volume ratio of 1:1.5-2. For example, the volume ratio of HF to water in the HF solution is 1:1.65.
[0053] In practice, the water used in the HF solution is preferably deionized water.
[0054] Step 4, polishing: alkaline solution (alkaline solution for short) is used to perform alkaline polishing on the back side of the silicon wafer 1 to form a smooth plane morphology on the back surface of the silicon wafer 1; and the BSG on the front side of the silicon wafer 1 is retained as a protective layer for subsequent CMP.
[0055] The BSG on the front side of the silicon wafer 1 is retained, which can protect the front side of the silicon wafer 1 to prevent the P+ emitter 2 from being damaged during the CMP treatment, and does not require additional preparation of a protective layer or mask, and does not increase additional steps.
[0056] Since CMP fine polishing will be performed later, the time of alkali polishing can be appropriately reduced in step 4, and the alkali polishing time can be reduced to 1 / 2 or 2 / 3 of the existing alkali polishing time. The existing alkali polishing time for the back side of the silicon wafer 1 is 300-350s.
[0057] In one example of this embodiment, a KOH solution is used to perform alkali polishing on the back side of the silicon wafer 1. The KOH solution is prepared by mixing water and KOH at a volume ratio of 18-25:1. The alkali polishing time is 150-200 seconds, and the alkali polishing temperature is 45-65° C. For example, the volume ratio of water to KOH in the KOH solution used for alkali polishing is 20:1, the alkali polishing time is 160 seconds, and the alkali polishing temperature is 53° C.
[0058] Step 5: CMP polishing: chemical mechanical polishing is performed on the back surface of the silicon wafer 1 to make the back surface of the silicon wafer 1 more flat and smooth.
[0059] Wherein, under the action of the polishing liquid and the polishing disk, the back surface of the silicon wafer 1 is subjected to chemical mechanical fine polishing.
[0060] The existing CMP includes three stages: rough polishing, fine polishing and precision polishing, which takes a long time. The existing alkali polishing takes a short time, but cannot obtain the back surface with ideal flatness (atomic level flatness).
[0061] Therefore, this embodiment adopts a polishing method of first alkali polishing and then CMP fine polishing, so that alkali polishing replaces the rough polishing and fine polishing stages in the existing CMP to shorten the polishing time and obtain a back surface with ideal flatness, providing conditions for the subsequent formation of a dense and thin Poly layer.
[0062] Specifically, in step 5, CMP fine polishing is performed using a silicon polishing liquid, and the formula of the silicon polishing liquid is as follows:
[0063]
[0064]
[0065] Specifically, in the CMP fine polishing of step 5, the rotation speed of the polishing disc is 26-33r / min, the temperature is maintained at 25-30°C, the polishing rate is 0.4-0.6um / min, and the polishing pressure is 0.8-1.2N / cm 2The CMP polishing time is controlled at 60-90s, and the polishing pad is a non-woven fabric with fluff. The polishing amount of CMP polishing is 0.1-0.3um, and the final total polishing amount is controlled at 0.5-0.8um.
[0066] In one example of this embodiment, the formula of the silicon polishing liquid is:
[0067]
[0068] The water in the silicon polishing liquid is preferably deionized water.
[0069] In one example of this embodiment, in the CMP fine polishing of step 5, the rotation speed of the polishing disk is 30 r / min, the temperature is 26° C., the polishing rate is 0.5 um / min, and the polishing pressure is 0.9 N / cm 2 , the CMP fine polishing time is controlled at 70s; the CMP fine polishing amount is 0.1um, and the final total polishing amount is 0.5um.
[0070] Step 6, TOPCon structure preparation: a tunneling layer and an amorphous silicon layer doped with N-type material are sequentially prepared on the back side of the silicon wafer 1 .
[0071] The preparation method of the TOPCon structure includes but is not limited to low-pressure chemical deposition, ion implantation or physical deposition. The preparation process can refer to the preparation steps of the existing TOPCon battery, so it will not be described in detail here.
[0072] Step 7, annealing: annealing the silicon wafer 1 to crystallize the amorphous silicon layer to form a Poly layer (i.e., polycrystalline silicon layer), and activate the doped atoms in the doped N-type material to obtain an N+Poly layer 7.
[0073] Specifically, the annealing temperature is 800-1000° C., and the holding time is 0.5-1.5 h.
[0074] In an example of this embodiment, the annealing temperature is 900° C. and the holding time is 1.2 h.
[0075] After the annealing treatment in step 7, the thickness of the obtained N+Poly layer 7 can be controlled to be 75-90 nm, such as 75 nm, 78 nm, 81 nm, 85 nm, 88 nm or 90 nm.
[0076] Step 8, cleaning: cleaning the silicon wafer 1 to remove organic matter, impurities, annealed oxide layer remaining on the surface of the silicon wafer 1 and BSG retained on the front side.
[0077] In one example of the present embodiment, the silicon wafer 1 is cleaned with a hydrogen peroxide solution, an HF solution, and a mixture of HCl and HF in sequence. The mixture of HCl and HF is prepared by water: HF: HCl in a volume ratio of 10-15:3:1. For example, the volume ratio of water: HF: HCl in the mixture of HCl and HF is 13:3:1. In the mixture of HCl and HF, water is preferably deionized water. The mixture of HCl and HF is mainly used to remove the BSG retained in step 4 to protect the front structure, and the cleaning time is controlled at 100-150s (such as 120s).
[0078] Step 9, coating: an Al2O3 film 3 and a front silicon nitride film 4 are sequentially prepared on the front side of the silicon wafer 1, and a back side silicon nitride film 8 is prepared on the back side of the silicon wafer 1.
[0079] In practice, TMA (trimethylaluminum) is used as a raw material to prepare the Al2O3 film 3. SiH4 and NH3 are used as precursor gases to prepare the front silicon nitride film 4 and the back silicon nitride film 8, so that the precursor gas can release atomic H to perform hydrogen passivation on the silicon wafer 1. The coating process of step 9 is a prior art and is not described in detail.
[0080] Step 10, metallization: metallization treatment is performed on the silicon wafer 1 to form a front metal electrode 5 contacting the P+ emitter 2 on the front side of the silicon wafer 1 , and a back metal electrode 9 contacting the N+Poly layer 7 on the back side of the silicon wafer 1 .
[0081] In practice, metal paste (such as silver paste) is printed on a local area of the surface of the silicon wafer 1 by screen printing and sintering to form the front metal electrode 5 and the back metal electrode 9. The metallization process is a prior art and will not be described in detail here.
[0082] After step 10, the N-type solar cell of this embodiment can be obtained. The structure of the solar cell is as follows: Figure 4 shown.
[0083] Comparative Example 1
[0084] The preparation method of an N-type solar cell in this comparative example has specific preparation steps referring to Example 1, and the difference between the comparative example and Example 1 is that:
[0085] The back side of the silicon wafer is only subjected to alkali polishing treatment, and the alkali polishing time is 310s; and no CMP fine polishing treatment is performed on the back side of the silicon wafer.
[0086] Performance Testing
[0087] 1. The performance of the batteries prepared in Example 1 and Comparative Example 1 was tested. The test results are as follows: Figure 1-3As shown, the PL brightness is tested before silicon wafer metallization, the thickness of N+Poly layer 7 is tested after annealing, and the cell efficiency is tested after metallization.
[0088] See also Figure 1 From the PL brightness comparison data, it can be seen that compared with comparative example 1, the PL brightness of embodiment 1 (exposure time 0.1s) increases by 1.62%, and the passivation performance can be guaranteed.
[0089] See also Figure 2 From the comparison data of the thickness of the N+Poly layer 7, it can be seen that: compared with the comparative example 1, the thickness of the N+Poly layer 7 of the embodiment 1 is reduced by 14.7%, which can reduce the parasitic light absorption.
[0090] See also Figure 3 From the comparison data of the battery efficiency, it can be seen that: compared with the comparative example 1, the battery efficiency of the embodiment 1 is improved by 0.19%. This also indirectly shows that the battery of the embodiment 1 effectively reduces the parasitic light absorption, because: the solar cell converts light energy into electrical energy, the total amount of light is constant, and the reduction of parasitic light absorption means that the light utilization rate is increased, the photocurrent becomes larger, and thus the battery efficiency is increased.
[0091] Combination Figure 1-3 From the comparison data, it can be seen that: the preparation method of Example 1 can significantly reduce the thickness of the N+Poly layer 7 to reduce parasitic light absorption; at the same time, when the thickness of the N+Poly layer 7 is thinned, it not only has no negative impact on the passivation performance of the tunneling layer 6, but also improves the passivation performance and contact performance of the tunneling layer 6 and the N+Poly layer 7.
[0092] 2. Taking the processing of 1000 silicon wafers as an example, before preparing the TOPCon structure, in order to obtain a flat and smooth back surface, two polishing methods are used, namely, alkali polishing + CMP fine polishing (as shown in steps 4-5 of Example 1) and existing CMP polishing (which includes three stages of CMP rough polishing, fine polishing and fine polishing). The time consumption data of the obtained silicon wafer samples are shown in Table 1 below:
[0093] Table 1
[0094] Technology Alkali polishing + CMP polishing Existing CMP polishing time 1500s 4300s
[0095] It can be seen that, under the premise of obtaining a dense and thin N+Poly layer on the back surface of the silicon wafer, compared with the existing CMP polishing process, Example 1 can greatly shorten the total time spent on polishing by combining alkaline polishing with CMP fine polishing, thereby improving the battery production efficiency.
[0096] In summary, the preparation method of Example 1 can improve battery efficiency and reduce raw material cost investment; moreover, through the combination of alkaline polishing and CMP fine polishing, the total time spent on polishing can be shortened, thereby improving battery production efficiency.
[0097] Although the preferred embodiments of the present invention have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.
[0098] The technical solution provided by the present invention is introduced in detail above. Specific examples are used in this article to illustrate the principle and implementation mode of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of the present invention, there will be changes in the specific implementation mode and application scope. In summary, the content of this specification should not be understood as limiting the present invention.
Claims
1. A method for preparing an N-type solar cell, characterized in that: The steps include: S1, doping and diffusion are performed on the silicon wafer after texturing to prepare a P+ emitter on the front side of the silicon wafer; wherein the diffusion forms borosilicate glass on both the front and back sides of the silicon wafer; S2, single-sided pickling of the back side of the silicon wafer to remove the borosilicate glass on the back side of the silicon wafer; S3, performing alkali polishing on the back of the silicon wafer for 150-200 seconds, so that the back of the silicon wafer forms a planar morphology and the borosilicate glass on the front of the silicon wafer is retained; S4, using silicon polishing liquid to perform CMP fine polishing on the back of the silicon wafer, the CMP fine polishing time is 60-90s, so that the plane morphology of the back of the silicon wafer becomes more flat and smooth; S5, sequentially preparing a tunneling layer and an N+Poly layer on the back side of the silicon wafer; S6, cleaning the silicon wafer to remove residual organic matter, impurities on the surface of the silicon wafer and the borosilicate glass on the front side; S7, passivating the front and back sides of the silicon wafer to prepare a front passivation anti-reflection film and a back passivation film, respectively; S8. Metallize the front and back sides of the silicon wafer to obtain front metal electrodes and back metal electrodes, respectively.
2. The method for preparing an N-type solar cell according to claim 1, characterized in that: In step S3, the alkaline polishing is performed using a KOH solution, wherein the KOH solution is prepared by mixing water and KOH in a volume ratio of 18-25:1; the temperature of the alkaline polishing is 45-65°C.
3. The method for preparing an N-type solar cell according to claim 1, characterized in that: In step S4, the silicon polishing liquid has a raw material ratio, calculated by volume fraction, of: SiO2 latex 20-40% KOH 0-3% Fatty alcohol polyoxyethylene ether 0.01-0.5% Thickener 0-0.2% Water balance.
4. The method for preparing an N-type solar cell according to claim 1 or 3, characterized in that: In step S4, the process conditions of CMP fine polishing are: the rotation speed of the polishing disc is 26-33r / min, the temperature is maintained at 25-30°C, the polishing rate is 0.4-0.6um / min, and the polishing pressure is 0.8-1.2N / cm 2 , the polishing pad should be made of non-woven fabric with fluff; The polishing amount of the CMP fine polishing is 0.1-0.3 um.
5. A method for preparing an N-type solar cell according to any one of claims 1 to 3, characterized in that: In step S5, after preparing the tunneling layer, an amorphous silicon layer doped with an N-type material is prepared on the back of the tunneling layer, and then the silicon wafer is annealed to obtain an N+Poly layer with a thickness of 75-90 nm; The annealing treatment temperature is 800-1000° C., and the insulation time is 0.5-1.5 h.
6. The method for preparing an N-type solar cell according to claim 5, characterized in that: In step S6, the silicon wafer is cleaned with a hydrogen peroxide solution, an HF solution, and a mixture of HCl and HF in sequence to remove organic matter and impurities remaining on the surface of the silicon wafer, BSG retained on the front side, and an annealed oxide layer formed by annealing.
7. The method for preparing an N-type solar cell according to claim 1, characterized in that: In step S7, the front passivation anti-reflection film includes an Al2O3 film and a front silicon nitride film deposited in sequence; and the back passivation film is a back silicon nitride film.
8. The method for preparing an N-type solar cell according to claim 1, characterized in that: Step S2 also includes using the single-sided pickling to remove the wrap-around plating caused by doping diffusion at the edge of the silicon wafer; In step S2, the single-side pickling is performed using an HF solution, wherein the HF solution is prepared by mixing HF and water in a volume ratio of 1:1.5-2.
9. The method for preparing an N-type solar cell according to claim 1, characterized in that: In step S1, before doping and diffusion, the silicon wafer is textured to form a textured light-trapping structure on the surface of the silicon wafer.
10. An N-type solar cell, characterized in that: It is prepared by the preparation method of an N-type solar cell according to any one of claims 1 to 9.