Digital energy switch, DESS system and processing method thereof

Abstract

The invention provides a digital energy switch, a DESS system and a processing method of the DESS system. The switch comprises a switch CPU and a switch FPGA. One end of the switch CPU is respectively connected with the digital energy adapter and the digital energy concentrator through the switch FPGA, and the other end of the switch CPU is in two-way communication connection with an upper cloud end or a host. The switch FPGA comprises a data cache region, an information flow control module, an energy flow control module, an optical fiber communication module and an Ethernet communication module; according to the digital energy switch, the DESS system and the processing method of the DESS system, the limitation of a single CPU setting mode can be overcome, the task load borne by the CPU is reduced, the structure of the digital energy switch is optimized, the communication speed and the real-time performance of the switch are improved, and the anti-interference capability of the switch is enhanced.

Description

Technical Field

[0001] The present invention relates to the technical field of encoding, decoding or code conversion in an energy storage system, and in particular to a digital energy switch, a DESS system and a processing method thereof. Background Art

[0002] At present, the digital energy exchange system DESS is increasingly used in the energy field as a core device for realizing energy digitization and efficient management. However, the digital energy exchange in the existing DESS system has significant shortcomings.

[0003] Since the existing digital energy switches use RS485 half-duplex communication, this communication method has many limitations, such as low data transmission rate, which makes it difficult to cope with the growing demand for large-scale data transmission. It performs poorly in terms of real-time performance. Due to the half-duplex characteristics and limited communication rate, there is a significant delay in data update and transmission, which cannot meet the requirements of energy management systems for rapid response and precise control. Most importantly, in the actual application environment of DESS battery dynamic reconstruction, electromagnetic interference is particularly serious, and the electrical signals of RS485 communication are easily interfered, resulting in data transmission errors, which in turn affects the normal operation and decision-making of the system. This not only reduces the performance and efficiency of the DESS system, but also increases the maintenance cost and operation risk of the system, limiting its application and development in more key areas.

[0004] In addition, the communication protocol used by existing digital energy switches is relatively simple, and it is impossible to effectively detect and correct errors during data transmission. Once data errors occur, the system may make wrong decisions based on the wrong data, thus affecting the normal operation of the entire energy exchange system. Moreover, since there is no verification mechanism, the integrity and accuracy of the data cannot be ensured, which may lead to data loss or damage, further reducing the reliability and stability of the system.

[0005] The existing digital energy switches use a single CPU, which is prone to problems such as limited computing power, poor real-time performance, difficult function expansion, uneven resource utilization, insufficient flexibility, poor power consumption and heat dissipation, and high safety and reliability risks. Specifically, first, in the face of multi-source complex data from electrochemical energy storage systems, photovoltaic systems, photovoltaic storage complementary systems, etc., a single CPU may be difficult to cope with large-scale computing needs, resulting in slow data processing speed and affecting the real-time response of the system. Second, in critical tasks that require rapid decision-making and control in energy systems, such as completing precise adjustments to energy flow in an instant, a single CPU may be delayed due to being busy processing other matters, making it difficult to meet strict real-time requirements. Third, when adding new functions to the digital energy switch, such as supporting new communication protocols or introducing complex control algorithms, the single CPU architecture usually requires major modifications to the entire hardware and software, which is not only costly but also has a long development cycle. Fourth, when the CPU performs different tasks, it is easy to have unreasonable resource allocation, resulting in inefficiency of some tasks, while other tasks are delayed due to waiting for resources. Fifth, the single CPU architecture is subject to significant restrictions in hardware upgrades or functional expansion, and performance improvements or functional additions can often only be achieved by replacing the entire processor, which significantly increases the cost and complexity of system upgrades. Sixth, when running at high load, the power consumption of a single CPU increases significantly, generating a large amount of heat, and placing more stringent requirements on the system's heat dissipation design. Seventh, as the only core, once a single CPU fails, the entire system will be paralyzed, making it difficult to ensure the system's continued operation.

[0006] In addition, since the CPU chips in digital energy switches in the prior art are mostly imported chips, it is of great significance to study how to improve the communication speed and real-time performance of digital energy switches, enhance the anti-interference ability of switches, and overcome the limitations of single CPU settings.

[0007] In patent CN109447048B, an artificial intelligence early warning system is mentioned, including an intelligent Internet of Things and risk factor data collection system, a risk factor management system, cloud computing, cloud storage, cloud database, artificial intelligence early warning operating system, artificial intelligence early warning server, Internet + distributed early warning police booth, five-level artificial intelligence early warning system, four-level artificial intelligence early warning system, three-level artificial intelligence early warning system, two-level artificial intelligence early warning system, and one-level artificial intelligence early warning system, which can effectively improve the utilization rate of information resources. However, since the early warning system is applied to the field of security early warning, the control effect of batteries in energy storage technology is poor, and it has not been able to solve the problem of how to improve the anti-interference ability of the switch and overcome the limitations of the single CPU setting. Summary of the invention

[0008] In view of this, the present invention aims to propose a digital energy switch, a DESS system and a processing method thereof, so as to solve the problems existing in the prior art that the use of a single CPU easily leads to limited computing power, poor real-time performance, difficult function expansion, uneven resource utilization, insufficient flexibility, poor power consumption and heat dissipation, and high security and reliability risks, and at the same time solve the problem that the processing method of the existing switch is relatively simple, which easily leads to poor exception handling effect and incomplete information statistics; thereby optimizing the structure of the digital energy switch, improving the communication speed and real-time performance of the switch, enhancing the anti-interference ability, ensuring the accuracy and reliability of data transmission, and improving the perfection of information statistics. In addition, it can also overcome the limitations of the single CPU setting method and reduce the amount of tasks that the CPU needs to undertake. By reasonably setting the processing method, the data processing efficiency and the stability of the system can be further improved.

[0009] To achieve the above objectives, the technical solution of the present invention is as follows:

[0010] The present invention relates to a digital energy switch, a DESS system and a processing method thereof, wherein the digital energy switch comprises a switch CPU and a switch FPGA. One end of the switch CPU is connected to a digital energy adapter and a digital energy hub respectively through the switch FPGA; the other end of the switch CPU is connected to an upper cloud or a host in a two-way communication manner. The switch FPGA comprises a data cache, an information flow control module, an energy flow control module, an optical fiber communication module and an Ethernet communication module. One end of the information flow control module and the energy flow control module are both connected to the switch CPU through the data cache, and the other end of the information flow control module and the energy flow control module are respectively connected to the digital energy adapter and the digital energy hub through the data cache.

[0011] Furthermore, the data cache area includes three cache areas.

[0012] Furthermore, the switch FPGA is connected to the switch CPU via a data address bus.

[0013] Furthermore, the data width of the data address bus is 16 bits.

[0014] Furthermore, the three cache areas are respectively the CPU data cache area, the adapter data cache area, and the hub data cache area. One end of the information flow control module and the energy flow control module are bidirectionally connected to the switch CPU through the CPU data cache area; the other ends of the information flow control module and the energy flow control module are bidirectionally connected to the adapter data cache area and the hub data cache area respectively. The adapter data cache area is bidirectionally connected to the digital energy adapter through the optical fiber communication module; the hub data cache area is bidirectionally connected to the digital energy hub through the Ethernet communication module.

[0015] Furthermore, the data in the CPU data cache includes any one or more data types of relevant data transmitted by the digital energy adapter, relevant data transmitted by the digital energy hub, and relevant data transmitted by the upper cloud or host.

[0016] Furthermore, the switch FPGA also includes an abnormal feedback module, which is bidirectionally connected to the information flow control module, the energy flow control module, and the switch CPU.

[0017] A DESS system includes a digital energy switch as described above, including a power storage converter PCS. The DC side of the digital energy network card and the power storage converter PCS are respectively connected to the positive and negative poles of the digital energy adapter, and the AC side of the power storage converter PCS is connected to the power grid. The digital energy network card is connected to the energy components in a one-to-one correspondence; the digital energy adapter is connected to the digital energy switch via optical fiber communication, and the digital energy switch is connected to the digital energy network card via a digital energy hub.

[0018] A processing method for a digital energy switch, the method is applied to a digital energy switch, such as Figure 3 As shown, it is characterized in that the method comprises the following steps:

[0019] Step 1: Data collection and processing: The switch FPGA collects raw data from the digital energy adapter and the digital energy hub, and extracts key information from the processed data after preliminary preprocessing of the raw data;

[0020] Step 2: Data caching and processing: Classify and store the pre-processed data, and transfer the required data to the CPU data cache according to the predetermined timing and priority;

[0021] Step 3: CPU processing and decision-making: The switch CPU obtains data from the CPU data cache, uses the required data analysis algorithms and logic to perform in-depth analysis and calculations, formulates control strategies and decisions, and generates corresponding control instructions;

[0022] Step 4: Instruction transmission and execution: The control instruction is transmitted from the switch CPU back to the switch FPGA, and the switch FPGA executes the instruction;

[0023] Step 5: Exception handling and feedback.

[0024] Furthermore, in step one, the preprocessing operation type includes performing any one or more preprocessing operations of preliminary format conversion, filtering and denoising on the collected data.

[0025] Compared with the prior art, the digital energy switch, DESS system and processing method described in the present invention have the following beneficial effects:

[0026] Through the setting of the switch, the structure of the digital energy switch can be optimized, the communication speed and real-time performance of the switch can be improved, the anti-interference ability of the switch can be enhanced, and the accuracy and reliability of data transmission can be ensured. It can also overcome the limitations of the single CPU setting method; reduce the amount of tasks that the CPU needs to undertake, and improve the system's computing power, real-time performance, functional scalability, resource utilization efficiency, flexibility, heat dissipation effect, security and reliability. It can also reduce dependence on imported CPU chips and ensure the stability and autonomous controllability of chip supply. By setting the processing method, optimizing the communication protocol, and introducing the verification and error correction mechanism, it can also improve data processing efficiency and system stability. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The accompanying drawings, which constitute part of the present invention, are used to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute improper limitations of the present invention.

[0028] In the figure:

[0029] Figure 1 It is the overall structure diagram of the DESS system;

[0030] Figure 2 This is a schematic diagram of the internal structure of the digital energy switch;

[0031] Figure 3 The figure is a flowchart diagram of a processing method of a digital energy switch. DETAILED DESCRIPTION

[0032] The inventive concepts of the present disclosure will be described below using terms commonly used by those skilled in the art to convey the essence of their work to other persons skilled in the art. However, these inventive concepts can be embodied in many different forms and should not be considered limited to the embodiments described herein.

[0033] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features in the embodiments may be combined with each other.

[0034] The present invention will be described in detail below with reference to the accompanying drawings and in conjunction with embodiments.

[0035] A DESS system includes a digital energy switch as described above. The DESS system is a soft-defined dynamic topology energy exchange system. The system includes an energy storage converter PCS. The DC sides of the digital energy network card and the energy storage converter PCS are respectively connected to the positive and negative poles of the digital energy adapter, and the AC side of the energy storage converter PCS is connected to the power grid. The digital energy network card is connected to the energy components one by one; the digital energy adapter and the digital energy switch are connected via optical fiber communication, and the digital energy switch is connected to the digital energy network card via a digital energy hub. In this embodiment, the energy storage converter PCS can be used to convert the DC power output by the digital energy adapter into AC power and transmit it to the power grid, and can also convert the AC power of the power grid into DC power and transmit it to the energy component, which is a battery cell or a photovoltaic panel. The digital energy network card is a high-speed control and data acquisition device for the energy component. The digital energy switch, the digital energy hub, and the digital energy network card are connected via Ethernet communication.

[0036] Through the DESS system, combined with power electronics technology and information technology, and a variety of isolation sampling technologies, the energy informationization setting is realized to realize the digital processing of energy systems such as electrochemical energy storage systems, photovoltaic systems, and photovoltaic storage complementary systems, and realize the software-defined dynamic topology structure. After the energy components are connected through the DESS system, the system will perform online dynamic digital integration based on the energy status information of each subunit to form an intrinsically safe, highly available, and efficient energy system. Among them, the digital energy hub is responsible for the equipment control, data collection, judgment, and forwarding of the energy components at the device layer; performs online dynamic reconstruction of the series-parallel topology of the energy components; and performs detection and protection actions for overvoltage, overtemperature, overcharge, overdischarge, and other abnormal conditions of the energy components.

[0037] like Figure 1 As shown, N digital energy hubs are provided, where N is a positive integer. Each digital energy hub is communicatively connected to a corresponding digital energy network card. Each digital energy hub is connected to m energy components and digital energy network cards, where m is a positive integer and m≤16.

[0038] like Figure 1As shown, when m=9, each digital energy hub is connected to 9 energy components and digital energy network cards. The 9 energy components are connected to the 9 digital energy network cards one by one. The 9 digital energy network cards are respectively recorded as NIC0-NIC8. After NIC0, NIC1, and NIC2 are connected in parallel, one end is connected to the digital energy adapter or the digital energy network card connected to the adjacent digital energy hub. After NIC0, NIC1, and NIC2 are connected in parallel, the other end is connected to one end of NIC3, NIC4, and NIC5 in parallel. After NIC3, NIC4, and NIC5 are connected in parallel, the other end is connected to one end of NIC6, NIC7, and NIC8 in parallel. After NIC6, NIC7, and NIC8 are connected in parallel, the other end is connected to the digital energy network card or digital energy adapter connected to the adjacent digital energy hub.

[0039] Through the cascade setting of digital energy network cards, dynamic topology switching of energy components can be realized. It is also beneficial to timely isolate or handle the energy components through digital energy network cards in the event of failure or abnormality of energy components, so as to realize dynamic energy scheduling of energy components in the system.

[0040] The digital energy switch is a comprehensive control unit for the overall energy dispatch, high-level strategy execution and communication management of the DESS system. It is used to collect the working status of each circuit, analyze, judge and execute the corresponding system management strategy; upload the necessary data information of each part of the system; and perform corresponding actions according to the system status and superior dispatch instructions. The digital energy adapter is a system-level acquisition, control and management device of the DESS, and is the interface for the system's DC input and output. Responsible for data collection, fault protection and system management of the system input and output, the digital energy adapter also receives the dispatch instructions of the digital energy switch to ensure the safe and stable operation of the system under various working conditions.

[0041] Since the original digital energy switch cannot meet the actual work requirements well, in order to solve the problems in the prior art that the single CPU method is easy to limit the computing power, poor real-time performance, difficult function expansion, uneven resource utilization, insufficient flexibility, poor power consumption and heat dissipation, and high security and reliability risks, and the existing switch processing method is relatively simple, prone to poor exception processing effect, and incomplete information statistics; this embodiment proposes a digital energy switch, DESS system and processing method thereof.

[0042] like Figure 2As shown, the digital energy switch includes a switch CPU and a switch FPGA. One end of the switch CPU is connected to the digital energy adapter and the digital energy hub through the switch FPGA, and the other end of the switch CPU is connected to the upper cloud or host in a two-way communication. The switch FPGA includes a data cache, an information flow control module, an energy flow control module, an optical fiber communication module, and an Ethernet communication module; one end of the information flow control module and the energy flow control module are connected to the switch CPU through the data cache, and the other end of the information flow control module and the energy flow control module are connected to the digital energy adapter and the digital energy hub through the data cache. In this embodiment, the host is a PC. In this embodiment, the switch CPU uses the N32G457 CPU chip of National Technology Co., Ltd., and the switch FPGA uses the domestic Anlu EG4D20EG FPGA to ensure hardware performance and reliability and reduce dependence on imported chips. The switch FPGA is connected to the switch CPU through the data address bus to achieve efficient collaborative work. The data width of the data address bus is 16bit.

[0043] By adopting the setting of the switch CPU and the switch FPGA working together, the structure of the digital energy switch can be optimized, the communication speed and real-time performance of the switch can be improved, the anti-interference ability of the switch can be enhanced, and the accuracy and reliability of data transmission can be ensured. It can also overcome the limitations of the single CPU setting method; reduce the amount of tasks that the CPU needs to undertake, and improve the system's computing power, real-time performance, functional scalability, resource utilization efficiency, flexibility, heat dissipation effect, security and reliability. It can also reduce dependence on imported CPU chips and ensure the stability and autonomous controllability of chip supply.

[0044] The functions of the switch FPGA are as follows:

[0045] The data cache area of ​​the switch FPGA includes three cache areas. The three cache areas are the CPU data cache area, the adapter data cache area, and the hub data cache area. One end of the information flow control module and the energy flow control module are connected to the switch CPU through the CPU data cache area in a two-way communication; the other end of the information flow control module and the energy flow control module are connected to the adapter data cache area and the hub data cache area in a two-way communication. The hub data cache area is connected to the digital energy hub in a two-way communication through the Ethernet communication module; the adapter data cache area is connected to the digital energy adapter in a two-way communication through the optical fiber communication module.

[0046] By opening up different high-speed cache areas on the switch FPGA and setting up each cache area, fast data storage and interaction can be achieved, and the speed and efficiency of data processing can be improved. Among them, the CPU data cache area is used to store data related to the CPU, so as to achieve a fast response between the CPU and FPGA inside the switch, and to process various requests inside the system in a timely manner, thereby reducing the workload of the switch CPU. The switch FPGA can effectively share the tasks of the switch CPU, improve the speed and accuracy of the switch data transmission and processing, and reduce the probability of data errors. In addition, the adapter data cache area is used to temporarily store data communicated between the switch and the digital energy adapter, and the hub data cache area is used to temporarily store data communicated between the switch and the digital energy hub.

[0047] The data in the CPU data cache includes any one or more data types among the relevant data transmitted by the digital energy adapter, the relevant data transmitted by the digital energy hub, and the relevant data transmitted by the upper cloud or host. The relevant data transmitted by the digital energy adapter includes any one or more data of the system component status and energy parameters collected by the adapter. The relevant data transmitted by the digital energy adapter can provide a basis for the switch CPU to evaluate the input and output of the system. The relevant data transmitted by the digital energy hub includes detailed information of the energy components of the device layer, and the detailed information includes the execution status of the relevant actions of controlling and protecting the energy components; it is used for the switch CPU to understand the energy management status of the entire device layer. The relevant data transmitted by the upper cloud or host includes the upper-layer control instructions and the comprehensive information of the system that needs to be uploaded to the upper layer.

[0048] By gathering data from different sources in the CPU data cache, the switch CPU can perform comprehensive analysis and processing. For example, the switch CPU can combine the data from the digital energy adapter and the digital energy hub to optimize the system's energy distribution strategy; at the same time, it can adjust the system's operating mode according to the instructions of the upper layer. Through efficient processing and integration of these data, the switch CPU can make more accurate decisions to ensure the stable and efficient operation of the entire system.

[0049] The switch FPGA also includes an abnormal feedback module and a system status judgment and processing module. The abnormal feedback module is connected to the information flow control module, the energy flow control module, and the switch CPU in a two-way communication manner; it is used to feed back abnormal information to the switch CPU through the abnormal feedback module after abnormal data is found during the processing of the information flow control module and the energy flow control module, and interrupt the communication connection between the switch CPU and the switch FPGA to perform data abnormality processing. The system status judgment and processing module is connected to the information flow control module and the energy flow control module in a two-way communication manner, and is used to monitor the information flow and energy flow data in real time, and make timely analysis and judgment.

[0050] By setting up the abnormal feedback module, data abnormalities can be effectively handled in a timely manner, thereby improving the reliability and stability of the digital energy switch in overall dispatching the entire DESS system, thus ensuring the continuous and stable operation of the digital energy switch and the system.

[0051] In addition, through the setting of the switch FPGA, a full-duplex optical fiber communication mode is adopted between the digital energy switch and the digital energy hub; it is conducive to improving the real-time performance of data transmission in the system and enhancing the efficiency of data sending and receiving in the system. Different from the half-duplex communication mode of RS485, the data transmission rate is low. It is also conducive to achieving the data transmission rate between the digital energy switch and the digital energy adapter and enhancing the security of data transmission. In addition, the switch FPGA has powerful parallel processing capabilities and flexible programmability, and can quickly process large amounts of data and implement complex communication protocols and algorithms. By implementing any one of the functions of data encoding, decoding, frame format processing and error checking in the switch FPGA. It can significantly improve the speed and efficiency of data processing, thereby solving the problems of slow communication rate and poor real-time performance. Optical fiber communication uses optical signals to transmit data in optical fibers. Compared with traditional electrical signal communication methods, it has extremely high bandwidth and anti-electromagnetic interference capabilities. By adopting optical fiber communication technology, data can be transmitted quickly and accurately without electromagnetic interference, thereby solving the problem that the existing RS485 communication method is susceptible to interference in complex electromagnetic environments. It is conducive to enhancing the stability of system operation and reducing the cost of the system.

[0052] Regarding the optical fiber communication module in the switch FPGA, the optical fiber communication module includes a sending processing logic module and a receiving processing logic module. The sending processing logic module and the receiving processing logic module are both integrated inside the optical fiber communication module to provide an optical fiber communication channel for data exchange between the digital energy switch and the digital energy adapter. The sending processing logic module is connected to the optical fiber sending device, and the receiving processing logic module is connected to the optical fiber receiving device. Figure 2 As shown, the optical fiber receiving device (RX) of the adapter is connected to the optical fiber transmitting device (TX) of the digital energy switch via optical fiber communication; the optical fiber transmitting device (TX) of the adapter is connected to the optical fiber receiving device (RX) of the digital energy switch via optical fiber communication.

[0053] The sending processing logic module includes a sending framing processing module, an encoding module, and a parallel-to-serial conversion module. One end of the sending framing processing module is connected to the data buffer area for fetching data through the data buffer area; the other end of the sending framing processing module is connected to the optical fiber sending device through the encoding module and the parallel-to-serial conversion module in turn, and the data is sent out through the optical fiber sending device. The receiving processing logic module includes a receiving parsing processing module, a decoding module, and a serial-to-parallel conversion module. One end of the optical fiber receiving device is connected to the optical fiber for receiving the optical fiber transmission signal; the other end of the optical fiber receiving device is connected to the data buffer area through the serial-to-parallel conversion module, the decoding module, and the receiving parsing processing module in turn, and the data is stored in the data buffer area. Among them, the encoding module and the decoding module both adopt the 8B / 10B data encoding method. When sending data, 8B / 10B is used for encoding before sending data, and when receiving data, 8B / 10B is used for decoding before receiving data. The optical fiber sending device and the optical fiber receiving device adopt domestic devices FT-1629Z and FT-2529Z respectively. It is used to achieve high-speed and stable data transmission and improve communication performance and anti-interference ability.

[0054] By selecting the domestic switch FPGA, optical fiber transmitting device and optical fiber receiving device in this embodiment, the system risk caused by the limited supply of foreign chips can be avoided. It can also reduce chip costs and improve the market competitiveness of products. And by adopting the setting of the switch FPGA, the transmission of data in the system can be made more efficient and the delay time in the data transmission process can be reduced. In addition, the data cache area set by the switch FPGA can play a key role during the operation of the system. The existence of the data cache area greatly liberates the burden of the switch CPU, so that the switch CPU no longer needs to consume resources to process complex communication protocols. It is beneficial for the switch CPU to devote more energy and computing power to other important tasks of the system; such as the execution of more complex energy management algorithms, in-depth analysis of system status, and rapid decision-making. This optimized resource allocation method significantly improves the operating efficiency and response speed of the entire system.

[0055] The communication protocol between the digital energy switch and the digital energy adapter adopts the proprietary communication protocol based on the DESS system. The data length of each data frame corresponding to the proprietary communication protocol is 64 bits. The structure of each data frame includes address command information, data segment, frame sequence number and CRC check data. The data in the address command information, data segment, frame sequence number and CRC check data are arranged in sequence to form the data of each data frame. Among them, the data length of the address command information is 16 bits, the data length of the data segment is 32 bits, the data length of the frame sequence number is 8 bits, and the data length of the CRC check data is 8 bits. By setting the above data frame format, the accuracy, integrity and orderliness of data transmission can be effectively ensured. Reduce data transmission conflicts and confusion. Ensure that each data frame can be accurately sent, received and processed, and provide solid technical support for the refined energy management and intelligent control of the DESS system. Among them, the 8-bit frame sequence number starts from 0 to 255 cycles, and the last 8 bits of CRC check data are CRC check data for the previous 56 bits of data.

[0056] Based on the DESS system's own communication protocol, the digital energy switch and the digital energy hub in the present invention are connected to each other through an Ethernet communication method in a digital energy switch, and the method is applied to the digital energy switch. The method includes the following steps:

[0057] Step S100: Data packet reception: The Ethernet communication module in the switch FPGA receives the Ethernet data packet from the digital energy hub and performs frame check and address matching;

[0058] Step S200: Data analysis: The switch FPGA analyzes the content of the data packet and extracts valid data and control information;

[0059] Step S300: Data cache: storing the parsed data in the hub data cache area;

[0060] Step S400: Data transmission: According to the instruction of the switch FPGA, the data to be transmitted is assembled into an Ethernet data packet and sent out through the Ethernet port.

[0061] Workflow between digital energy switches or digital energy hubs: The digital energy network card collects high-speed control and data of each energy component in real time, and transmits the data to the digital energy hub. After receiving the data from the digital energy network card, the digital energy hub performs transit processing, encapsulates the data into data frames according to its own communication protocol, and sends it to the digital energy switch via Ethernet. After receiving the data frame, the digital energy switch stores it in the hub data buffer area, processes and analyzes the data to determine the control strategy for the energy component. Then, the digital energy switch sends the control instruction to the digital energy hub via Ethernet, and the hub conveys the instruction to the digital energy network card, which executes the instruction to achieve specific control of the energy component. In this process, the digital energy hub plays a role of transit and coordination, ensuring that the data transmission and instruction execution between the digital energy switch and the digital energy network card can proceed smoothly.

[0062] A processing method for a digital energy switch, the method is applied to the digital energy switch. The method comprises the following steps:

[0063] Step 1: Data collection and processing: The switch FPGA collects raw data from the digital energy adapter and the digital energy hub, and extracts key information from the processed data after preliminary preprocessing of the raw data;

[0064] Step 2: Data caching and processing: Classify and store the pre-processed data, and process the data according to the predetermined timing and priority. Some data needs to be transferred to the CPU data cache;

[0065] Step 3: CPU processing and decision-making: The switch CPU obtains data from the CPU data cache, uses the required data analysis algorithms and logic to perform in-depth analysis and calculations, and formulates control strategies and decisions to generate corresponding control instructions.

[0066] Step 4: Instruction transmission and execution: The control instruction is transmitted from the switch CPU back to the switch FPGA, and the switch FPGA executes the instruction to achieve precise control and management of the digital energy switch; the actions of the switch FPGA executing the instruction include adjusting the power output, controlling the distribution of energy flow, etc.

[0067] Step 5: Exception handling and feedback: During the entire data processing and control process, the switch FPGA and switch CPU work together to detect and handle exceptions. When an abnormal situation occurs, the switch FPGA sends an interrupt signal containing abnormal data information to the switch CPU and takes corresponding emergency measures. At the same time, the abnormal information is fed back to the system for fault diagnosis and recovery.

[0068] Among them, in step one, the preprocessing operation type includes performing any one or more preprocessing operations of preliminary format conversion, filtering and denoising on the collected data.

[0069] Step 2 includes:

[0070] Step S21: the pre-processed data is stored in the adapter data buffer and the hub data buffer according to its source and type;

[0071] Step S22: According to the predetermined timing rules and priorities, the adapter data buffer area and the hub data buffer area transfer data to the CPU data buffer area, and then execute step three.

[0072] Through the setting of the method, based on the integrated setting of domestic CPU and FPGA, combined with the application of optical fiber communication technology, the digital energy switch can effectively realize the efficient and accurate management of the overall system, and can also improve the stability and reliability of the digital energy switch in the management of energy flow and information flow. It can also give full play to the advantages of the switch CPU and switch FPGA combined in the digital energy switch, which is specifically reflected in the ability to have powerful parallel processing capabilities, flexible function customization, low energy consumption, high reliability, optimized resource allocation, good heat dissipation effect, high performance computing, and fast response and real-time control capabilities, thereby improving the overall performance and stability of the digital energy switch.

[0073] Step five includes:

[0074] Step S51: During the entire data processing and control process, the switch FPGA and the switch CPU cooperate to perform abnormality detection and processing. The abnormality detection and processing method includes continuously monitoring the range and change rate of input data through the switch FPGA, and determining whether the input data exceeds the normal data range or change rate range. If yes, the data is abnormal, and step S53 is executed; if no, the data is normal, and step S52 is executed;

[0075] Step S52: The switch CPU makes a rationality judgment on the analyzed and processed data obtained from the switch FPGA; judges whether the processed data meets expectations or has no logical contradictions. If yes, the data is normal, and continues to monitor other data, and returns to step S51; if no, the data is abnormal, and executes step S53;

[0076] Step S53: The detected abnormal data is quickly notified to the switch CPU through the pre-set interrupt signal mechanism, so that it suspends the current task and gives priority to the abnormality. Specifically, the switch FPGA generates an interrupt signal and transmits it to the switch CPU, so that it suspends the current task and gives priority to the abnormality; and takes corresponding emergency measures for different abnormal situations. Emergency measures include immediately stopping certain operations, switching to a backup system, and adjusting parameters to stabilize any one or more emergency measures in the system. Emergency measures also include recording the abnormal information in detail through the switch FPGA, and feeding it back to the entire system through the abnormal feedback module, providing key data support for subsequent fault diagnosis and recovery.

[0077] Through the exception handling and feedback in step five, abnormal situations can be handled and fed back in a timely manner, which effectively improves the stability and reliability of the system and ensures the continuous and stable operation of the digital energy switch.

[0078] The overall processing method of a digital energy switch includes an information flow management method in a digital energy switch, an energy flow management method in a digital energy switch, and an Ethernet communication method in a digital energy switch. The information flow management method and the energy flow management method are parallel processing methods.

[0079] Specifically, a method for managing information flow in a digital energy switch is applied to the digital energy switch. The method comprises the following steps:

[0080] Step S1: Data collection: The Ethernet communication module and the optical fiber communication module in the switch FPGA collect information flow data from the digital energy hub and the digital energy adapter respectively;

[0081] Step S2: Preprocessing: The switch FPGA performs preliminary format conversion, screening and denoising on the collected data; and extracts key information, which includes any one or more data information of data address, data type, and payload;

[0082] Step S3: Cache: according to the data source, the processed information flow data is stored in the hub data cache area and the adapter data cache area respectively;

[0083] Step S4: Transmitting: According to a predetermined priority and timing, the data required by the adapter data buffer area and the hub data buffer area are transmitted to the CPU data buffer area according to certain rules;

[0084] Step S5: Processing: The switch CPU reads data from the CPU data buffer and performs in-depth processing using data analysis algorithms and strategies, which include any one or more processing methods of data fusion, pattern recognition, and priority judgment.

[0085] Step S6: Decision and instruction generation: Based on the processing results, information flow control instructions are generated; the information flow control instructions include any one or more instruction types of data transmission path adjustment, priority setting and flow control.

[0086] Step S7: Instruction execution: The control instruction is transmitted back to the switch FPGA, and the switch FPGA configures the corresponding hardware modules and software parameters; the hardware modules include Ethernet ports and fiber optic interfaces, and the software parameters include parameters in the fiber optic communication module; so as to achieve precise control of information flow.

[0087] Through the information flow management method, the digital energy switch can achieve precise control of the information flow data transmitted between the adapters, hubs and other components in the system, prevent the occurrence of abnormal situations, and make corresponding analysis and judgments in time, which can not only improve the real-time performance of system control, but also prevent the occurrence of data abnormalities.

[0088] A method for managing energy flow in a digital energy switch, the method being applied to the digital energy switch. The method comprises the following steps:

[0089] Step S1': Data collection: The switch FPGA communicates bidirectionally with the digital energy adapter and the digital energy hub through the optical fiber interface and the Ethernet port, and collects energy flow data from any one or more energy components in the battery module and the power supply in real time. The energy flow data includes any one or more parameters of voltage, current, power, and temperature.

[0090] Step S2': Preprocessing: amplify, quantify and filter the collected energy flow data to ensure the accuracy and stability of the data;

[0091] Step S3': Abnormality detection and caching: Real-time monitoring of energy flow data changes, and detection of abnormalities in different energy components through threshold comparison and trend analysis. If yes, store the abnormal energy flow data in the storage area in the abnormal feedback module; if no, store the normal energy flow data in the hub data cache area and / or the adapter data cache area. The abnormality includes any one or more fault modes of overvoltage, overcurrent, and short circuit.

[0092] Step S4': Transmission: according to preset rules, the energy flow data of different cache areas are transmitted to the CPU cache area;

[0093] Step S5': CPU analysis: The switch CPU performs a comprehensive analysis on the received energy flow data and uses the energy management algorithm to calculate the energy allocation plan and fault handling strategy;

[0094] Step S6': Instruction generation: Generate energy flow control instructions according to the analysis results; the energy flow control instructions include any one or more control instructions of adjusting power output, starting protection mechanism and performing fault isolation.

[0095] Step S7': Instruction execution: The control instruction is transmitted to the switch FPGA, and the switch FPGA controls and manages related hardware devices. The hardware devices include power regulators and switches, which are used to achieve precise control and management of energy flow.

[0096] The energy flow management method is conducive to the digital energy switch to achieve precise control of the energy flow data in the energy components monitored by the network card in the system. By monitoring the changes in energy flow data in real time, timely analyzing and generating corresponding instructions through the CPU, and processing normal or abnormal energy components accordingly, the flexibility and reliability of energy flow data control are improved.

[0097] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A digital energy switch, characterized in that: It includes a switch CPU and a switch FPGA. One end of the switch CPU is connected to the digital energy adapter and the digital energy hub through the switch FPGA, and the other end of the switch CPU is connected to the upper cloud or host for bidirectional communication. The switch FPGA includes a data cache area, an information flow control module, an energy flow control module, an optical fiber communication module and an Ethernet communication module. One end of the information flow control module and the energy flow control module are both connected to the switch CPU for communication through the data cache area, and the other end of the information flow control module and the energy flow control module are respectively connected to the digital energy adapter and the digital energy hub through the data cache area.

2. A digital energy switch according to claim 1, characterized in that: The data buffer area includes three buffer areas.

3. A digital energy switch according to claim 1, characterized in that: The switch FPGA is connected to the switch CPU via a data address bus.

4. A DESS system according to claim 3, characterized in that: The data width of the data address bus is 16 bits.

5. A digital energy switch according to claim 2, characterized in that: The three cache areas are respectively the CPU data cache area, the adapter data cache area, and the hub data cache area; one end of the information flow control module and the energy flow control module are both connected to the switch CPU through the CPU data cache area for bidirectional communication; the other ends of the information flow control module and the energy flow control module are respectively connected to the adapter data cache area and the hub data cache area for bidirectional communication, and the adapter data cache area is connected to the digital energy adapter for bidirectional communication through the optical fiber communication module; the hub data cache area is connected to the digital energy hub for bidirectional communication through the Ethernet communication module.

6. A digital energy switch according to claim 5, characterized in that: The data in the CPU data cache area includes any one or more data types of relevant data transmitted by the digital energy adapter, relevant data transmitted by the digital energy hub, and relevant data transmitted by the upper cloud or host.

7. A digital energy switch according to claim 1, characterized in that: The switch FPGA also includes an abnormal feedback module, which is bidirectionally connected to the information flow control module, the energy flow control module, and the switch CPU.

8. A DESS system, characterized in that: The system comprises a digital energy switch according to any one of claims 1 to 7, the system comprises an energy storage converter PCS, the DC sides of the digital energy network card and the energy storage converter PCS are respectively connected to the positive and negative poles of the digital energy adapter, the AC side of the energy storage converter PCS is connected to the power grid, and the digital energy network card is connected to the energy components in a one-to-one correspondence; The digital energy adapter is connected to the digital energy switch via optical fiber communication, and the digital energy switch is connected to the digital energy network card via a digital energy hub.

9. A processing method of a digital energy switch, characterized in that: The method is applied to a digital energy switch according to any one of claims 1 to 7, and the method comprises the following steps: Step 1: Data collection and processing: The switch FPGA collects raw data from the digital energy adapter and the digital energy hub, and extracts key information from the processed data after preliminary preprocessing of the raw data; Step 2: Data caching and processing: Classify and store the pre-processed data, and transfer the required data to the CPU data cache according to the predetermined timing and priority; Step 3: CPU processing and decision-making: The switch CPU obtains data from the CPU data cache, uses the required data analysis algorithms and logic to perform in-depth analysis and calculations, formulates control strategies and decisions, and generates corresponding control instructions; Step 4: Instruction transmission and execution: The control instruction is transmitted from the switch CPU back to the switch FPGA, and the switch FPGA executes the instruction; Step 5: Exception handling and feedback.

10. A processing method for a digital energy switch according to claim 9, characterized in that: In the step 1, the preprocessing operation type includes performing any one or more preprocessing operations of preliminary format conversion, filtering and denoising on the collected data.

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