Storage class memory, data processing method and processor system

Abstract

The invention discloses a storage-level memory, a data processing method and a processor system, and relates to the field of computers. A plurality of memory particles included in the storage class memory are divided into at least one group. Each group comprises a first type of memory particles and a second type of memory particles. The second type of memory particles are used for storing operation error correction codes, and the first type of memory particles are used for storing data and re-error correction codes. The operation error correction codes are used for performing first-level memory error correction on the data stored in the first-class memory particles in the same group. The re-error correction code is used for performing secondary memory error correction on the data stored in the first type of memory particles when the primary memory error correction fails. And the access delay is as low as possible when the high reliability of the data stored in the storage-level memory is ensured through a two-stage memory error correction mechanism. Besides, the memory particles of the storage-level memory are arranged, so that the bit width of the storage-level memory meets the memory bit width indicated by the DDR protocol, and the storage-level memory is compatible with the DDR protocol.

Description

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on December 13, 2021, with application number 202111513788.2 and application name “Method and storage device for transmitting data”, all contents of which are incorporated by reference in this application.

[0002] This application is a divisional application. The application number of the original application is 202210114650.3, and the original application date is January 30, 2022. The entire contents of the original application are incorporated into this application by reference. Technical Field

[0003] The present application relates to the field of computers, and in particular to a storage-level memory, a data processing method, and a processor system. Background Art

[0004] Storage class memory (SCM) is a new type of storage medium with storage capacity, access speed and cost between main memory (such as dynamic random access memory (DRAM)) and hard disk (such as NAND flash). For example, compared with DRAM, SCM has persistence capability, data will not be lost after power failure, and has a larger storage capacity. Compared with NAND flash, SCM has faster access speed.

[0005] At present, SCM implements memory error correction based on the built-in controller. Since the storage medium in the controller may cache data, the access delay of SCM is uncertain, and it is not compatible with the Double Data Rate (DDR) protocol, and the versatility of SCM is low. Therefore, how to improve the reliability of SCM and reduce the access delay of SCM as much as possible while SCM is compatible with the DDR protocol is an urgent problem to be solved. Summary of the invention

[0006] The present application provides a storage-level memory, a data processing method, and a processor system, thereby improving the reliability of the SCM and reducing the access latency of the SCM as much as possible when the SCM is compatible with the DDR protocol.

[0007] In a first aspect, a storage-class memory is provided, wherein a plurality of memory particles included in the storage-class memory are divided into at least one group; each of the at least one group includes a first-class memory particle and a second-class memory particle; the second-class memory particle is used to store a running error correction code, and the first-class memory particle is used to store data and a re-error correction code. The running error correction code is used to perform a first-level memory error correction on the data stored in the first-class memory particles of the same group. The re-error correction code is used to perform a second-level memory error correction on the data stored in the first-class memory particles when the first-level memory error correction fails.

[0008] In this way, the access delay is as low as possible while ensuring the high reliability of the storage-level memory storage data through the two-level memory error correction mechanism. Compared with the built-in controller of the SCM using a more complex error correction algorithm for memory error correction, resulting in a longer access delay, the embodiment of the present application uses a two-level memory error correction mechanism. When the error rate of the storage-level memory is low, the first-level memory error correction can effectively shorten the access delay when ensuring the high reliability of the storage-level memory storage data; when the error rate of the storage-level memory is high, the second-level memory error correction can also ensure the high reliability of the storage-level memory storage data, and the first-level memory error correction can be combined to shorten the access delay as a whole. In addition, by arranging the memory particles of the storage-level memory, the bit width of the storage-level memory meets the memory bit width indicated by the double data rate (Double Data Rate, DDR) protocol, thereby realizing the storage-level memory compatible with the DDR protocol, so that the storage-level memory can be connected to more types of processors (processor), improving the versatility of the storage-level memory.

[0009] The number of the first type of memory particles and the number of the second type of memory particles in each group are determined according to the bit width of the first type of memory particles, the bit width of the second type of memory particles and the memory bit width indicated by the DDR protocol.

[0010] For example, the memory bit width indicated by the DDR protocol is 80 bits, the bit width of the first type of memory particles and the bit width of the second type of memory particles are both 8 bits, and the 10 memory particles contained in the storage-class memory are divided into 2 groups, each group includes 4 first type of memory particles and 1 second type of memory particle; the sum of the bit widths of the 4 first type of memory particles and 1 second type of memory particle contained in each group is 40 bits, and the unit access data amount of each bit is 16 bytes or 32 bytes.

[0011] In a possible implementation, the first type of memory particles includes M first type units and N second type units. The first type unit is used to store data. The second type unit is used to store heavy error correction codes. Therefore, the number of first type units and the number of second type units can be switched or upgraded online by the memory controller or firmware (firmware, FW) according to the usage scenario, thereby improving the flexibility of adapting to different system reliability requirements.

[0012] In another possible implementation, the unit access data volume of the first type of unit and the unit access data volume of the second type of unit are both the unit access data volume of one bit in the bit width of the first type of memory particle. Thus, the unit access data volume of the storage-class memory satisfies the cache line length of the processor connected thereto, thereby improving the versatility of the storage-class memory.

[0013] In another possible implementation, the first type of memory particles also include a third type of unit. The third type of unit is used to implement the function of bad block management of the unit of the first type of memory particles. Thus, the space of the storage-class memory is saved, the storage-class memory is more compatible with the memory (such as DRAM) that meets the DDR protocol, and the versatility of the storage-class memory is improved.

[0014] In a second aspect, a data processing method is provided, which is executed by a controller, and the controller is connected to the above-mentioned first aspect or any possible storage-level memory and processor of the first aspect; the method includes: the controller obtains data stored in the first-class memory particles of the same group in the storage-level memory to perform a first-level memory error correction; when the first-level memory error correction fails, the controller obtains each first-class memory particle to perform a second-level memory error correction on the data stored in the first-class memory particles.

[0015] For example, the controller performs a first-level memory error correction on data stored in the first-class memory particles of the same group in the storage-class memory, including: the controller uses a Hamming code or a block code to perform a first-level memory error correction on the data stored in the first-class memory particles of the same group in the storage-class memory. The controller performs a first-level memory error correction on a single bit in 128 bytes to 512 bytes of the data stored in the first-class memory particles of the same group in the storage-class memory.

[0016] For example, the controller performs secondary memory error correction on the data stored in the first type of memory particles, including: the controller uses a block code or a low-density parity check code to perform secondary memory error correction on the data stored in the first type of memory particles. The controller performs secondary memory error correction on hundreds of bits in 2048 bytes to 4096 bytes of the data stored in the first type of memory particles.

[0017] In a possible implementation, the method further includes: the controller converting the processor's instructions into storage-class memory instructions, and converting the storage-class memory instructions into processor instructions, so as to facilitate the processor to perform read and write operations on the storage-class memory.

[0018] In a third aspect, a processor system is provided, which includes a controller and the above-mentioned first aspect or any possible storage-level memory and processor of the first aspect, the controller is respectively connected to the processor and at least one storage-level memory, and the controller is used to execute the operating steps of the method described in the above-mentioned second aspect or any possible method of the second aspect.

[0019] Based on the implementations provided in the above aspects, this application can also be further combined to provide more implementations. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 A schematic diagram of the structure of a storage-level memory provided in an embodiment of the present application;

[0021] Figure 2 A schematic diagram of the physical division of a storage-level memory provided in an embodiment of the present application;

[0022] Figure 3 A schematic diagram of the structure of a first type of memory particle provided in an embodiment of the present application;

[0023] Figure 4 A schematic diagram of generating a running error correction code and a heavy error correction code provided in an embodiment of the present application;

[0024] Figure 5 A schematic diagram of the structure of another storage-level memory provided in an embodiment of the present application;

[0025] Figure 6 A schematic diagram of the structure of another storage-level memory provided in an embodiment of the present application;

[0026] Figure 7 A schematic diagram of the structure of a processor system provided in an embodiment of the present application;

[0027] Figure 8 A schematic diagram of the structure of another processor system provided in an embodiment of the present application;

[0028] Fig. 9 A schematic diagram of a data processing method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0029] In digital circuits, the smallest unit of data is a bit, which is also the smallest unit of data in memory (or main memory). The value of a bit is "0" or "1", and 8 consecutive bits constitute a byte. In machine language, a byte represents a letter or number. Electric fields, magnetic fields, and even cosmic ray interference can cause the value of a single bit stored in memory to change. If the value of a single bit in a byte that is important for system operation changes, system errors may occur, leading to downtime or other failures.

[0030] Error Correcting Code (ECC) is a technology that can detect and correct errors. Error-correcting code memory (ECC memory) is a memory that uses ECC technology, that is, a memory that can detect and correct errors. Error-correcting memory is mostly used in servers and graphic workstations to improve the stability and reliability of computer operation.

[0031] The embodiment of the present application provides a storage-class memory, and in particular, provides a storage-class memory with high reliability and low latency, that is, the access latency is as low as possible while ensuring the high reliability of the storage-class memory storage data through a two-level memory error correction mechanism. In addition, by arranging the memory particles of the storage-class memory, the bit width of the storage-class memory meets the memory bit width indicated by the double data rate (Double Data Rate, DDR) protocol, thereby achieving storage-class memory compatibility with the DDR protocol, so that the storage-class memory can be connected to more types of processors (processor), thereby improving the versatility of the storage-class memory.

[0032] In the embodiment of the present application, the memory particle may refer to a phase change memory (PCM). Phase change memory is a storage device that uses the difference in conductivity exhibited by special materials (such as chalcogenides) when they transform between crystalline and amorphous states to store data. Memory bit width refers to the amount of data that the memory can transmit at one time. The larger the bit width, the larger the amount of data that can be transmitted at one time. Memory bit width can also be called data bit width or simply bit width.

[0033] The multiple memory particles included in the storage-class memory are divided into at least one group. Each of the at least one group includes a first type of memory particles and a second type of memory particles. Understandably, at least one group refers to at least one channel of DDR. The number of the first type of memory particles and the number of the second type of memory particles in each group are determined based on the bit width of the first type of memory particles, the bit width of the second type of memory particles, and the memory bit width indicated by the DDR protocol, so that the bit width of the storage-class memory meets the memory bit width indicated by the DDR protocol.

[0034] The second type of memory particles are used to store running error correction codes. The running error correction codes are used to perform first-level memory error correction on the data stored in the first type of memory particles in the same group. It should be understood that the running error correction codes can be generated based on the data stored in the first type of memory particles belonging to the same group. First-level memory error correction refers to memory error correction for the data stored in the first type of memory particles belonging to the same group. For example, the running error correction codes stored in the second type of memory particles included in the first group are generated based on the data stored in the first type of memory particles included in the first group. The running error correction codes stored in the second type of memory particles included in the first group are used to perform first-level memory error correction on the data stored in the first type of memory particles included in the first group.

[0035] The first type of memory particles are used to store data and heavy error correction codes. The heavy error correction codes are used to perform secondary memory error correction on the data stored in the first type of memory particles when the primary memory error correction fails. It should be understood that the heavy error correction codes can be generated based on the data stored in the first type of memory particles. Secondary memory error correction refers to memory error correction for the data stored in each first type of memory particle. For example, the heavy error correction codes stored in the first type of memory particles included in the first group are generated based on the data stored in the same first type of memory particles. The heavy error correction codes stored in the first type of memory particles included in the first group are used to perform secondary memory error correction on the data stored in the same first type of memory particles.

[0036] In various embodiments of the present application, the running error correction code may also be referred to as a first-level correction code, and the heavy error correction code may also be referred to as a second-level correction code.

[0037] In other embodiments, the first-class memory particles are also used to implement the function of bad block management for the first-class memory particles. Compared with setting memory particles for implementing bad block management on storage-class memory, setting a medium for implementing bad block management in the first-class memory particles saves storage-class memory space, makes storage-class memory more compatible with memory that meets the DDR protocol (such as DRAM), and improves the versatility of storage-class memory.

[0038] Storage-class memory can also include other chips, such as clock chips.

[0039] The storage-level memory provided in the embodiments of the present application is described in detail below with reference to the accompanying drawings.

[0040] Take the storage-class memory compatible with DDR5 with a memory width of 80 bits as an example. Figure 1A schematic diagram of the structure of a storage-class memory provided for an embodiment of the present application. The storage-class memory 100 includes 10 memory particles 110, and the bit width of each memory particle 110 is 8 bits. The 10 memory particles 110 are divided into 2 groups, each group includes 5 memory particles 110, and the sum of the bit widths of the 5 memory particles 110 included in each group is 40 bits. The sum of the bit widths of the 5 memory particles 110 included in the 2 groups is 80 bits, and the storage-class memory 100 is compatible with the memory bit width of DDR5. It can be understood that the 2 groups obtained by dividing the 10 memory particles 110 refer to the 2 sub-channels of DDR5, which are compatible with the dual-channel standard of DDR5. The bit width of each sub-channel is 40 bits.

[0041] Each group includes 4 first-class memory particles 111 and 1 second-class memory particle 112. The unit access data amount of each bit in the bit width of the memory particle 110 is 16 bytes or 32 bytes, that is, each time the storage-level memory is accessed, 16B or 32B of data can be obtained after a certain delay. If 4 first-class memory particles 111 are accessed at a time, 64B of data can be read or written. If 8 first-class memory particles 111 are accessed at a time, 128B of data can be read or written. 64B or 128B is equal to the cache line length of the processor, thereby improving the versatility of the storage-level memory.

[0042] The second type of memory particles 112 are used to store the running error correction code. The first type of memory particles 111 are used to store data and the heavy error correction code. The length of the running error correction code codeword is determined by the first type of memory particles 111 and the second type of memory particles 112 in the group. For example, if 64B of data can be read or written by accessing 4 first type memory particles 111 at a time, the length of the running error correction code codeword is 64B+16B; if 128B of data can be read or written by accessing 8 first type memory particles 111 at a time, the length of the running error correction code codeword is 128B+32B. The heavy error correction code can set the length of the heavy error correction code codeword according to the reliability requirements.

[0043] Understandably, if Figure 2 As shown, the physical division of the storage class memory 100 can be divided into a plane (rank) 120, a memory chip (chip) 110, a unit (bank) 130 and a storage unit (cell) 140 from large to small. The plane 120 includes all memory chips 110 installed on the storage class memory 100. Each memory chip 110 includes a plurality of units 130. Each unit 130 includes a storage unit 140. Each storage unit 140 is determined by a row (row) and a column (column).

[0044] In some embodiments, the medium used by the first-type memory cell 111 to store the heavy error correction code may be a part of the cells 130 of the multiple cells 130 included in the first-type memory cell 111. For example, the first-type memory cell 111 includes M first-type cells 131 and N second-type cells 132. The first-type cells 131 are used to store data. The second-type cells 132 are used to store the heavy error correction code. In practical applications, the number M of the first-type cells 131 and the number N of the second-type cells 132 can be flexibly configured according to reliability requirements. If the reliability requirement is low and the amount of data for secondary memory error correction is small, fewer second-type cells 132 and more first-type cells 131 can be configured; if the reliability requirement is high and the amount of data for secondary memory error correction is large, more second-type cells 132 can be configured. The number M of the first-type cells 131 and the number N of the second-type cells 132 can be switched or upgraded online by the memory controller or firmware (firmware, FW) according to the usage scenario, thereby improving the flexibility of adapting to different system reliability requirements.

[0045] For example, Figure 3 As shown, the first type memory particle 111 includes 16 independently operable units 130. The first unit 130 to the 14th unit 130 are used as the first type unit 131 for storing data. The 15th unit 130 is used as the second type unit 132 for performing secondary memory error correction. Optionally, the 16th unit 130 in the first type memory particle 111 is used as the third type unit 133 to implement the function of bad block management of the unit 130 of the first type memory particle 111. When a unit among the first unit 130 to the 15th unit 130 fails, the 16th unit 130 can be used to replace the failed unit 130, thereby avoiding the storage class memory 100 from failing. For example, when some addresses of a unit among the first unit 130 to the 15th unit 130 are damaged, the controller remaps the corresponding 16B address to the reserved 16th unit 130, so as to implement the bad block management function.

[0046] The access unit 130 can read or write 16B or 32B of data at a time. Assuming that the access unit 130 can read or write 16B of data at a time, the length of the heavy error correction code word can be 224B (16*14) + 16B. Since the heavy error correction code word is longer, the error correction capability of the secondary memory error correction is also stronger. This is only one of the ways to construct the heavy error correction code word. In other embodiments, the data stored in some of the first-class units 131 in multiple first-class units 131 can also be used to construct the heavy error correction code word. During the secondary memory error correction, the units 130 included in the first-class memory particles 111 are cyclically checked for errors and corrected.

[0047] For example, Figure 4As shown, the data of the primary memory error correction and the data of the secondary memory error correction can form a two-dimensional matrix. The x dimension represents four first-class memory particles 111 and one second-class memory particle 112, and the y dimension represents the address of the minimum access unit 16B of the memory particle. The four first-class memory particles 111 store data and heavy error correction codes, and the one second-class memory particle 112 stores running error correction codes. Each row constitutes a 64B+16B running error correction code codeword, and the entire two-dimensional matrix constitutes a 512B+208B heavy error correction code codeword. When the running error correction code decoding of any row fails, the system reads out the two-dimensional matrix data for secondary memory error correction, that is, performs secondary memory error correction on the data of each column. The system can perform horizontal decoding and vertical decoding in parallel, effectively reducing the error correction rate of the system.

[0048] In some embodiments, the data of the first type memory cell 111 in each column of the two-dimensional matrix may be data of any eight cells 130 from the first cell 130 to the fourteenth cell 130, and the eight cells 130 may be continuous. For example, the data of the first type memory cell 111 in the first column may be data from the first cell 130 to the eighth cell 130, and the heavy error correction code stored in the first type memory cell 111 in the first column is generated based on the data from the first cell 130 to the eighth cell 130. The heavy error correction code stored in the first type memory cell 111 in the first column performs memory error correction on the data from the first cell 130 to the eighth cell 130.

[0049] For another example, the data of the first type memory cell 111 in the second column may be the data of the third unit 130 to the tenth unit 130, and the heavy error correction code stored in the first type memory cell 111 in the second column is generated based on the data of the third unit 130 to the tenth unit 130. The heavy error correction code stored in the first type memory cell 111 in the second column performs memory error correction on the data of the third unit 130 to the tenth unit 130.

[0050] In addition, the first type memory cell 111 is selected according to the reliability requirement for generating the data of the heavy error correction code, that is, if the reliability requirement is high, each column in the two-dimensional matrix includes more data of the cells 130; if the reliability requirement is low, each column in the two-dimensional matrix includes less data of the cells 130. The second type cells 132 in the first type memory cell 111 can store the heavy error correction code generated by different first type cells 131, for example, the second type cells 132 in the first type memory cell 111 in the first column can store the heavy error correction code generated according to the data of the first cell 130 to the eighth cell 130, and the heavy error correction code generated according to the data of the third cell 130 to the tenth cell 130. This allows the controller to perform memory error correction on the data of different first type cells 131.

[0051] The error correction algorithms used in the primary memory error correction and the secondary memory error correction provided in the embodiments of the present application include any one of a parity check code, a Hamming code, a block code, and an error correction code. The error correction algorithm used in the primary memory error correction and the error correction algorithm used in the secondary memory error correction can be the same or different, without limitation.

[0052] In one example, the first-level memory error correction can reuse the error correction method of DDR5. For example, the first-level memory error correction can use Hamming code or block code. Since the memory error correction method of DDR5 has low latency, the error correction capability can cover most error scenarios of storage-level memory. Therefore, when the error rate of storage-level memory is low, it can ensure the high reliability of storage-level memory data storage and effectively reduce access latency.

[0053] When the primary memory error correction cannot correct the error or the error correction fails, the secondary memory error correction can be performed using the heavy error correction code in a single or multiple first-class memory particles 111. For example, the secondary memory error correction can use a block code or a low-density parity check code. When the error rate of the storage-level memory is high, the secondary memory error correction can effectively reduce the error rate of the storage-level memory, ensure the high reliability of the storage-level memory data, and extend the service life of the storage-level memory.

[0054] The above example shows that the first-level memory error correction is set between the first-class memory particles 111, that is, the running error correction codeword is constructed using the data of the first-class memory particles 111 belonging to the same group (channel), and the second-level memory error correction is set within the first-class memory particles 111, that is, the heavy error correction codeword is constructed using the data of the first-class memory particles 111. In actual applications, the two-level memory error correction of the storage-class memory can also be set in other ways.

[0055] The above embodiment is described by taking the memory chip bit width of 8 bits as an example. In another embodiment, the memory chip bit width used by the storage-class memory may also be 4 bits.

[0056] For example, Figure 5 As shown, the storage-class memory 500 includes 20 memory particles 510, and the bit width of each memory particle 510 is 4 bits. The 20 memory particles 510 are divided into 4 groups, each group includes 5 memory particles 510, and the sum of the bit widths of the 5 memory particles 510 included in each group is 20 bits. The sum of the bit widths of the 20 memory particles 510 included in the 4 groups is 80 bits, so the storage-class memory 500 is compatible with the memory bit width of DDR5. Each group includes 4 first-class memory particles 511 and 1 second-class memory particle 512.

[0057] Alternatively, if Figure 6As shown, the 20 memory particles 510 included in the storage-class memory 500 can also be divided into 2 groups, each group includes 10 memory particles 510, and the sum of the bit widths of the 10 memory particles 510 included in each group is 40 bits. The sum of the bit widths of the 20 memory particles 510 included in the 2 groups is 80 bits, and the storage-class memory 500 is compatible with the memory bit width of DDR5. Each group includes 9 first-class memory particles 511 and 1 second-class memory particle 512.

[0058] For a detailed explanation of the first-type memory cell 511 and the one second-type memory cell 512 , reference may be made to the above description of the first-type memory cell 111 and the one second-type memory cell 112 .

[0059] When the storage-class memory is used as the main memory, the storage-class memory can be installed on the computer device using a dual-inline-memory-module (DIMM) interface, so that the processor of the computer device can read and write the storage-class memory. The computer device can be an independent server or a computing device in a computing cluster.

[0060] A controller is also required between the storage-level memory and the processor, and the controller is used to implement functions such as instruction conversion, memory error correction, bad block management, and address mapping. Compared with the solution in which the built-in controller of the storage-level memory implements memory error correction, and the DRAM cache data connected to the controller causes uncertainty in the access delay of the SCM, the storage-level memory provided in the embodiment of the present application does not require a built-in controller and DRAM, and uses the memory controller of the processor connected to the storage-level memory to control the storage-level memory, or connects other controllers between the processor and the storage-level memory to control the storage-level memory and ensure deterministic latency in accessing the storage-level memory, which is compatible with the DDR protocol.

[0061] Figure 7 A schematic diagram of a processor system provided in an embodiment of the present application. The processor system 700 includes a controller 710, a storage-level memory 720, and a processor 730. The processor system 700 may be a computer device, a server, or a computing device in a computing cluster.

[0062] The processor 730 is the computing core and control core of the processor system 700. The processor 730 can be a very large scale integrated circuit. The operating system 731 and other software programs are installed in the processor 730, so that the processor 730 can access the storage-level memory 720 and various peripheral component interconnect express (PCIe) devices. The processor 730 includes one or more processor cores 732. The processor core 732 in the processor 730 is, for example, a central processing unit (CPU) or other specific integrated circuit (ASIC). The processor 730 can also be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc. In practical applications, the processor system 700 may also include multiple processors.

[0063] In the embodiment of the present application, the processor 730 is used to write data to the storage-level memory 720 or read data from the storage-level memory 720.

[0064] The storage-class memory 720 may be the main memory of the processor system 700. The storage-class memory 720 is generally used to store various running software in the operating system 731, input and output data, and information exchanged with external memory. In order to improve the access speed of the processor 730, the storage-class memory 720 needs to have the advantage of fast access speed. The processor 730 can access the storage-class memory 720 at high speed through the controller 710, and perform read and write operations on any storage unit in the storage-class memory 720.

[0065] The controller 710 is a bus circuit controller that controls the storage-level memory 720 within the processor system 700 and is used to manage and plan data transmission from the storage-level memory 720 to the processor core 732. Through the controller 710, data can be exchanged between the storage-level memory 720 and the processor core 732.

[0066] The controller 710 may be integrated into the processor 730, or may be built into the north bridge, or may be an independent memory controller chip. The controller 710 may be a separate chip and connected to the processor core 732 via a system bus. For example, Figure 7 The processor systems shown differ in that Figure 8 As shown, the controller 710 may be an external controller between the storage-class memory 720 and the processor 730. The external controller may be a centralized controller, which may be connected to a plurality of storage-class memories 720, thereby expanding the storage capacity of the main memory of the processor system, making the storage-class memory more compatible with the DDR protocol, and reducing the cost of the controller.

[0067] The embodiment of the present application does not limit the specific location and existence form of the memory controller. In practical applications, the controller 710 can control the necessary logic to write data to the storage-level memory 720 or read data from the storage-level memory 720. The controller 710 can be a memory controller in a processor system such as a general-purpose processor, a dedicated accelerator, a GPU, an FPGA, an embedded processor, etc.

[0068] The processor system 700 also includes various input / output (I / O) devices 740. The I / O device 740 refers to the hardware for data transmission, and can also be understood as a device connected to the I / O interface. Common I / O devices include network cards, printers, keyboards, mice, etc. All external memories can also be used as I / O devices, such as hard disks, floppy disks, optical disks, etc.

[0069] The processor 730, the storage-class memory 720, the controller 710, and the I / O device 740 are connected via a bus 750. The bus 750 may include a path for transmitting information between the above components (such as the processor 730 and the storage-class memory 720). In addition to the data bus, the bus 750 may also include a power bus, a control bus, and a status signal bus. However, for the sake of clarity, various buses are labeled as bus 750 in the figure. Bus 750 may be a PCIe bus, or an extended industry standard architecture (EISA) bus, a unified bus (Ubus or UB), a computer express link (CXL), a cache coherent interconnect for accelerators (CCIX), etc. For example, the processor 730 can access these I / O devices 740 via the PCIe bus. The processor 730 is connected to the storage-class memory 720 via a double data rate (DDR) bus. Here, different storage-level memories 720 may use different data buses to communicate with the processor 730. Therefore, the DDR bus may also be replaced with other types of data buses. The embodiment of the present application does not limit the bus type.

[0070] The processor system 700 also includes a DPU 760, which can be connected to the processor 730 via a PCIe bus. The DPU 760 unloads applications related to artificial intelligence, storage, etc. that are run by other chips of the processor system 700 (such as the processor 730), improves the data processing performance of the processor system 700, and reduces the load of the processor system 700. The processor system 700 may also include other dedicated processors. A dedicated processor is a processor for a specific application or field. For example, a graphics processing unit (GPU) for processing image data or a DSP for processing signals.

[0071] It should be noted that the processor system 700 may be referred to as a host. Figure 7 This is just a schematic diagram. The processor system 700 may also include other components, such as a hard disk, an optical drive, a power supply, a chassis, a cooling system, and other input and output controllers and interfaces. Figure 7 The embodiment of the present application does not limit the number of processors, storage-level memories, and controllers included in the processor system 700.

[0072] Next, Fig. 9A schematic diagram of a data processing method provided in an embodiment of the present application. Figure 7 The structure shown is used as an example for explanation. Assume that the processor 730 writes or reads data to the storage-level memory 720. The data processing method provided in the embodiment of the present application includes the following steps.

[0073] In some embodiments, the processor 730 executes S910 to S930 when writing data to the storage-level memory 720 .

[0074] S910 , the controller 710 performs instruction conversion, that is, the controller 710 converts the write instruction of the processor 730 into a write instruction that can be recognized by the storage-level memory 720 .

[0075] S920 : The controller 710 generates a running error correction code and a heavy error correction code according to the data to be written.

[0076] The controller 710 determines the location of the first type of memory particles in the storage-class memory 720 where the data to be written is written. For example, the controller 710 performs address mapping, that is, converting the logical block address into a physical block address. The logical block address (Logic Block Address, LBA) describes the virtual address of the block where the data is located on the storage device, and is generally used in auxiliary memory devices such as hard disks. LBA can refer to the address of a data block or the data block pointed to by a certain address. The physical block address (Physical Block Address, PBA) describes the physical address of the block where the data is located on the storage device. There is a one-to-one mapping relationship between LBA and PBA, and the mapping relationship is usually stored in the main memory. In the embodiment of the application, the mapping relationship between LBA and PBA can be stored in the storage-class memory. When the controller 710 determines to write the data to be written into the storage-class memory 720, it first determines the logical block address, and then determines the physical block address of the storage-class memory 720 based on the logical fast address and the mapping relationship between LBA and PBA, and writes the data to be written into the storage-class memory 720 according to the physical block address.

[0077] Furthermore, the controller 710 generates a running error correction code based on an error correction algorithm (such as Hamming code or block code) using the data written into the same group of first-class memory particles in the data to be written, and generates a heavy error correction code based on an error correction algorithm (such as block code or low-density parity-check code) using the data written into the same first-class memory particles.

[0078] S930 , the controller 710 writes the running error correction code, the heavy error correction code and the data to be written into the storage-level memory 720 .

[0079] The controller 710 writes the data to be written into the determined location of the first type of memory cell, writes the running error correction code into the second type of memory cell, and writes the heavy error correction code into the second type of unit of the first type of memory cell.

[0080] In other embodiments, the processor 730 executes S940 to S970 when reading data from the storage-level memory 720 .

[0081] S940 , the controller 710 performs instruction conversion, that is, the controller 710 converts the read instruction of the processor 730 into a read instruction that can be recognized by the storage-level memory 720 .

[0082] S950 , the controller 710 reads data from the storage-level memory 720 , and runs an error correction code and a re-error correction code.

[0083] The controller 710 determines the storage location of the data in the storage-level memory 720, that is, first determines the logical block address, and then determines the physical block address of the storage-level memory 720 based on the logical fast address and the mapping relationship between LBA and PBA, and reads data from the storage-level memory 720 according to the physical block address.

[0084] S960, the controller 710 performs primary memory error correction on the read data, that is, uses the running error correction code to check the read data.

[0085] In some embodiments, the controller 710 determines the storage location of the data, reads the data and runs the error correction code according to the storage location. The controller 710 generates a temporary running error correction code using the read data based on an error correction algorithm (such as a Hamming code or a block code), compares the temporary running error correction code with the running error correction code, and if the temporary running error correction code and the running error correction code are the same, it indicates that the read data is correct; if the temporary running error correction code and the running error correction code are different, it indicates that there is an error in the read data. If the read data does not match the stored code, the read data can be decrypted using the parity bit to determine which bit is wrong, and then the wrong bit is corrected.

[0086] Optionally, if the primary memory error correction fails, S970 is executed and the controller 710 performs secondary memory error correction, that is, uses a heavy error correction code to check the data of the first type of memory particles. For example, the controller 710 uses a block code or a low-density parity check code to perform secondary memory error correction on the data stored in the first type of memory particles using a heavy error correction code.

[0087] During data processing, the controller 710 may use an algorithm (eg, Hamming code) to continuously scan the data to check and correct each bit of memory error.

[0088] The embodiment of the present application does not limit the method for determining the location where the controller 710 writes data into the storage-level memory 720 and the location where the data is read from the storage-level memory 720, and reference may be made to the prior art. Also, the method for generating the running error correction code and the re-error correction code, and the method for verifying the read data using the running error correction code and the re-error correction code may also reuse the prior art.

[0089] It is understandable that in order to implement the functions in the above embodiments, the computing device includes hardware structures and / or software modules corresponding to the execution of each function. Those skilled in the art should easily realize that, in combination with the units and method steps of each example described in the embodiments disclosed in this application, the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is executed in the form of hardware or computer software driving hardware depends on the specific application scenario and design constraints of the technical solution.

[0090] The method steps in this embodiment can be implemented by hardware or by a processor executing software instructions. The software instructions can be composed of corresponding software modules, which can be stored in random access memory (RAM), flash memory, read-only memory (ROM), programmable ROM (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disks, mobile hard disks, CD-ROMs, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor so that the processor can read information from the storage medium and write information to the storage medium. Of course, the storage medium can also be a component of the processor. The processor and the storage medium can be located in an ASIC. In addition, the ASIC can be located in a computing device. Of course, the processor and the storage medium can also exist as discrete components in a network device or a terminal device.

[0091] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented by software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer programs or instructions. When the computer program or instruction is loaded and executed on a computer, the process or function described in the embodiment of the present application is executed in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, a network device, a user device or other programmable device. The computer program or instruction may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer program or instruction may be transmitted from one website site, computer, server or data center to another website site, computer, server or data center by wired or wireless means. The computer-readable storage medium may be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium may be a magnetic medium, for example, a floppy disk, a hard disk, a tape; it may also be an optical medium, for example, a digital video disc (DVD); it may also be a semiconductor medium, for example, a solid state drive (SSD).

[0092] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed in the present application, and these modifications or replacements should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A storage-class memory, characterized in that: The storage-class memory includes a plurality of memory particles, and the plurality of memory particles are divided into at least one group; a first group in the at least one group includes a first type of memory particles and a second type of memory particles; The second type of memory particles are used to store running error correction codes, and the running error correction codes are used to perform primary memory error correction on data stored in the first type of memory particles in the first group; The first type of memory particles are used to store data and heavy error correction codes, and the heavy error correction codes are used to perform secondary memory error correction on the data stored in the first type of memory particles when the first level memory error correction of the data stored in the first type of memory particles using the error correction code fails.

2. The storage-class memory according to claim 1, wherein: The first type of memory particles include M first type units and N second type units, the first type units are used to store data, and the second type units are used to store the heavy error correction code.

3. The storage-class memory according to claim 2, wherein: The unit access data volume of the first type of unit and the unit access data volume of the second type of unit are both the unit access data volume of one bit in the bit width of the first type of memory particles.

4. The storage class memory according to any one of claims 1 to 3, characterized in that: The first-type memory particle also includes a third-type unit, and the third-type unit is used to implement a bad block management function for the unit of the first-type memory particle.

5. The storage class memory according to any one of claims 1 to 4, characterized in that: The bit width of the storage-class memory satisfies the memory bit width indicated by the double data rate DDR protocol.

6. The storage class memory according to claim 5, characterized in that: The number of the first type of memory particles and the number of the second type of memory particles in each group are determined according to the bit width of the first type of memory particles, the bit width of the second type of memory particles and the memory bit width indicated by the DDR protocol.

7. The storage class memory according to claim 6, characterized in that: The memory bit width indicated by the DDR protocol is 80 bits, the bit width of the first type of memory particles and the bit width of the second type of memory particles are both 8 bits, and the 10 memory particles contained in the storage-class memory are divided into 2 groups, each group includes 4 first type of memory particles and 1 second type of memory particle; the sum of the bit widths of the 4 first type of memory particles and 1 second type of memory particle contained in each group is 40 bits, and the unit access data amount of each bit is 16 bytes or 32 bytes.

8. A data processing method, characterized in that: The method is executed by a controller, the controller is connected to at least one storage-class memory, the storage-class memory includes a plurality of memory particles, the plurality of memory particles are divided into at least one group, a first group of the at least one group includes a first type of memory particles and a second type of memory particles. The method includes: The controller performs a first-level memory error correction on the data stored in the first-type memory particles of the first group in the storage-level memory; When the primary memory error correction fails, the controller obtains data of the first-type memory particles and performs secondary memory error correction on the data stored in the first-type memory particles.

9. The method according to claim 8, characterized in that The controller performs primary memory error correction on the data stored in the first type of memory particles, including: The controller uses Hamming code or block code to perform primary memory error correction on the data stored in the first type of memory particles in the storage-level memory; The controller performs secondary memory error correction on the data stored in the first type of memory particles, including: The controller uses block codes or low-density parity check codes to perform secondary memory error correction on the data stored in the first type of memory particles.

10. The method according to claim 8 or 9, characterized in that: The controller performs primary memory error correction on the data stored in the first type of memory particles, including: The controller performs memory error correction on a single bit in 128 bytes to 512 bytes of data stored in the first type of memory particles; The controller performs secondary memory error correction on the data stored in the first type of memory particles, including: The controller performs secondary memory error correction on hundreds of bits in 2048 bytes to 4096 bytes of data stored in the first type of memory particles.

11. The method according to any one of claims 8 to 10, characterized in that: The method further comprises: The controller converts instructions from the processor into instructions from the storage class memory, and converts instructions from the storage class memory into instructions from the processor.

12. A processor system, characterized in that: The processor system includes a controller and at least one storage-level memory and a processor as described in any one of claims 1-7, wherein the controller is respectively connected to the processor and at least one storage-level memory, and the controller is used to execute the operating steps of the method described in any one of claims 8-11.

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