Digital time taming and signal synchronization correction method

Abstract

The invention discloses a digital time taming and signal synchronization correction method, which comprises the following steps that: a reference node sends a synchronization sequence, and the synchronization sequence modulates the reference node time at the sending moment; the synchronization node receives the synchronization sequence and obtains synchronous digital time by adopting a digital time taming mode; and the synchronous node realizes synchronous correction of the signal based on the obtained synchronous digital time. According to the digital time taming and signal synchronization correction method provided by the invention, a burst transmission mode is adopted to send a synchronization signal, and a receiving node rapidly captures and adopts a dynamic interval loop tracking method, so that flexible channel time division multiplexing can be realized. The synchronous time is obtained in a digital time taming mode, synchronous correction of the signals is achieved through resampling on the basis of the synchronous digital time, the problem that a sampling clock is not synchronous is prevented from being coupled to a subsequent signal processing flow, and meanwhile dependence on a programmable crystal oscillator is also avoided.

Description

Technical Field

[0001] The invention belongs to the technical field of time synchronization, and in particular relates to a digital time taming and signal synchronization correction method. Background Art

[0002] In some large-scale whole machine systems and distributed systems, in order to achieve the coordinated control of various functional components in the system and the fusion of sensor signals, relative time synchronization is a basic problem in system construction and is often a key factor affecting the final performance of the system. For example, in the field of autonomous driving, multi-source heterogeneous sensors such as lidar and visual cameras need to have synchronized time tags to ensure correct decision-making; in similar rail transit fields, time synchronization between railway bureaus and stations and between detection systems such as tracks and contact networks on trains is also a prerequisite for realizing intelligent train operation and maintenance; in wide-area power systems, physical quantities such as voltage and current that are strongly related to time need to be collected and controlled in real time and synchronously to achieve timely and accurate fault detection and location; in large-scale experimental equipment, the synchronization accuracy requirements for multi-node data acquisition and control can even reach the picosecond level. With the high-speed, intelligent, and precise development of various system equipment, the requirements for time synchronization accuracy are becoming more and more stringent. It is very necessary to develop a high-precision and highly applicable time synchronization method.

[0003] The widely used relative time synchronization solutions can be divided into the following three categories:

[0004] The first is the timing scheme based on the Global Navigation Satellite System (GNSS). The satellite sends out the second pulse signal through pseudo code modulation. The ground equipment passively receives the information of multiple satellite stations, calculates the position information, compensates for the propagation delay, and obtains the synchronization time. This scheme has the advantages of simple equipment, wide application, and mature technology. However, relatively speaking, the delay correction model for the ionosphere and troposphere is imperfect, the positioning accuracy is limited, and the operation differences of each satellite also lead to jitters of 10 nanoseconds in synchronization accuracy. In addition, the strength of the GNSS signal is affected by the environment and there is a risk of being deceived. It is not suitable for occasions with high safety requirements such as vehicle control systems.

[0005] The second is the network-based time synchronization protocol. The mainstream ones, such as Network Time Protocol (NTP), Precise Time Protocol (PTP) and White Rabbit Precise Time Protocol (WR-PTP), all use two-way communication to achieve time transfer. The popularity of the Internet has made NTP based on UDP (User Datagram Protocol) widely used for time synchronization of personal computers, but the synchronization accuracy of NTP can only reach the millisecond level, while the more accurate PTP and WR-PTP rely on hardware-level timestamp marking, and even require the code stream timing recovery information of the optical fiber Ethernet physical layer, and the support of network equipment such as dedicated switches, and the link laying cost is relatively high.

[0006] The third is the synchronization scheme based on a custom communication protocol, which is commonly used in communication scenarios such as radio and underwater acoustics. This scheme can communicate and achieve synchronization according to the channel conditions that can be provided by the application scenario. The synchronization accuracy achieved is related to the communication bandwidth and signal-to-noise ratio supported by the channel, and it is more adaptable to the scenario. With the development of programmable devices such as field-programmable gate arrays (FPGAs), this type of scheme has gradually gained popularity due to its application-oriented customization advantages. As far as the current implementation scheme is concerned, there are two limitations: (1) In the time transfer scheme, it is usually necessary to continuously track the synchronization signal or track it within a fixed time window, which is difficult to apply to occasions where channel resources are tight and the channel needs to be flexibly time-divided. (2) In terms of time taming, the scheme of taming digital time does not need to rely on peripheral devices such as programmable crystal oscillators compared to the scheme of taming programmable crystal oscillators, but related studies have not considered the problem of physical sampling clock asynchrony after digital time taming. Summary of the invention

[0007] The present invention provides a digital time taming and signal synchronization correction method to solve the above-mentioned technical problems, and specifically adopts the following technical solutions:

[0008] A digital time discipline and signal synchronization correction method, comprising:

[0009] The reference node sends a synchronization sequence, which modulates the reference node time at the time of sending;

[0010] The synchronization node receives the synchronization sequence and obtains the synchronized digital time by adopting the digital time taming method;

[0011] The synchronization node implements synchronization correction of the signal based on the obtained synchronized digital time.

[0012] Furthermore, the reference node sends the synchronization sequence in a burst transmission manner.

[0013] Furthermore, the synchronization node adopts a dynamic interval loop tracking method to complete the timing recovery of the burst synchronization signal and the dynamic interval taming of the digital time.

[0014] Furthermore, the synchronization node adopts a composite loop structure to complete the timing recovery of the burst synchronization signal and the dynamic interval taming of the digital time.

[0015] Further, the composite loop structure includes a symbol tracking loop and a timing tracking loop;

[0016] The symbol tracking loop is used to extract the precise delay of the synchronization sequence. The timing tracking loop compares the receiving time information obtained based on the tracking of each synchronization sequence with the sending time information of the synchronization sequence, and tames the digital time to make the two time information the same.

[0017] Furthermore, the synchronization node performs carrier deviation compensation and resampling based on the obtained synchronization digital time to achieve signal synchronization correction.

[0018] Furthermore, the synchronization sequence includes multiple synchronization symbols, which are used for data message modulation.

[0019] Furthermore, the synchronization code element adopts spread spectrum technology.

[0020] Furthermore, the spread spectrum technology is one of direct sequence spread spectrum and linear frequency modulation.

[0021] Furthermore, during data modulation, only the phase of the synchronization symbol is modulated.

[0022] The benefit of the present invention lies in the digital time taming and signal synchronization correction method provided, which realizes a high-precision and high-applicability digital time taming and signal synchronization correction method. The method uses burst transmission to send synchronization signals, and the receiving node quickly captures and adopts a dynamic interval loop tracking method to realize flexible channel time-division multiplexing. The synchronization time is obtained by digital time taming, and the synchronization correction of the signal is realized by resampling on the basis of the synchronized digital time, which avoids the problem of sampling clock asynchrony being coupled to the subsequent signal processing process, and also avoids the dependence on programmable crystal oscillators.

[0023] The digital time training and signal synchronization correction method provided by the present invention, on the one hand, improves the applicability to application scenarios. For occasions where hardware resources are tight or system power consumption is demanding, it supports dynamic interval transmission of synchronization signals to achieve flexible time-division multiplexing; on the other hand, it improves the applicability to hardware platforms, avoids dependence on peripheral circuits such as programmable crystal oscillators, and realizes synchronous acquisition and transmission of signals. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0025] Figure 1 A schematic diagram of a digital time taming and signal synchronization correction method of the present application;

[0026] Figure 2 is a schematic diagram of a synchronization signal for transmitting time;

[0027] Figure 3 It is a schematic diagram of synchronous sequence transmission;

[0028] Figure 4 A schematic diagram of sequence capture;

[0029] Figure 5 This is a schematic diagram of the implementation of sequence peak value verification;

[0030] Figure 6 Schematic diagram of the symbol tracking loop;

[0031] Figure 7 This is a schematic diagram of the timing tracking loop;

[0032] Figure 8 This is a schematic diagram of a carrier deviation compensation module;

[0033] Fig. 9 Schematic diagram of the resampling process;

[0034] Fig.10 It is a schematic diagram of the cross-time domain conversion of the original resampling interface;

[0035] Fig.11 The present invention is a schematic diagram of a specific implementation method of the present application under wireless communication conditions. DETAILED DESCRIPTION

[0036] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be construed as limiting the present application.

[0037] like Figure 1 As shown, the present application discloses a digital time taming and signal synchronization correction method, comprising:

[0038] S1: The reference node sends a synchronization sequence, which modulates the reference node time at the time of transmission.

[0039] S2: The synchronization node receives the synchronization sequence and obtains the synchronized digital time by adopting the digital time discipline method.

[0040] S3: The synchronization node implements synchronization correction of the signal based on the obtained synchronized digital time.

[0041] Specifically, the node that provides the time reference is called the "reference node", and the node that receives the reference node signal for synchronization is called the "synchronization node". The synchronization signal used in this application to transmit time is in the form of Figure 2 , the reference node can send a synchronization sequence at any burst transmission interval. A single synchronization sequence contains multiple synchronization symbols, which are used for data message modulation and convenient timing information extraction. In order to improve the delay estimation accuracy, the synchronization symbol applies spread spectrum technology, such as direct sequence spread spectrum, linear frequency modulation, etc. The symbol waveform with a wider frequency band can obtain a sharper correlation peak after matched filtering. The estimation accuracy is also related to the symbol signal-to-noise ratio of the signal, so only the symbol phase is modulated in data modulation.

[0042] The time transfer process is as follows Figure 3 ,The messages in the figure correspond to the above synchronization sequence. The two-way synchronization process includes three types of messages: request (Req), response (Ack) and end (Fin). The response message carries forwarding time information, and the end message is a request message with propagation delay information. Two-way synchronization is used to compensate for propagation delay, and one-way synchronization can use the sending time information of the reference node in the request and end messages to achieve time taming.

[0043] The receiver's delay estimation usually obtains the reception time of the last codeword, and the time information modulated by the sender is the sending time of the first codeword, that is, the propagation delay includes the length of the synchronization sequence. Since the synchronization process does not adjust the logical clock or sampling clock, in order to prevent the influence of clock frequency deviation on propagation delay, and considering the simplicity of hardware implementation, this application does not use the method of resampling or adjusting the sending time of each codeword to correct the sequence to be sent, but corrects the sending time information and uses the step value of the timing accumulator to calculate the sending time of the last codeword.

[0044] To ensure rapid capture of burst synchronization sequences, a matched filter structure of segmented frequency domain product is used. Subsequently, sequence capture is performed based on the continuous matched filtering results, such as Figure 4 Sequence capture uses dynamic threshold, peak value check and synchronization symbol transmission period information for screening.

[0045] The dynamic threshold uses the statistical noise power of the received signal between synchronization symbols as follows, where z(n) is the squared modulus result of the matched filter, n Δand L are the location parameters of the statistical window, g th is the threshold adjustment coefficient, which can be adjusted according to the symbol signal-to-noise ratio requirement of the received signal. In hardware, it can be implemented using a comb filter and a shift register.

[0046]

[0047] The schematic diagram of the sequence peak check can be seen Figure 5 , only two comparison operations are required for each input sampling point. Based on the symbol period information, the capture state machine locates and narrows the search window for subsequent symbols after capturing the sampling point that meets both the threshold and peak conditions for the first time, and searches for and captures the maximum value in a smaller window.

[0048] In terms of time taming, the present application adopts a composite loop structure to realize the timing recovery of burst synchronization signals and the dynamic interval taming of digital time. Specifically, the composite loop is composed of a symbol tracking loop and a timing tracking loop, both of which are used to lock the time quantity. Referring to the phase-locked loop theory, a second-order type II loop is used for implementation. The corresponding loop structure is as follows: Figure 6 and Figure 7 As shown. Among them, the loop filter F L (z) and the time accumulator F T The transfer function of (z) is as follows, and the tracking error discriminator gain is K f .

[0049]

[0050] The transfer function of the simulated second-order type II loop is discretized by the bilinear transformation method and obtained as n T L The discrete closed-loop transfer function related to ζ is compared with the closed-loop transfer function obtained by the above unknown coefficients, keeping the closed-loop pole position unchanged, and we can get C 1 and C 2 The design formula is as follows, where K' = K f K u T L According to the optimal control theory, the damping coefficient ζ in the second-order system is usually taken as Digital natural frequency ω n T L It is related to loop performance parameters such as loop noise bandwidth, closed-loop cutoff frequency, and loop response speed.

[0051]

[0052] The symbol tracking loop is used to extract the precise delay of the synchronization sequence, and the loop tracking between each synchronization sequence is independent of each other. According to the above calculation formula, the relevant parameter design considerations are as follows:

[0053] (1) The loop is discretized according to the symbol reception period, corresponding to K u T L =1;

[0054] (2) The discriminator is implemented using an early-late gate synchronizer. Based on the early-late gate correlation results, the following normalized calculation formula is used, and the corresponding discriminator gain K f is a constant, which is related to the symbol shape and the early and late gate interval;

[0055]

[0056] (3) Loop taming frequency Higher, smaller ω is preferred n T L In order to obtain a narrower noise bandwidth without affecting the phase noise tracking. In engineering, the capture time of the loop can be considered as To ensure that the loop can complete the capture within N code elements, there is That is, here ω n T L Minimum possible value

[0057] The timing tracking loop compares the receiving time information obtained by tracking each synchronization sequence with the sending time information in the message, and tames the digital time to make the two time information the same. The design considerations of the relevant parameters are as follows:

[0058] (1) Every time the loop receives a valid synchronization sequence, it updates the loop state. The tracking timing accumulator in the figure provides real-time time and needs to be updated every cycle, that is, the step value of the self-increment latch. Assume that the loop taming interval T L =ΔnT clk , Δn can be obtained by counting the processing clock between two reception times. From the perspective of loop discipline, the gain K of the tracking timing accumulator is u T L =Δn;

[0059] (2) The discriminator only calculates the difference between the sending time and the receiving time, and the gain K f =1;

[0060] (3) The timing tracking loop is not limited by the capture time, and its purpose is to reduce the loop tracking error. The tracking error comes from the error in the estimation of the receiving time introduced by the channel noise on the one hand, and from the error caused by the inability to track the target tracking signal containing phase noise in time due to the limited loop cutoff frequency on the other hand. n T L The value requirement of is opposite. Considering that the taming interval is usually low in the time-sharing system, the phase noise tracking requirement is dominant, and a larger ω should be taken. n T Lvalue, and should also be combined with ω in the process of loop discretization n T L Limit of <<1.

[0061] Digital time training only trains the timing accumulator module, and the actual sampling clock and frequency conversion clock of the signal are still different. Therefore, the present application realizes the synchronous correction of the signal through the digital signal processing method of carrier deviation compensation and resampling.

[0062] Carrier deviation compensation must first obtain the carrier phase information of the reference node. After taming synchronization, digital time τ(t) = τ' clk (t) is the cycle count value of the source reference node processing clock, which can be regarded as the normalized phase of the reference processing clock. The count value does not have phase ambiguity. Therefore, the normalized phase information of any other homologous signal of the reference node can be obtained according to the frequency multiple relationship, as shown in the following formula, where τ' xx (t) represents the phase of the corresponding signal that is homologous to the reference clock, τ 0 It is the phase difference between the multiplied processing clock and the carrier signal. The circuit design should ensure that the phase is fixed.

[0063]

[0064] Knowing the expected carrier phase τ' c (t), combined with the actual local modulation or demodulation carrier phase τ c (t,τ 0 0, the phase deviation is sent to the DDS IP to generate a complex rotation factor. Figure 8 , the carrier deviation compensation can be realized. In addition to the RF carrier and intermediate frequency carrier in the analog domain, the frequency conversion signal that passes through before being converted to the baseband signal after sampling also needs to be compensated.

[0065] Resampling corrects the sampling position of the baseband signal, uses the high-order digital filter segmented fitting method to design a polynomial filter, and uses Farrow and transposed Farrow structures to achieve arbitrary resampling. The calculation formulas for Farrow and transposed Farrow are as follows. The former is suitable for upsampling, and the latter is suitable for downsampling.

[0066]

[0067] The resampled signal is regulated by the synchronous digital time, and its bandwidth may increase. Considering the higher processing bandwidth requirement after resampling, the receiving resampling is implemented using the Farrow structure, and the sending resampling is implemented using the transposed Farrow structure, such as Fig. 9 In the figure, 2μ m -1 as the polynomial basis in order to utilize c' l(n0) The symmetry reduces the multiplication unit. Since the sampling rate changes are similar, when two output or input sampling points appear, μ m and μ m+1 It can be approximated to 0 and 1, so it can actually be further simplified into a weighted operation unit.

[0068] After resampling, the signal bandwidth fluctuates. To ensure that the signal is not blocked or missing, the signal processing bandwidth of the subsequent logic is usually required to be doubled. In addition, the original resampling interface also requires the signal to be transmitted according to the requirements of digital time. The number of transmissions per cycle is uncertain, which is not convenient for integration. In this regard, this application performs a cross-time domain conversion on the original resampling interface, such as Fig.10 As shown, its main features are as follows:

[0069] (1) Slightly increase the processing clock to avoid doubling the logic resources;

[0070] (2) The time information of each sampling point is converted into a timestamp and periodically inserted into the data stream to reduce the transmission bandwidth requirement and save wiring resources and register resources required for beat generation;

[0071] (3) In the sending interface conversion module, a timing recovery and back pressure mechanism is introduced. That is, when the cached sampling point cannot match the sampling point required by the original resampling interface, the cached data is cleared and the data starting from a certain time after the sending logic request is sent. The cache is pre-cached and a back pressure signal is provided to achieve matching of the sending rate.

[0072] The time transfer scheme based on burst synchronization signals supports dynamic interval time taming, and the channel time-division multiplexing is more flexible, which is convenient for building a time-division multiplexing system and is beneficial to reducing system power consumption. At the same time, it also facilitates the scheduling of the synchronization process, and the taming interval can be dynamically modified according to the current work objectives; the signal synchronization correction method based on digital time taming can realize signal synchronization acquisition and transmission without relying on peripheral devices such as programmable crystal oscillators, which can reduce hardware development costs and adaptation costs. At the same time, there is no need to consider the control interface of the programmable crystal oscillator, which is convenient for the replacement and upgrade of the clock source.

[0073] This application mainly discusses end-to-end synchronization, so it is easy to achieve "one master and multiple slaves" type multi-node synchronization under shared channels such as radio. In non-shared channels, node scalability can be guaranteed by intermediate forwarding nodes with multiple sets of transmission interfaces. Fig.11 This is an implementation example of the present invention under wireless communication conditions. To simplify the description, only one synchronization node is shown in the figure, and other synchronization nodes are similar, and the synchronization nodes are distinguished according to the configured node addresses.

[0074] In the implementation of the present application, the hardware platform of the node includes an FPGA chip, a digital-to-analog converter (DAC), an analog-to-digital converter (ADC), a switch component, a local crystal oscillator, and a radio frequency antenna. The local crystal oscillator provides a clock for the chip on the board, does not require a programmable crystal oscillator, and can be replaced by an external clock source. The timing synchronization subsystem in the FPGA chip realizes the transmission and taming of local timing; the synchronous resampling subsystem shares a channel with the timing synchronization subsystem, and realizes synchronous transmission and reception of signals according to the synchronized local timing. Both subsystems need to use ADC and DAC to send and receive signals, which are time-division multiplexed through the arbitration control module. The module also controls the peripheral switch components to make the DAC and ADC time-division multiplex the antenna channel.

[0075] In the implementation of the present application, a linear frequency modulation (LFM) signal is used as a synchronization symbol, and the sampling rate of the baseband signal is recorded as f s , the bandwidth of the LFM signal is recorded as B, and f s / B and the number of symbol points are set to integer powers of 2, which makes it easy to calculate the signal phase of LFM with arbitrary fractional delay in hardware, so as to send it to DDS IP to generate waveform, realize signal transmission and waveform generation requirements in early and late gate synchronizers. At the same time, the main lobe shape of the LFM signal after matched filtering is close to the sampling function. In the absence of multipath interference, the discriminator gain of the aforementioned symbol tracking loop is 1.

[0076] In the implementation of the present application, the reference node has two working modes: one-way synchronization and two-way synchronization. The sending interval of the synchronization sequence can be configured by the software program. During the system startup phase or when the relative distance changes, each synchronization node can be scanned at a smaller taming interval, and the two-way synchronization process can be performed one by one to quickly update the propagation delay information of each synchronization node; during the stable working phase, a one-way broadcast signal can be sent at a larger interval, leaving more idle time slots for time-sharing multiplexing of other modules.

[0077] In the implementation manner of the present application, the taming action of the synchronization node is completely triggered by the synchronization sequence of the reference node, and responds accordingly to the unidirectional synchronization request and the bidirectional synchronization request directed to its own node.

[0078] In the implementation of the present application, the synchronous resampling system can automatically handle the jump of digital time. When the digital time jump causes inconsistency with the buffered data point time, the receiving interface conversion module will update the correct time at the next timestamp insertion moment, and the sending interface conversion module will clear the cache and request subsequent data in advance to align the timing.

[0079] The above shows and describes the basic principles, main features and advantages of the present invention. Those skilled in the art should understand that the above embodiments do not limit the present invention in any form, and any technical solution obtained by equivalent replacement or equivalent transformation falls within the protection scope of the present invention.

Claims

1. A digital time discipline and signal synchronization correction method, characterized in that: Include: The reference node sends a synchronization sequence, which modulates the reference node time at the time of sending; The synchronization node receives the synchronization sequence and obtains the synchronized digital time by adopting the digital time taming method; The synchronization node implements synchronization correction of the signal based on the obtained synchronized digital time.

2. The digital time discipline and signal synchronization correction method according to claim 1, characterized in that: The reference node sends the synchronization sequence using burst transmission.

3. The digital time discipline and signal synchronization correction method according to claim 2, characterized in that: The synchronization node uses a dynamic interval loop tracking method to complete the timing recovery of the burst synchronization signal and the dynamic interval taming of the digital time.

4. The digital time discipline and signal synchronization correction method according to claim 3, characterized in that: The synchronization node uses a composite loop structure to complete the timing recovery of the burst synchronization signal and the dynamic interval taming of the digital time.

5. The digital time discipline and signal synchronization correction method according to claim 4, characterized in that: The composite loop structure includes a symbol tracking loop and a timing tracking loop; The symbol tracking loop is used to extract the precise delay of the synchronization sequence. The timing tracking loop compares the receiving time information obtained based on the tracking of each synchronization sequence with the sending time information of the synchronization sequence, and tames the digital time to make the two time information the same.

6. The digital time discipline and signal synchronization correction method according to claim 1, characterized in that: The synchronization node performs carrier deviation compensation and resampling based on the obtained synchronized digital time to achieve signal synchronization correction.

7. The digital time discipline and signal synchronization correction method according to claim 1, characterized in that: The synchronization sequence includes multiple synchronization symbols and is used for data message modulation.

8. The digital time discipline and signal synchronization correction method according to claim 7, characterized in that: The synchronization code element adopts the spread spectrum technology.

9. The digital time discipline and signal synchronization correction method according to claim 8, characterized in that: The spread spectrum technology is one of direct sequence spread spectrum and linear frequency modulation.

10. The digital time discipline and signal synchronization correction method according to claim 9, characterized in that: During data modulation, only the phase of the synchronization symbol is modulated.

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