Chip packaging structure and chip packaging method
By using grooves to block solder overflow in the chip packaging structure, the problems of solder overflow and bridge in the flip chip packaging structure are solved, and the reliability of chip packaging is improved. It is suitable for packaging structures with small spacing between connected solder joints. .
Patent Information
- Application Number
- CN202411397440.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-09
- Publication Date
- 2025-01-10
AI Technical Summary
In the existing flip chip packaging structure, because the bump size of the flip chip functional surface is short, the solder is prone to overflow, resulting in a bridge between two adjacent bumps and may contact the line layer of the chip to cause a short circuit. This problem is more likely to occur in structures with smaller bump spacing.
A chip packaging structure is designed in which a plurality of metal bumps are formed on the functional surface of the chip and grooves are formed away from one side to form a plurality of first solder joints; a second solder joint that matches the groove shape is formed on the substrate. , and insert it into the groove of the first solder joint for reflow soldering, using the groove to block solder overflow and prevent bridges and short circuits.
Effectively prevent solder overflow and bridging between adjacent solder joints, improve the reliability of the chip packaging structure, especially in structures with small spacing between connected solder joints, enhance the reliability of the chip packaging.
Smart Images
Figure CN119297165A_ABST
Abstract
Description
Technical Field
[0001] The embodiments of the present disclosure belong to the field of semiconductor packaging technology, and specifically relate to a chip packaging structure and a chip packaging method. Background Art
[0002] In the existing flip chip packaging structure, due to the short size of the bumps on the functional surface of the flip chip, the solder is easy to overflow when the bumps are reflowed with the pads on the substrate, which on the one hand causes bridging between two adjacent bumps, and on the other hand, the overflowing solder climbs up along the bumps and contacts the circuit layer of the chip, causing a short circuit, thereby affecting the reliability of the flip chip packaging structure. Especially for the packaging structure with a small bump pitch, it is easier for two adjacent bumps to bridge.
[0003] In view of the above problems, it is necessary to propose a chip packaging structure and packaging method that are reasonably designed and effectively solve the above problems. Summary of the invention
[0004] The embodiments of the present disclosure aim to solve at least one of the technical problems existing in the prior art and provide a chip packaging structure and a packaging method.
[0005] An aspect of an embodiment of the present disclosure provides a chip packaging structure, including a chip and a substrate;
[0006] A plurality of first solder joints are arranged on a side of the chip facing the substrate, and a groove is arranged on an end of each of the first solder joints facing the substrate;
[0007] A plurality of solder pads are arranged on a side of the substrate facing the chip, each of the solder pads is provided with a second solder point corresponding to the first solder point, wherein the shape of the second solder point matches the shape of the groove;
[0008] When the chip is flip-chip mounted on the substrate, the second solder joint is located in the groove of the first solder joint corresponding to the second solder joint.
[0009] Optionally, the first welding point abuts against the substrate on a side facing the substrate.
[0010] Optionally, a diameter of the second welding point is smaller than a diameter of the groove.
[0011] Optionally, the second welding point protrudes in a direction away from the substrate.
[0012] Optionally, a metal connection plating layer is further included, and the metal connection plating layer is sandwiched between the groove and the second welding point.
[0013] Another aspect of the present disclosure provides a chip packaging method, the method comprising:
[0014] Providing a chip and a substrate, wherein a plurality of pads are arranged on the substrate;
[0015] Forming a plurality of metal bumps on the functional surface of the chip, and patterning a side of each metal bump away from the chip to form a groove, so as to form a plurality of first solder joints;
[0016] forming a plurality of second solder joints corresponding to the first solder joints on the solder pad of the substrate, wherein the shapes of the second solder joints match the shapes of the grooves;
[0017] The second solder joint is inserted into the groove of the first solder joint corresponding to the second solder joint, and reflow soldering is performed to flip the chip onto the substrate.
[0018] Optionally, forming a plurality of metal bumps on the functional surface of the chip includes:
[0019] forming a seed layer electrically connected to the pad of the chip on the functional surface of the chip;
[0020] forming a first photoresist layer on the seed layer, and exposing and developing the first photoresist layer to form a plurality of first openings on the first photoresist layer;
[0021] forming the metal bump in the first opening window by an electroplating process;
[0022] The remaining first photoresist layer and a portion of the seed layer are removed.
[0023] Optionally, patterning a side of each metal bump facing away from the chip to form a groove to form a plurality of first solder joints includes:
[0024] forming a second photoresist layer on the functional surface of the chip, wherein the second photoresist layer wraps the metal bump;
[0025] Exposing and developing the second photoresist layer to form a second window corresponding to the metal bump;
[0026] Etching the metal bump along the second opening through an etching process to form a groove at an end of the metal bump away from the chip to form the first solder joint;
[0027] The remaining second photoresist layer is removed.
[0028] Optionally, forming a plurality of second welding points corresponding to the first welding points on the welding pad of the substrate includes:
[0029] A soldering metal layer is coated on the soldering pad, and the soldering metal layer is reflowed to form a second soldering point matching the shape of the groove.
[0030] Optionally, after forming the first solder joint, the method further includes:
[0031] A metal connection plating layer is formed in the groove.
[0032] The chip packaging structure and chip packaging method of the embodiment of the present disclosure are characterized in that a plurality of first solder joints are arranged on the side of the chip facing the substrate, and a groove is arranged on one end of each first solder joint facing the substrate; a plurality of solder pads are arranged on the side of the substrate facing the chip, and a second solder joint corresponding to the first solder joint is arranged on each solder pad, wherein the shape of the second solder joint matches the shape of the groove; the second solder joint is arranged in the groove of the first solder joint corresponding to it, so that the chip is flip-chip arranged on the substrate. When the first solder joint of the chip and the second solder joint of the substrate are reflow-soldered, the second solder joint is arranged in the groove, and the groove can block the solder, prevent the solder from overflowing, thereby preventing bridging between adjacent solder joints, and preventing the solder from contacting the circuit layer of the chip to cause a short circuit, thereby improving the reliability of the chip packaging structure. In addition, the chip packaging structure of the embodiment of the present disclosure can be applied to a packaging structure with a small spacing between connected solder joints, which can well avoid bridging between two adjacent solder joints, and increase the reliability of the chip packaging structure with solder joints with a small spacing. BRIEF DESCRIPTION OF THE DRAWINGS
[0033] Figure 1 This is a schematic structural diagram of a chip packaging structure according to an embodiment of the present disclosure;
[0034] Figure 2 This is an exploded schematic diagram of a chip packaging structure according to another embodiment of the present disclosure;
[0035] Figure 3 A schematic diagram of a chip packaging method according to another embodiment of the present disclosure;
[0036] Figures 4 to 15 The figure is a process diagram of a chip packaging method according to another embodiment of the present disclosure. DETAILED DESCRIPTION
[0037] In order to enable those skilled in the art to better understand the technical solutions of the embodiments of the present disclosure, the embodiments of the present disclosure are further described in detail below in conjunction with the accompanying drawings and specific implementation methods.
[0038] like Figure 1 and Figure 2 As shown, one aspect of an embodiment of the present disclosure provides a chip package structure 100 including a chip 110 and a substrate 120 .
[0039] A plurality of first solder joints 130 are disposed on a side of the chip 110 facing the substrate 120 , and a groove 131 is disposed on an end of each first solder joint 130 facing the substrate 120 .
[0040] A plurality of solder pads 121 are disposed on a side of the substrate 120 facing the chip 110 , and a second solder point 140 corresponding to the first solder point 130 is disposed on each solder pad 121 , wherein the shape of the second solder point 140 matches the shape of the groove 131 .
[0041] When the chip 110 is electrically connected to the substrate 120 in a flip-chip manner, the second solder joint 140 is located in the groove 131 of the corresponding first solder joint 130 .
[0042] It should be noted that, in this embodiment, the first solder joint 130 is a copper bump and the second solder joint 140 is a tin bump.
[0043] The chip packaging structure of the embodiment of the present disclosure is configured such that the chip is flip-chip mounted on the substrate by placing the second solder joint in the groove of the first solder joint corresponding to the second solder joint. When the first solder joint of the chip and the second solder joint of the substrate are reflow-soldered, the second solder joint is placed in the groove, and the groove can block the solder to prevent the solder from overflowing, thereby preventing bridging between adjacent solder joints, and preventing the solder from contacting the circuit layer of the chip to cause a short circuit, thereby improving the reliability of the chip packaging structure. In addition, the chip packaging structure of the embodiment of the present disclosure can be applied to a packaging structure with a small spacing between connected solder joints, which can effectively avoid bridging between two adjacent solder joints, thereby increasing the reliability of the chip packaging structure with solder joints having a small spacing.
[0044] For example, Figure 1 As shown, the first solder joint 130 abuts against the substrate 120 on one side facing the substrate 120. That is, the height dimension of the second solder joint 140 matches the depth dimension of the groove 131. Preferably, the height dimension of the second solder joint 140 is the same as the depth dimension of the groove 131.
[0045] In this embodiment, the first solder joint 130 is in contact with the substrate 120 at one side thereof facing the substrate 120 , and the groove 131 can prevent the overflow of solder to the greatest extent during the reflow soldering process.
[0046] For example, Figure 1As shown, the diameter of the second solder joint 140 is smaller than the diameter of the groove 131, which can better realize soldering on the one hand, and can better prevent the overflow of solder on the other hand. In this embodiment, the groove 131 is located in the central area of the first solder joint 130, and the diameter of the groove 131 is about half of the diameter of the first solder joint 130. Specifically, the diameter of the first solder joint 130 ranges from 60μm to 80μm, the diameter of the groove 131 ranges from 30μm to 80μm, and the depth of the groove 131 ranges from 20μm to 30μm. Correspondingly, the diameter of the second solder joint 140 ranges from 20μm to 30μm, and the height of the second solder joint 140 ranges from 20μm to 30μm.
[0047] For example, in this embodiment, Figure 1 and Figure 2 As shown, the second solder joint 140 protrudes in a direction away from the substrate 120. Specifically, the longitudinal section of the second solder joint 140 is an arc shape protruding in a direction away from the substrate. Accordingly, the longitudinal section of the groove 131 of the first solder joint 130 can be rectangular, trapezoidal or arc-shaped, as long as the second solder joint 140 is wrapped in the groove 131.
[0048] For example, Figure 2 As shown, the chip packaging structure 100 further includes a metal connection plating layer 150, which is sandwiched between the groove 131 and the second solder joint 140. The metal connection plating layer 150 can make the first solder joint 130 and the second solder joint 140 more firmly welded. In this embodiment, the metal connection plating layer 150 can be a nickel plating layer, the first solder joint 130 is a copper bump, and the second solder joint 140 is a tin bump. The metal connection plating layer 150 using a nickel plating layer can increase the bonding between the copper bump and the tin bump, so that the first solder joint 130 and the second solder joint 140 can be better welded, thereby increasing the reliability of the chip packaging structure 100.
[0049] For example, Figure 1 and Figure 2 As shown, the chip packaging structure 100 further includes a seed layer 160, which is sandwiched between the chip 110 and the first solder joint 130, and plays a role in electrically connecting the first solder joint 130 to the chip 110. Specifically, the seed layer 160 is electrically connected to the first solder joint 130 and the pad on the functional surface of the chip 110.
[0050] like Figure 3 As shown, another aspect of the embodiment of the present disclosure provides a chip packaging method S100, the chip packaging method S100 comprising:
[0051] S110, providing a chip and a substrate, wherein a plurality of pads are provided on the substrate.
[0052] Specifically, Figures 4 to 14 As shown, a chip 110 and a substrate 120 are provided. Fig.12 As shown, a plurality of pads 121 are provided on the surface of the substrate 120. Figure 4 As shown, a functional surface of the chip 110 is provided with a plurality of pads 111 and a passivation layer 112 .
[0053] S120, forming a plurality of metal bumps on the functional surface of the chip, and patterning a side of each metal bump away from the chip to form a groove, so as to form a plurality of first solder joints.
[0054] Specifically, a plurality of metal bumps A are formed on the functional surface of the chip 110, and a side of each metal bump A facing away from the chip 110 is patterned to form a groove 131 to form a plurality of first solder joints 130. In this embodiment, the metal bump A is a copper bump.
[0055] The specific process of forming a plurality of metal bumps A on the functional surface of the chip 110 in step S120 is as follows:
[0056] Step S121 : forming a seed layer 160 electrically connected to the pad 111 of the chip 110 on the functional surface of the chip 110 .
[0057] Specifically, Figure 4 As shown, a sputtering process may be used to form a seed layer 160 on the passivation layer 112 of the functional surface of the chip 110 , wherein the seed layer 160 is electrically connected to the pad 111 of the chip 110 .
[0058] In this embodiment, the material of the seed layer 160 may be metal copper or metal titanium. The seed layer 160 may serve as a substrate during electroplating or deposition to promote uniform growth of subsequent metal layers.
[0059] Step S122 , forming a first photoresist layer 171 on the seed layer 160 , and exposing and developing the first photoresist layer 171 to form a plurality of first openings 172 on the first photoresist layer 171 .
[0060] Specifically, Figure 5 As shown, a photoresist is applied on the seed layer 160 to form a first photoresist layer 171. A first mask is placed above the first photoresist layer 171, wherein a preset pattern of metal bumps A is provided on the first mask. Figure 5 As shown, the first photoresist layer 171 is exposed and developed using the first mask as a mask to form a plurality of first openings 172 on the first photoresist layer 171. In other words, the preset pattern on the first mask is transferred to the first photoresist layer 171.
[0061] It should be noted that the first photoresist layer 171 can be made of either positive photoresist or negative photoresist, which can be selected according to actual needs. This embodiment does not specifically limit the material of the first photoresist layer 171.
[0062] Step S123 , forming a metal bump A in the first window 172 by electroplating process.
[0063] Specifically, Figure 6 As shown, the metal bump A is formed in the first window 172 by electroplating through the electroplating process. That is, in this embodiment, copper liquid is electroplated in the first window 172 to form the copper bump.
[0064] Step S124 , removing the remaining first photoresist layer 171 and part of the seed layer 160 .
[0065] Specifically, Figure 7 As shown, the remaining first photoresist layer 171 is removed by etching process. Also, part of the seed layer 160 is removed by etching process, so that the remaining seed layer 160 is only connected to the metal bump A, to prevent the chip 110 from short circuiting due to the seed layer 160 existing in other positions.
[0066] The specific steps of patterning the side of each metal bump A away from the chip 110 to form a groove 131 in step S120 to form a plurality of first solder joints 130 may include:
[0067] Step S125 , forming a second photoresist layer 173 on the functional surface of the chip 110 , wherein the second photoresist layer 173 wraps the metal bump A.
[0068] Specifically, Figure 8 As shown, photoresist is coated on the passivation layer 112 of the chip 110 and on the seed layer 160 to form a second photoresist layer 173 , wherein the formed second photoresist layer 173 wraps the metal bump A.
[0069] It should be noted that the second photoresist layer 173 can be made of either positive photoresist or negative photoresist, which can be selected according to actual needs. This embodiment does not specifically limit the material of the second photoresist layer 173.
[0070] Step S126 , exposing and developing the second photoresist layer 173 to form a second window at a location corresponding to the metal bump.
[0071] Specifically, Fig. 9As shown, a second mask is placed on the second photoresist layer 173, wherein the second mask is provided with a preset pattern of grooves 131. The second photoresist layer 173 is exposed and developed using the second mask as a mask to transfer the preset pattern of grooves 131 on the second mask to the second photoresist layer 173, and a second opening 174 is formed on the second photoresist layer 173.
[0072] Step S127 , etching the metal bump A along the second window 174 by an etching process to form a groove 131 at the end of the metal bump A away from the chip 110 , so as to form a first solder joint 130 .
[0073] Specifically, Fig.10 As shown, the metal bump A is etched along the second opening 174 by an etching process, and the preset pattern on the second photoresist layer 173 is transferred to the metal bump A, so as to form a groove 131 at the end of the metal bump A away from the chip 110, so as to form a first solder joint 130. That is, in this embodiment, the first solder joint 130 is a copper bump with a groove.
[0074] It should be noted that, in this embodiment, the groove 131 is located in the central area of the first solder joint 130, and the diameter of the groove 131 is about half of the diameter of the first solder joint 130. Specifically, the diameter of the first solder joint 130 ranges from 60 μm to 80 μm, the diameter of the groove 131 ranges from 30 μm to 80 μm, and the depth of the groove 131 ranges from 20 μm to 30 μm.
[0075] Step S128, removing the remaining second photoresist layer.
[0076] Specifically, Fig.10 As shown, the remaining second photoresist layer 173 is removed by an etching process.
[0077] After forming the first solder joint 130, the chip packaging method S100 further includes:
[0078] like Fig.11 As shown, a metal connection plating layer 150 is formed in the groove 131. Specifically, the metal connection plating layer 150 can be formed on the inner side wall of the groove 131 by a sputtering process. It should be noted that, in this embodiment, the metal connection plating layer 150 can be a nickel plating layer.
[0079] S130 , forming a plurality of second solder joints 140 corresponding to the first solder joints 130 on the solder pads 121 of the substrate 110 , wherein the shapes of the second solder joints 140 match the shapes of the grooves 131 .
[0080] Specifically, Fig.13As shown, a soldering metal layer 180 is coated on the soldering pad 121, and the soldering metal layer 180 is reflowed. Fig.14 As shown, a second welding point 140 matching the shape of the groove 131 is formed.
[0081] It should be noted that, in this embodiment, the material of the second solder joint 140 can be metallic tin, that is, the second solder joint 140 is a tin bump. The steps of forming the tin bump can be: applying tin paste on the solder pad 121 of the substrate 120, and reflowing the tin paste to form a tin bump protruding in a direction away from the substrate 120.
[0082] It should be noted that, in this embodiment, Fig.14 As shown, the longitudinal section of the second solder joint 140 is an arc convex toward the direction away from the substrate. Accordingly, the longitudinal section of the groove 131 of the first solder joint 130 can be rectangular, trapezoidal or arc shaped, as long as the second solder joint 140 is wrapped in the groove 131.
[0083] It should be further explained that, corresponding to the size of the groove 131 , the diameter of the second solder joint 140 may be in the range of 20 μm to 30 μm, and the height of the second solder joint 140 may be in the range of 20 μm to 30 μm.
[0084] S140 , inserting the second solder joint 140 into the groove 131 of the corresponding first solder joint 130 , and performing reflow soldering to flip-mount the chip 110 on the substrate 120 .
[0085] Specifically, Fig.15 As shown, the substrate 120 is placed on the carrier, wherein the side where the second solder joint 140 is formed faces upward, and the functional surface of the chip 110 faces downward so that each first solder joint 130 corresponds to the second solder joint 140, and the first solder joint 130 needs to be dipped in flux first, and then the second solder joint 140 is inserted into the groove 131 of the first solder joint 130, and then the first solder joint 130 and the second solder joint 140 are reflowed to flip the chip 110 on the substrate 120, complete the chip packaging, and form the chip packaging structure 100.
[0086] It should be noted that the nickel plating layer used for the metal connection plating layer 150 can increase the bonding between the copper bump and the tin bump, so that the first solder joint 130 and the second solder joint 140 can be better welded, thereby increasing the reliability of the chip packaging structure 100 .
[0087] The chip packaging method of the embodiment of the present disclosure forms a plurality of metal bumps on the functional surface of the chip, and patterns the side of each metal bump away from the chip to form a groove to form a plurality of first solder joints; forms a plurality of second solder joints corresponding to the first solder joints on the solder pad of the substrate, wherein the shape of the second solder joints matches the shape of the grooves; inserts the second solder joints into the grooves of the first solder joints corresponding thereto, and performs reflow soldering to flip the chip onto the substrate. When the second solder joints are inserted into the grooves of the first solder joints corresponding thereto for reflow soldering, the grooves can block the solder, prevent the solder from overflowing, thereby preventing bridging between adjacent solder joints, and preventing the solder from contacting the circuit layer of the chip to cause a short circuit, thereby improving the reliability of the chip packaging structure. In addition, the chip packaging method of the embodiment of the present disclosure can be applied to chip packaging with a small spacing between adjacent solder joints, which can well avoid bridging between two adjacent solder joints, thereby increasing the reliability of the chip packaging structure with solder joints having a small spacing.
[0088] It is to be understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of the embodiments of the present disclosure, but the embodiments of the present disclosure are not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and essence of the embodiments of the present disclosure, and these modifications and improvements are also considered to be within the protection scope of the embodiments of the present disclosure.
Claims
1. A chip packaging structure, characterized in that: Including chip and substrate; A plurality of first solder joints are arranged on a side of the chip facing the substrate, and a groove is arranged on an end of each of the first solder joints facing the substrate; A plurality of solder pads are arranged on a side of the substrate facing the chip, each of the solder pads is provided with a second solder point corresponding to the first solder point, wherein the shape of the second solder point matches the shape of the groove; When the chip is flip-chip mounted on the substrate, the second solder joint is located in the groove of the first solder joint corresponding to the second solder joint.
2. The chip packaging structure according to claim 1, characterized in that: The first welding point abuts against the substrate at a side facing the substrate.
3. The chip packaging structure according to claim 2, characterized in that: The diameter of the second welding point is smaller than the diameter of the groove.
4. The chip packaging structure according to any one of claims 1 to 3, characterized in that: The second welding point protrudes in a direction away from the substrate.
5. The chip packaging structure according to any one of claims 1 to 3, characterized in that: It also includes a metal connection plating layer, which is sandwiched between the groove and the second welding point.
6. A chip packaging method, characterized in that: The method comprises: Providing a chip and a substrate, wherein a plurality of pads are arranged on the substrate; Forming a plurality of metal bumps on the functional surface of the chip, and patterning a side of each metal bump away from the chip to form a groove, so as to form a plurality of first solder joints; forming a plurality of second solder joints corresponding to the first solder joints on the solder pad of the substrate, wherein the shapes of the second solder joints match the shapes of the grooves; The second solder joint is inserted into the groove of the first solder joint corresponding to the second solder joint, and reflow soldering is performed to flip the chip onto the substrate.
7. The chip packaging method according to claim 6, characterized in that: The forming of a plurality of metal bumps on the functional surface of the chip comprises: forming a seed layer electrically connected to the pad of the chip on the functional surface of the chip; forming a first photoresist layer on the seed layer, and exposing and developing the first photoresist layer to form a plurality of first openings on the first photoresist layer; forming the metal bump in the first opening window by an electroplating process; The remaining first photoresist layer and a portion of the seed layer are removed.
8. The chip packaging method according to claim 7, characterized in that: The step of patterning a side of each metal bump away from the chip to form a groove to form a plurality of first solder joints comprises: forming a second photoresist layer on the functional surface of the chip, wherein the second photoresist layer wraps the metal bump; Exposing and developing the second photoresist layer to form a second window corresponding to the metal bump; Etching the metal bump along the second opening through an etching process to form a groove at an end of the metal bump away from the chip to form the first solder joint; The remaining second photoresist layer is removed.
9. The chip packaging method according to any one of claims 6 to 8, characterized in that: The step of forming a plurality of second solder joints corresponding to the first solder joints on the solder pad of the substrate comprises: A soldering metal layer is coated on the soldering pad, and the soldering metal layer is reflowed to form a second soldering point matching the shape of the groove.
10. The chip packaging method according to any one of claims 6 to 8, characterized in that: After forming the first solder joint, the method further includes: A metal connection plating layer is formed in the groove.