Semiconductor structure and preparation method thereof

Abstract

The embodiment of the invention relates to the field of semiconductors, and provides a semiconductor structure and a preparation method thereof, and the preparation method comprises the steps: providing a substrate which is internally provided with a channel region and doped regions located at the two sides of the channel region, the substrate is provided with a gate structure right opposite to the channel region, a side wall is formed on the side wall of the gate structure, and the doped regions are located at the two sides of the channel region; the side wall is adjacent to the doped region, and the substrate is also provided with an isolation layer covering the side wall and the doped region; patterning the isolation layer to form a groove exposing the doped region; carrying out metallization processing on the doped region exposed out of the groove so as to form a metal silicide layer; forming a barrier layer, wherein the barrier layer at least covers the inner wall of the groove; and forming a conductive column, wherein the conductive column fills the groove and is in electric contact with the metal silicide layer.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the semiconductor field, and in particular to a semiconductor structure and a method for preparing the same. Background Art

[0002] Memory is a memory component used to store programs and various data information. The random access memory (RAM) used in general computer systems can be divided into two types: dynamic random access memory (DRAM) and static random access memory (SRAM). Dynamic random access memory is a commonly used semiconductor memory device in computers, consisting of many repeated storage units.

[0003] A memory cell generally includes a memory element and a transistor. The drain of the transistor is connected to a bit line structure, and the source is connected to the memory element. The word line structure of the memory cell can control the opening or closing of the channel region of the transistor, thereby reading the data information stored in the memory element through the bit line structure, or writing the data information into the memory element for storage through the bit line structure.

[0004] Due to the current requirements for storage density and integration density, the characteristic dimensions of each device in the semiconductor structure are further reduced. For example, the contact area between the semiconductor device and the metal wiring is reduced, resulting in an increase in contact resistance. The contact resistance plays a vital role in the reliability and performance of semiconductor memory devices. Summary of the invention

[0005] The embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same, which are at least beneficial to improving the reliability and performance of the semiconductor structure.

[0006] According to some embodiments of the present disclosure, on the one hand, an embodiment of the present disclosure provides a method for preparing a semiconductor structure, comprising: providing a substrate, wherein the substrate has a channel region and doped regions located on both sides of the channel region, the substrate has a gate structure directly opposite to the channel region, and side walls are formed on the side walls of the gate structure, the side walls are adjacent to the doped regions, and the substrate also has an isolation layer covering the side walls and the doped regions; patterning the isolation layer to form a groove exposing the doped region; metallizing the doped region exposed by the groove to form a metal silicide layer; forming a barrier layer, the barrier layer at least covering the inner wall of the groove; forming a conductive column, the conductive column filling the groove and being in electrical contact with the metal silicide layer.

[0007] In some embodiments, before the metallization process is performed, a portion of the inner wall of the groove exposes at least a portion of the side surface of the spacer away from the gate structure.

[0008] In some embodiments, the sidewall includes: a first sidewall and a second sidewall, the first sidewall covers the sidewall of the gate structure, the second sidewall covers the sidewall of the first sidewall, and the second sidewall is located between the isolation layer and the first sidewall; in the step of patterning the isolation layer, at least part of the width of the second sidewall is also removed.

[0009] In some embodiments, the material of the second sidewall spacer is the same as that of the isolation layer; and in the step of patterning the isolation layer, the second sidewall spacer is removed simultaneously.

[0010] In some embodiments, the material of the second sidewall spacer is different from the material of the isolation layer; after patterning the isolation layer, the method further includes: removing the second sidewall spacer.

[0011] In some embodiments, the process steps for forming the groove include: forming a first mask layer, the first mask layer is located on the surface of the isolation layer, and the first mask layer has a first through hole; using the first mask layer as a mask, etching the isolation layer along the first through hole to form a groove.

[0012] In some embodiments, the first mask layer covers the entire top surface of the sidewall; after patterning the isolation layer, the method further includes: performing side etching along the inner wall of the groove until a portion of the width of the sidewall is removed.

[0013] In some embodiments, the first through hole also exposes a portion of the top surface of the sidewall; using the first mask layer as a mask, while etching the isolation layer along the first through hole, a portion of the width of the sidewall directly below the first through hole is also etched.

[0014] In some embodiments, an orthographic projection of the groove on the substrate is located within the metal silicide layer.

[0015] According to some embodiments of the present disclosure, on the other hand, the embodiments of the present disclosure further provide a semiconductor structure, including: a substrate, wherein the substrate has a channel region and doped regions located on both sides of the channel region, the surface of the substrate has a gate structure directly opposite to the channel region, and side walls are formed on the side walls of the gate structure, the side walls are adjacent to the doped regions, and the substrate also has an isolation layer covering the side walls and the doped regions; a metal silicide layer, wherein the metal silicide layer is located in the doped regions; a conductive column located in the isolation layer, wherein the conductive column is electrically in contact with the metal silicide layer; a blocking layer, wherein the blocking layer is located between the isolation layer and the conductive column, and the blocking layer is also located between the side walls and the conductive column, and the dielectric constant of the material of the blocking layer is greater than the dielectric constant of the material of the side walls.

[0016] The technical solution provided by the embodiments of the present disclosure has at least the following advantages:

[0017] In the method for preparing the semiconductor structure provided by the embodiment of the present disclosure, a gate structure facing the channel region is provided on the substrate, a sidewall is formed on the sidewall of the gate structure, and the sidewall is adjacent to the doping region. By setting the sidewall adjacent to the doping region, it is ensured that the area directly above the channel region is the gate structure, thereby ensuring that the length of the channel region is large, thereby improving the integration. The isolation layer is patterned and a groove is formed, a metal silicide layer is formed in the groove and in the doping region, and a barrier layer is formed, the barrier layer covers the inner wall of the groove, thereby increasing the range of the groove as much as possible in a limited area, and since the barrier layer is provided to isolate the electrical insulation between the subsequently formed conductive column and the gate structure, the distance between the groove and the gate structure can be set to be small, that is, the cross-sectional area of ​​the groove is large, so that the exposed doping region is large, and the area of ​​the formed metal silicide layer is large, which can ensure that the area where the conductive column and the doping region are in contact is the metal silicide layer, and the contact area between the conductive column and the doping region is large, so the contact resistance is small, and the resistance value of the conductive column itself is small, thereby effectively improving the reliability and electrical performance of the semiconductor structure.

[0018] In addition, before the metallization treatment is performed, part of the inner wall of the groove exposes at least part of the side of the side wall away from the gate structure, so that the line width or size of the groove can be expanded as much as possible, so that when the doped area located at the bottom of the groove is metallized and a metal silicide layer is formed, a larger window can be used to form the metal silicide layer, thereby ensuring that the area where the conductive column and the doped area are in contact is all the metal silicide layer, forming a good ohmic contact, thereby reducing the contact resistance. When the size and line width of the groove are as large as possible, the cross-sectional area of ​​the conductive column is large, so that the resistance value of the conductive column itself is correspondingly reduced, which is beneficial to improving the electrical performance of the conductive column. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings, and these exemplified descriptions do not constitute a limitation on the embodiments. Unless otherwise specified, the pictures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0020] Figure 1 A flow chart of a method for preparing a semiconductor structure provided in one embodiment of the present disclosure;

[0021] Figures 2 to 13 A schematic diagram of the structure of a semiconductor structure corresponding to each step in a method for preparing a semiconductor structure provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0022] As can be seen from the background art, the reliability and performance of current semiconductor structures need to be improved.

[0023] The embodiment of the present disclosure provides a semiconductor structure and a preparation method thereof, comprising: a gate structure facing a channel region on a substrate, a sidewall formed on a sidewall of the gate structure, the sidewall adjacent to a doping region, and by setting the sidewall adjacent to the doping region, it is ensured that the region directly above the channel region is the gate structure, thereby ensuring that the length of the channel region is large, thereby improving the integration. Graphically forming an isolation layer and forming a groove, forming a metal silicide layer in the groove and in the doping region, and forming a barrier layer, the barrier layer covering the inner wall of the groove, thereby increasing the range of the groove as much as possible in a limited area, because the barrier layer is set to isolate the electrical insulation between the subsequently formed conductive column and the gate structure, the distance between the groove and the gate structure can be set to be small, that is, the cross-sectional area of ​​the groove is large, so that the exposed doping region is large, and the area of ​​the formed metal silicide layer is large, which can ensure that the region where the conductive column and the doping region are in contact is the metal silicide layer, and the contact area between the conductive column and the doping region is large, so that the contact resistance is small, and the resistance value of the conductive column itself is small, thereby effectively improving the reliability and electrical performance of the semiconductor structure.

[0024] The following will describe the various embodiments of the present disclosure in detail with reference to the accompanying drawings. However, it will be appreciated by those skilled in the art that in the various embodiments of the present disclosure, many technical details are provided in order to enable the reader to better understand the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can be implemented.

[0025] Figure 1A flow chart of a method for preparing a semiconductor structure provided in one embodiment of the present disclosure; Figures 2 to 13 A schematic diagram of the structure of a semiconductor structure corresponding to each step in a method for preparing a semiconductor structure provided in an embodiment of the present disclosure.

[0026] in, Figure 3 for Figure 2 Schematic diagram of the cross-sectional structure along section A1-A2. Figure 7 for Figure 6 Schematic diagram of the cross-sectional structure along section A1-A2.

[0027] According to some embodiments of the present disclosure, on the one hand, a method for preparing a semiconductor structure is provided by controlling the size of a groove, etching a side wall of partial thickness, and forming a barrier layer with a higher dielectric constant than the side wall on the inner wall surface of the groove to reduce the problem of leakage current between the conductive column and the gate structure, thereby improving the yield of the semiconductor structure.

[0028] refer to Figures 1 to 3 or Figure 6 to Figure 7 The preparation method includes: providing a substrate 100, wherein the substrate 100 has a channel region 102 and doped regions 103 located on both sides of the channel region 102, the substrate 100 has a gate structure 105 directly opposite to the channel region 102, and a sidewall 106 is formed on the sidewall of the gate structure 105, and the sidewall is adjacent to the doped region 103, and the substrate 100 also has an isolation layer 107 covering the sidewall 106 and the doped region 103.

[0029] In some embodiments, the material of the substrate 100 may be a semiconductor material, and the semiconductor material includes silicon, silicon germanium, or germanium. The substrate 100 contains a P-type doping element or an N-type doping element. The N-type doping element may be a Group V element such as phosphorus (P), bismuth (Bi), antimony (Sb), or arsenic (As), and the P-type doping element may be a Group III element such as boron (B), aluminum (Al), gallium (Ga), or indium (In).

[0030] In some embodiments, the substrate 100 has a plurality of active regions and an isolation structure 101 that separates each active region. The isolation structure 101 is used to separate each two active regions, thereby subsequently forming transistor structures.

[0031] In some embodiments, the material of the active region may include a semiconductor material, and the semiconductor material includes silicon, silicon germanium or germanium. In some embodiments, the material of the active region includes an amorphous material, and the amorphous material has a gap inside, has a higher carrier mobility, can reduce the thickness of the active region, and reduce the line width of the semiconductor structure within a limited unit area, and further improve the storage density of the semiconductor structure. The amorphous material may include at least one of IGZO (Indium Gallium Zinc Oxide), IWO (Tungsten-doped Indium Oxide, Indium Tungsten Oxide) or ITO (Indium Tin Oxide). For example, when the material of the active region is IGZO, the carrier mobility of IGZO is 20 to 50 times that of polycrystalline silicon, which is beneficial to improve the carrier mobility in the active region, thereby helping to reduce the leakage current when the semiconductor structure is working, so as to reduce the power consumption of the semiconductor structure and improve the working efficiency of the semiconductor structure.

[0032] In some embodiments, the active region and the base may be prepared from the same original substrate, that is, the material of the active region is the same as that of the base. In some embodiments, the material of the active region is different from that of the base.

[0033] In some embodiments, the active region includes a channel region 102 and doped regions 103 located on both sides of the channel region 102. The doped regions 103 serve as a source or drain of the transistor structure. One of the doped regions 103 is electrically connected to the bit line structure, and the other doped region 103 is electrically connected to the capacitor structure.

[0034] In some embodiments, the doping region 103 has a first type of doping element, and the channel region 102 has a second type of doping element. The first type of doping element is one of an N-type doping element or a P-type doping element, and the second type of doping element is the other of an N-type doping element or a P-type doping element. Then, a PN junction is formed at the interface where each doping region 103 contacts the channel region, and the semiconductor structure is a junction transistor. The PN junction is a device in which the majority carriers are used as a conductor, so the problem of minority carrier storage and diffusion can be avoided, and the majority carrier velocity is high, which is beneficial to improving the conductivity of the semiconductor channel. In some embodiments, the doping region 103 and the channel region 102 have the first type of doping element or the second type of doping element, and the semiconductor structure is a junctionless transistor.

[0035] In some embodiments, the isolation structure 101 may be a shallow trench isolation structure (STI) or an isolation structure formed of an isolation material. The isolation structure 101 may be a single-layer film layer or a multi-layer film layer.

[0036] In some embodiments, the material of the isolation structure 101 includes silicon oxide, silicon nitride, silicon carbonitride, or other materials with a high dielectric constant.

[0037] In some embodiments, the gate structure 105 is used as a word line structure later, and the gate structure 105 can be a metal gate structure or a polysilicon gate structure. The gate structure 105 includes a stacked barrier layer, a conductive layer and a gate cap. The material of the barrier layer includes a metal nitride, and the metal nitride can be titanium nitride or tantalum nitride. The material of the conductive layer includes at least one of doped polysilicon, tungsten, tantalum, titanium, tantalum nitride or titanium nitride. The material of the gate cap includes silicon nitride.

[0038] In some embodiments, a gate dielectric layer 104 is provided between the gate structure 105 and the channel region 102. The gate dielectric layer 104 is used to isolate the gate structure 105 from the channel region 102. The material of the gate dielectric layer 104 includes silicon oxide or a high dielectric constant material. The high dielectric constant material includes hafnium oxide or hafnium oxynitride.

[0039] In some embodiments, the spacer 106 is used to protect the gate structure 105. The material of the spacer 106 includes silicon nitride.

[0040] In some embodiments, the material of the isolation layer 107 includes silicon oxide.

[0041] In some embodiments, under the same etching process, the etching rate of the sidewall 106 is different from the etching rate of the isolation layer 107, so that in the process of patterning the isolation layer 107 and forming the groove, there is no etching damage to the gate structure 105, thereby ensuring the performance of the gate structure 105 itself. In addition, in the process of patterning the isolation layer 107, the sidewall is not etched, and the sidewall can be used as an insulating material between the conductive pillar formed subsequently and the gate structure 105, thereby preventing the conductive pillar and the gate structure 105 from short-circuiting, effectively ensuring the yield of the semiconductor structure.

[0042] Continue to refer Figures 1 to 3 or Figure 6 to Figure 7 The preparation method includes: forming a first mask layer 108 , the first mask layer 108 is located on the surface of the isolation layer 107 , and the first mask layer 108 has a first through hole 109 .

[0043] In some embodiments, the material of the first mask layer 108 includes photoresist. Under the same etching process, the etching rate of the first mask layer 108 is different from the etching rate of the isolation layer 107, thereby ensuring that the morphology of the first mask layer 108 does not change during the entire etching process, so that the prepared groove has higher precision.

[0044] refer to Figure 3 , the first mask layer 108 covers the entire top surface of the spacer 106 .

[0045] refer to Figure 4 The preparation method includes: patterning the isolation layer 107 to form a groove 110 exposing the doped region 103.

[0046] Among them, part of the inner wall of the groove 110 exposes at least part of the side of the side wall 106 away from the gate structure 105, so that the line width or size of the groove 110 can be expanded as much as possible, so that when the doped area 103 located at the bottom of the groove 110 is metallized and a metal silicide layer is formed, a larger window can be used to form a metal silicide layer, thereby ensuring that the area where the subsequently formed conductive column contacts the doped area 103 is all a metal silicide layer, forming a good ohmic contact, thereby reducing the contact resistance. When the size and line width of the groove 110 are as large as possible, the cross-sectional area of ​​the conductive column is large, so that the resistance value of the conductive column itself is correspondingly reduced, which is beneficial to improving the electrical performance of the conductive column.

[0047] In some embodiments, the first mask layer 108 is used as a mask to etch the isolation layer along the first through hole 109 to form a groove 110. The groove 110 is formed by a dry etching process or a wet etching process.

[0048] refer to Figure 5 , after patterning the isolation layer 107, the method further includes: performing lateral etching on the inner wall of the groove 110 until a portion of the width of the sidewall 106 is removed. In this way, the embodiment of the present disclosure optimizes the size of the groove 110, that is, etching a portion of the width of the sidewall 106 to increase the size of the groove 110, thereby increasing the window of the metallization process, so that more areas form a metal silicide layer, thereby reducing the contact resistance between the conductive pillar and the doped region 103 and increasing the cross-sectional area of ​​the conductive pillar itself, thereby improving the electrical performance of the conductive pillar.

[0049] Continue to refer Figure 5 , remove the first mask layer.

[0050] The above embodiment provides a method for preparing a semiconductor structure in which the first through hole does not expose the sidewall, so as to accurately control the thickness of the removed sidewall, thereby avoiding etching damage to the gate structure. The disclosed embodiment also provides a method for preparing a semiconductor structure in which the first through hole exposes a portion of the top surface of the sidewall, which reduces the process steps, thereby reducing the preparation cost and reducing the process complexity.

[0051] refer to Figure 6 as well as Figure 7 , the first through hole 109 also exposes a portion of the top surface of the sidewall 106 .

[0052] refer to Figure 5, using the first mask layer as a mask, while etching the isolation layer 107 along the first through hole, also etching a portion of the width of the sidewall 106 located directly below the first through hole; and removing the first mask layer.

[0053] refer to Figure 8 The preparation method includes: performing metallization treatment on the doped region 103 exposed by the groove 110 to form a metal silicide layer 113 .

[0054] In some embodiments, in order to reduce the series resistance and contact resistance of the active region, a metal silicide layer 113 is formed on the active region.

[0055] In some embodiments, a metal silicide layer is formed by self-aligned silicide (Self Aligned Silicide-Salicide), that is, the metallization process includes self-aligned metal silicide technology. Self-aligned metal silicide technology uses metal (Ti, Co, NiPt, etc.) to react with silicon in the active area in direct contact to form metal silicide. The metal will not react with the dielectric materials such as SiO2, Si3N4 and SiON in contact, so the metal silicide can be well aligned with the active area without deviation.

[0056] In some embodiments, the basic process steps of the self-aligned metal silicide technology are to first use physical vapor deposition (PVD) to deposit a layer of metal (Ti, Co, NiPt, etc.) on the doped region 103 and the inner wall surface of the groove 110. Then, two rapid thermal annealing processes (RTA) and one selective wet etching process are performed to finally form a metal silicide layer 113 on the surface of the doped region 103. The metal silicide layer 113 is used to reduce the sheet resistance and contact resistance of the doped region 103. In terms of design, a smaller series resistance can be obtained, the RC delay can be reduced, and the speed of the circuit can be increased.

[0057] In some embodiments, the metal silicide layer 113 includes thin films such as TiSi 2 , CoSi 2 , and NiPtSi.

[0058] In some embodiments, the metallization process includes an ion implantation technique followed by a thermal treatment to form a metal silicide layer.

[0059] It is understandable that, since the metallization process is a reaction between the metal and the material of the doped region 103 itself, not only the formed metal silicide layer 113 is located in the groove 110, but also part of the doped region is converted into a metal silicide layer.

[0060] In some embodiments, the orthographic projection of the groove 110 on the substrate 100 is located in the metal silicide layer 113. The area of ​​the metal silicide layer 113 is greater than or equal to the groove 110, thereby increasing the area of ​​the metal silicide layer 113 as much as possible, reducing the contact resistance between the doped region 103 and the subsequently formed conductive pillar, reducing the RC delay, and improving the speed of the circuit.

[0061] refer to Fig. 9 The preparation method includes: forming a barrier layer 114 , the barrier layer 114 at least covers the inner wall of the groove 110 , and the relative dielectric constant of the material of the barrier layer 114 is greater than the relative dielectric constant of the material of the sidewall 106 .

[0062] In some embodiments, the barrier layer 114 also covers the outer surface of the sidewall 106, and the material of the barrier layer 114 can be selected as a suitable insulating material according to the coupling capacitance and breakdown voltage between the gate and the conductive column expected in actual conditions. For example, when the deposition process is ideal, in order to reduce the possibility of breakdown, the material of the barrier layer 114 with a relative dielectric constant greater than the relative dielectric constant of the sidewall material can be selected, and the barrier layer 114 with a higher dielectric constant is located between the conductive column and the gate structure. The barrier layer 114 with a higher relative dielectric constant can reduce the possibility of direct breakdown between the conductive column and the gate structure, thereby improving the reliability of the semiconductor structure. Under the same expected coupling capacitance and breakdown voltage, using a higher dielectric constant material as the barrier layer material can reduce the thickness of the barrier layer 114, thereby making the volume of the conductive column 115 larger, and further increasing the contact area with the metal silicide layer 113; in some embodiments, the process steps of forming the barrier layer 114 include: forming a dielectric film on the inner wall surface and the top surface of the groove 110; removing the dielectric film at the bottom and top surface of the groove 110, and the remaining dielectric film is used as the barrier layer 114.

[0063] In some embodiments, the dielectric film is formed by a chemical vapor deposition process or a physical vapor deposition process.

[0064] refer to Fig.10 The preparation method includes: forming a conductive column 115 , the conductive column 115 fills the groove 110 and is in electrical contact with the metal silicide layer 113 .

[0065] In some embodiments, the conductive pillar 115 may serve as a bit line structure or a capacitor plug.

[0066] In some embodiments, the material of the conductive pillar 115 includes at least one of tungsten, tantalum, titanium, tantalum nitride, or titanium nitride.

[0067] In some embodiments, the thickness of the conductive pillar 115 and the thickness of the blocking layer 114 are used to ensure that the thickness of the blocking layer 114 is moderate, which can not only ensure that the breakdown voltage between the gate structure 105 and the conductive pillar 115 is large, but also ensure that the area of ​​the conductive pillar 115 is large, so that the electrical performance of the conductive pillar 115 is better.

[0068] The above embodiments are discussed with the spacer being a single film layer. The present disclosure also provides a method for preparing a semiconductor structure with a spacer including a first spacer and a second spacer. Figures 11 to 13 Provide explanation.

[0069] refer to Fig.11 The sidewall spacer 106 includes: a first sidewall spacer 111 and a second sidewall spacer 112 , the first sidewall spacer 111 covers the sidewall of the gate structure 105 , the second sidewall spacer 112 covers the sidewall of the first sidewall spacer 111 , and the second sidewall spacer 112 is located between the isolation layer 107 and the first sidewall spacer 111 .

[0070] In some embodiments, the material of the first spacer 111 includes silicon nitride, silicon oxide, or silicon oxynitride.

[0071] In some embodiments, the material of the second spacer 112 includes silicon nitride, silicon oxide, or silicon oxynitride.

[0072] In some embodiments, the ratio of the thickness of the first sidewall 111 to the thickness of the second sidewall 112 is 0.1 to 10. The ratio of the thickness of the first sidewall 111 to the thickness of the second sidewall 112 may be 0.1 to 0.5, 0.5 to 1, 1 to 2.3, 2.3 to 3.8, 3.8 to 5.2, 5.2 to 6.7, 6.7 to 8.2, or 8.2 to 10. The ratio of the thickness of the first sidewall 111 to the thickness of the second sidewall 112 may be 0.3, 0.5, 1.3, 1.9, 2.8, 4.1, 5.2, 6.8, 7.3, 8.5, 9.2, or 10.

[0073] When the ratio of the thickness of the first sidewall 111 to the thickness of the second sidewall 112 is within the above range, the thickness of the first sidewall 111 itself can serve as a protective layer for the gate structure 105 to prevent etching damage to the gate structure 105 during the etching process. On the contrary, when the thickness of the first sidewall 111 is large, the proportion of the second sidewall removed by etching is small, and the first sidewall may need to be etched, resulting in repeated processes and increased process complexity, or the thickness of the formed barrier layer is thin, and the breakdown voltage between the gate structure and the conductive pillar is too small.

[0074] When the ratio of the thickness of the first side wall 111 to the thickness of the second side wall 112 is within the above range, the second side wall 112 that needs to be removed is larger, the area of ​​the metal silicide layer 113 can be increased, and a barrier layer with a higher dielectric constant can be used as a dielectric layer to reduce the breakdown voltage and suppress leakage current, thereby increasing the breakdown voltage between the gate structure and the conductive column.

[0075] refer to Fig.12 , patterning the isolation layer 107 and forming the groove 110. In the step of patterning the isolation layer 107, at least a portion of the width of the second sidewall is also removed.

[0076] In some embodiments, the material of the second spacer 112 is the same as that of the isolation layer 107; during the step of patterning the isolation layer 107, the second spacer 112 is removed at the same time. In this way, the step of removing the second spacer 112 can be reduced, the process can be simplified, the preparation cost can be reduced, and the waiting time between patterning the isolation layer 107 and removing the second spacer 112 can be avoided, thereby speeding up the process.

[0077] In some embodiments, the material of the second spacer 112 is different from the material of the isolation layer 107 ; after patterning the isolation layer 107 , the method further includes: removing the second spacer 112 .

[0078] refer to Fig.13 , forming a barrier layer 114 , the barrier layer 114 at least covers the inner wall of the groove 110 and the outer side of the first sidewall 111 ; forming a conductive column 115 , the conductive column 115 fills the groove 110 and is in electrical contact with the metal silicide layer 113 .

[0079] In the method for preparing the semiconductor structure provided by the embodiment of the present disclosure, after forming the groove 110 and before forming the conductive column 115, a barrier layer 114 is formed in the groove 110, and the barrier layer 114 at least covers the inner wall of the groove 110, thereby increasing the range of the groove 110 as much as possible within a limited area. Since the barrier layer 114 is provided to isolate the formed conductive column 115 from the electrical insulation between the gate structure 105, the distance between the groove 110 and the gate structure 105 can be set to be smaller, that is, the cross-sectional area of ​​the groove 110 is larger, so that the area of ​​the exposed doping region 103 is larger, and the area of ​​the formed metal silicide layer 113 is larger, which can ensure that the area where the conductive column 115 contacts the doping region 103 is the metal silicide layer 113, and the contact area between the conductive column 115 and the doping region 103 is larger, so that the contact resistance is smaller, and the resistance value of the conductive column 115 itself is smaller, thereby effectively improving the reliability and electrical performance of the semiconductor structure.

[0080] If the relative dielectric constant of the material of the blocking layer 114 is greater than the relative dielectric constant of the material of the sidewall 106, then the blocking layer 114 with a high dielectric constant is located between the conductive column 115 and the gate structure 105. The blocking layer 114 with a higher relative dielectric constant has a stronger ability to bind the charges in the conductive column 115, that is, the blocking layer 114 can suppress the tunneling leakage current generated by the gate structure 105 and the tunneling leakage current generated by the conductive column 115, reduce the possibility of direct tunneling of electrons between the conductive column 115 and the gate structure 105, thereby increasing the breakdown voltage between the gate structure 105 and the conductive column 115, avoiding the problem of leakage current between the gate structure 105 and the conductive column 115, and improving the yield of the semiconductor structure.

[0081] Accordingly, according to some embodiments of the present disclosure, the embodiments of the present disclosure further provide a semiconductor structure, which can be prepared using the semiconductor structure preparation method provided by the above embodiments. Elements that are the same or similar to the above embodiments will not be described in detail here.

[0082] refer to Fig.10 The semiconductor structure includes: a substrate 100, wherein the substrate 100 has a channel region 102 and doped regions 103 located on both sides of the channel region 102, a gate structure 105 directly opposite to the channel region 102, and a sidewall 106 is formed on the sidewall of the gate structure 105, the sidewall is adjacent to the doped region 103, and the substrate 100 also has an isolation layer 107 covering the sidewall 106 and the doped region 103; a metal silicide layer 113, wherein the metal silicide layer 113 is located in the doped region 103; a conductive column 115 located in the isolation layer 107, wherein the conductive column 115 is electrically in contact with the metal silicide layer 113; and a barrier layer 114, wherein the barrier layer 114 is located between the isolation layer 107 and the conductive column 115, and the barrier layer 114 is also located between the sidewall 106 and the conductive column 115.

[0083] In some embodiments, the substrate 100 may be made of a semiconductor material and may contain a P-type doping element or an N-type doping element.

[0084] In some embodiments, the substrate 100 has a plurality of active regions and an isolation structure 101 that separates each active region. The isolation structure 101 is used to separate each two active regions, thereby subsequently forming transistor structures.

[0085] In some embodiments, the material of the active region includes semiconductor material or amorphous material. The active region can be prepared from the same original substrate as the substrate 100, that is, the material of the active region is the same as that of the substrate 100. In some embodiments, the material of the active region is different from that of the substrate 100.

[0086] In some embodiments, the active region includes a channel region 102 and doped regions 103 located on both sides of the channel region 102. The doped regions 103 serve as a source or drain of the transistor structure. One of the doped regions 103 is electrically connected to the bit line structure, and the other doped region 103 is electrically connected to the capacitor structure.

[0087] In some embodiments, the isolation structure 101 may be a shallow trench isolation structure or an isolation structure formed of an isolation material. The isolation structure 101 may be a single-layer film layer or a multi-layer film layer.

[0088] In some embodiments, the gate structure 105 is used as a word line structure later, and the gate structure 105 can be a metal gate structure or a polysilicon gate structure. A gate dielectric layer 104 is provided between the gate structure 105 and the channel region 102 .

[0089] In some embodiments, the spacer 106 is used to protect the gate structure 105. The material of the spacer 106 includes silicon nitride.

[0090] In some embodiments, the material of the isolation layer 107 includes silicon oxide.

[0091] In some embodiments, the metal silicide layer 113 is used to reduce the sheet resistance and contact resistance of the doped region 103, and can be designed to obtain a smaller series resistance, reduce RC delay, and increase the speed of the circuit. The metal silicide layer 113 includes thin films such as TiSi2, CoSi2, and NiPtSi.

[0092] In some embodiments, the barrier layer 114 also covers the outer surface of the spacer 106 .

[0093] In some embodiments, the barrier layer 114 is also located on a portion of the surface of the metal silicide layer 113 .

[0094] In some embodiments, the conductive pillar 115 may serve as a bit line structure or a capacitor plug.

[0095] In some embodiments, the material of the conductive pillar 115 includes at least one of tungsten, tantalum, titanium, tantalum nitride, or titanium nitride.

[0096] In some embodiments, the thickness of the conductive pillar 115 and the thickness of the blocking layer 114 are used to ensure that the thickness of the blocking layer 114 is moderate, which can not only ensure that the breakdown voltage between the gate structure 105 and the conductive pillar 115 is large, but also ensure that the area of ​​the conductive pillar 115 is large, so that the electrical performance of the conductive pillar 115 is better.

[0097] In some embodiments, the dielectric constant of the material of the blocking layer 114 is greater than the dielectric constant of the material of the sidewall 106. The blocking layer 114 with a high dielectric constant is located between the conductive column 115 and the gate structure 105. The blocking layer 114 with a higher relative dielectric constant has a stronger ability to bind the charges in the conductive column 115, that is, the blocking layer 114 can suppress the tunneling leakage current generated by the gate structure 105 and the tunneling leakage current generated by the conductive column 115, reduce the possibility of direct tunneling of electrons between the conductive column 115 and the gate structure 105, thereby increasing the breakdown voltage between the gate structure 105 and the conductive column 115, avoiding the problem of leakage current between the gate structure 105 and the conductive column 115, and improving the yield of the semiconductor structure.

[0098] Those skilled in the art can understand that the above-mentioned embodiments are specific examples for realizing the present disclosure, and in practical applications, various changes can be made to them in form and details without departing from the spirit and scope of the present disclosure. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present disclosure, so the protection scope of the present disclosure shall be based on the scope defined in the claims.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: Providing a substrate, wherein the substrate has a channel region and doped regions located on both sides of the channel region, the substrate has a gate structure directly opposite to the channel region, and a sidewall is formed on the sidewall of the gate structure, the sidewall is adjacent to the doped region, and the substrate also has an isolation layer covering the sidewall and the doped region; Patterning the isolation layer to form a groove exposing the doped region; Performing metallization treatment on the doped region exposed by the groove to form a metal silicide layer; forming a barrier layer, wherein the barrier layer at least covers the inner wall of the groove; A conductive pillar is formed, the conductive pillar filling the groove and electrically contacting the metal silicide layer.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that: Before the metallization process is performed, a portion of the inner wall of the groove exposes at least a portion of the side surface of the sidewall away from the gate structure.

3. The method for preparing a semiconductor structure according to claim 1 or 2, characterized in that: The sidewall spacer includes: a first sidewall spacer and a second sidewall spacer, wherein the first sidewall spacer covers the sidewall of the gate structure, the second sidewall spacer covers the sidewall of the first sidewall, and the second sidewall spacer is located between the isolation layer and the first sidewall; in the step of patterning the isolation layer, at least a portion of the width of the second sidewall spacer is also removed.

4. The method for preparing a semiconductor structure according to claim 3, characterized in that: The material of the second sidewall spacer is the same as that of the isolation layer; and in the step of patterning the isolation layer, the second sidewall spacer is removed simultaneously.

5. The method for preparing a semiconductor structure according to claim 3, characterized in that: The material of the second sidewall is different from that of the isolation layer; after patterning the isolation layer, the method further includes: removing the second sidewall.

6. The method for preparing a semiconductor structure according to claim 1, characterized in that: The process steps for forming the groove include: forming a first mask layer, the first mask layer is located on the surface of the isolation layer, and the first mask layer has a first through hole; using the first mask layer as a mask, etching the isolation layer along the first through hole to form a groove.

7. The method for preparing a semiconductor structure according to claim 6, characterized in that: The first mask layer covers the entire top surface of the sidewall; after patterning the isolation layer, the method further comprises: performing lateral etching along the inner wall of the groove until a portion of the width of the sidewall is removed.

8. The method for preparing a semiconductor structure according to claim 6, characterized in that: The first through hole also exposes a portion of the top surface of the side wall; using the first mask layer as a mask, while etching the isolation layer along the first through hole, a portion of the width of the side wall directly below the first through hole is also etched.

9. The method for preparing a semiconductor structure according to claim 1, characterized in that: The orthographic projection of the groove on the substrate is located within the metal silicide layer.

10. A semiconductor structure, characterized in that: include: A substrate, wherein the substrate has a channel region and doped regions located on both sides of the channel region, a gate structure directly facing the channel region is provided on the surface of the substrate, and a sidewall is formed on the sidewall of the gate structure, the sidewall is adjacent to the doped region, and an isolation layer covering the sidewall and the doped region is also provided on the substrate; a metal silicide layer, wherein the metal silicide layer is located in the doped region; A conductive column located in the isolation layer, the conductive column being in electrical contact with the metal silicide layer; A barrier layer is located between the isolation layer and the conductive column, and the barrier layer is also located between the sidewall and the conductive column.

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