MIPI serializer / deserializer supporting photoelectric dual modes and MIPI transmission system

Abstract

An MIPI serializer / deserializer supporting photoelectric dual modes and an MIPI transmission system comprise a high-speed processing circuit, a low-speed processing circuit, forward and reverse packaging circuits, forward and reverse unpackaging circuits and a photoelectric configuration module which respectively comprise a sending unit and a receiving unit, and the sending unit and the receiving unit comprise an electrical path and / or an optical path. High-speed signals and low-speed signals in an MIPI mode are supported to be serially or deserialized together, the data transmission interface comprises an electric channel and an optical channel, data can be independently supported to be transmitted at the same time through any one or two of the electric channel and the optical channel, and therefore long-distance scenes and short-distance scenes can be supported at the same time.

Description

Technical Field

[0001] The present invention is applicable to the field of optoelectronic signal transmission, and in particular, to a serializer / deserializer based on the MIPI serializer / deserializer transmission protocol that supports both electrical transmission and optical transmission modes, and a MIPI transmission system using the serializer / deserializer. Background Art

[0002] MIPI (Mobile Industry Processor Interface) is the abbreviation of Mobile Industry Processor Interface, an alliance jointly established by ARM, TI, Nokia, ST and other companies in 2003. The alliance aims to standardize various interfaces inside mobile phones (such as camera CSI, display DSI, radio frequency / baseband interface DigRF, etc.) to reduce the complexity of mobile phone design and increase design flexibility. MIPI protocol is widely used in mobile devices such as mobile phones, tablets, smart watches, as well as automobiles and other fields, realizing functions such as high-definition video transmission, high-speed data transmission and low-power transmission.

[0003] MIPI's physical layer interface standards include D-PHY, C-PHY, M-PHY and other standards, among which D-PHY and C-PHY are the most widely used interface standards in the industry. D-PHY is a high-speed serial interface standard designed for mobile devices. It is known for its low power consumption, high speed and good anti-interference ability, and is widely used in mobile devices such as mobile phones and tablets. C-PHY was proposed after D-PHY to address the limitations of D-PHY in high-speed data transmission and low power consumption. D-PHY has been widely used in the market since 2009. As a simple source synchronous PHY, it uses a clock line and multiple data lines. Although it is suitable for many application scenarios, it is insufficient when facing high bandwidth requirements. C-PHY was proposed to meet this challenge. By introducing a combination of three-phase encoding and three signal lines to transmit data, it can transmit more information in each clock cycle, thereby improving data transmission efficiency. In addition, C-PHY does not rely on an independent clock line, but uses signal change edge triggering for data synchronization. This design improves anti-interference ability and design flexibility, and is particularly suitable for application scenarios that require high bandwidth.

[0004] Both D-PHY and C-PHY adopt a configurable channel number solution. For example, D-PHY can support 1, 2, 4 data channels, while C-PHY can support 1, 2, 3 channels. D-PHY has a fixed clock channel, and the minimum number of data channels n is 1. Each channel corresponds to 2 data lines, so there are 2 (n + 1) data lines in total. The C-PHY interface adopts a channel configuration method called "Trio". Each Trio consists of three lines for data transmission, which represents a data channel. C-PHY does not have a dedicated clock channel. If its data channel number is n, there will be 3n data lines in total. Therefore, D-PHY and C-PHY are both physical interface standards that require multiple data lines. In addition, MIPI mainly standardizes various interfaces inside mobile phones, so it focuses on short-distance application scenarios. The physical interfaces such as D-PHY and C-PHY defined by it cannot support long-distance transmission.

[0005] With the popularity of MIPI protocol, peripherals and main controllers using D-PHY / C-PHY interface are applied to other fields, such as automobiles, endoscopes, etc., and the applications in these fields have certain requirements for transmission distance and strict requirements for electromagnetic compatibility. To solve these problems, SerDes (Serializer / Deserializer) is loaded on the transmission link of D-PHY / C-PHY, and simplifies the intermediate transmission data line. One or more pairs of differential lines are used to realize the transmission of multiple D-PHY / C-PHY signals, which reduces the cable cost, eliminates the crosstalk between high-speed channels, and improves electromagnetic compatibility.

[0006] With the update of the version, the rate of D-PHY continues to increase. From 1.0Gbps in version v1.0 to 1.5Gbps in version v1.1, to 2.5Gbps in version v1.2, and 4.5Gbps in version v2.0, it finally reached a rate of 9Gbps ​​in version v3.0, and the rate of C-PHY v2.1 also reached 13.68Gbps / Trio. With the increase of single-channel rate, if data compression and decompression technology is not adopted, the serial rate of D-PHY / C-PHY signals will reach more than 36Gbps (D-PHY 4 channels, 9Gbps / channel). If such a high-speed serial signal is still transmitted by copper wire, it is difficult to achieve long-distance transmission. In this case, optical transmission is a good solution. However, in short-distance transmission applications, the comprehensive cost and reliability of optical transmission are weaker than copper wire transmission solutions.

[0007] In addition, in actual applications, there are application scenarios with multiple cameras. In order to reduce the number of SerDes chips, a single SerDes chip needs to be able to support dual cameras and multiple cameras. In addition, some cameras are configured through I 2 C is configured. In addition, there may be a need to transmit low-speed signals such as GPIOs. The above low-speed signals can also be transmitted using SerDes.

[0008] Therefore, how to cope with long-distance and short-distance application scenarios at the same time, reduce the transmission cost of MIPI chips, improve the reliability of transmission solutions, and support the transmission needs of low-speed signals including multiple cameras has become a technical problem that needs to be urgently solved by existing technologies. Summary of the invention

[0009] The purpose of the present invention is to propose a MIPI integrated circuit supporting optical and electrical dual modes, including a serializer and a deserializer, and a MIPI transmission system supporting optical and electrical dual modes using the above MIPI serializer and deserializer, thereby achieving support for long and short distance data transmission.

[0010] To achieve this object, the present invention adopts the following technical solutions:

[0011] A MIPI serializer supporting optical and electrical dual modes, comprising:

[0012] A first high-speed processing circuit, a first low-speed processing circuit, a forward packetizing circuit, a reverse unpacking circuit, an optoelectronic configuration module, a receiving unit and at least one transmitting unit;

[0013] There is at least one first high-speed processing circuit, and each high-speed processing circuit includes multiple data channels to support at least one MIPI interface located at the MIPI data transmitting end, and is used to receive the first high-speed signal to be transmitted in the MIPI interface, generate the first high-speed data and transmit it to the forward packet circuit for serial conversion;

[0014] The first low-speed processing circuit is used to receive a first low-speed signal to be transmitted from a MIPI data transmitting end, generate a first low-speed signal and send it to the forward packetizing circuit for serial conversion, receive a second low-speed signal from a reverse unpacking circuit, and send it to the MIPI data transmitting end;

[0015] The forward packetizing circuit is used to combine and encapsulate the received first high-speed data and the first low-speed signal into a first serial data frame, and output it to the optoelectronic configuration module;

[0016] The reverse unpacking circuit is used to unpack the second serial data frame received from the optoelectronic configuration module and send the obtained second low-speed signal to the first low-speed processing circuit;

[0017] The optoelectronic configuration module is used to send the first serial data frame to be sent through the electrical path and / or optical path in the at least one sending unit, and receive the second serial data frame transmitted by the electrical path and / or optical path in the receiving unit;

[0018] Each of the transmitting units includes an electrical transmitting circuit and an optical transmitting circuit, which transmit the first serial data frame of high-speed transmission by circuit or optical transmission respectively;

[0019] The receiving unit includes an electrical receiving circuit and an optical receiving circuit, which receive the second serial data frame transmitted at a high speed through circuit or optical transmission respectively.

[0020] Optionally, it also includes a channel configuration module, which is used to combine and configure multiple data channels in one or more of the first high-speed processing circuits to form a corresponding MIPI interface, and transmit the channel configuration information to the forward packetization circuit for encapsulation of the first serial frame.

[0021] Optionally, the first high-speed processing circuit also includes a clock channel, which is configured in combination with multiple data channels, or when the clocks of multiple MIPIs are the same, only one clock is used or one clock is recovered from the data channel, and the multiple MIPI interfaces are combined into one MIPI interface for forward packetization.

[0022] Optionally, an idle detection circuit is also provided for detecting the first data channel or the first clock channel of the MIPI interface and the receiving unit, and notifying the power management module to wake up from sleep.

[0023] Optionally, the number of data channels and clock channels in the high-speed processing circuit is set according to the number and type of configured MIPI interfaces.

[0024] Optionally, the sending unit and the receiving unit can independently select their own electrical path and optical path, and transmit only through the electrical path, or only through the optical path, or simultaneously through the electrical path and the optical path.

[0025] The present invention accordingly discloses a MIPI deserializer supporting optical and electrical dual modes, comprising:

[0026] a second high-speed processing circuit, a second low-speed processing circuit, a forward unpacking circuit, a reverse packing circuit, an optoelectronic configuration module, a transmitting unit, and at least one receiving unit;

[0027] There is at least one second high-speed processing circuit, and each high-speed processing circuit includes multiple data channels to support at least one MIPI interface located at the MIPI data receiving end, and is used to receive the third high-speed data obtained by the forward unpacking circuit parsing the third serial data frame for transmission to the MIPI interface;

[0028] The second low-speed processing circuit is used to receive a fourth low-speed signal from the MIPI data receiving end and generate a fourth low-speed signal, and transmit the fourth low-speed signal to the reverse packetization circuit for serial conversion, and receive the third low-speed signal obtained from the forward unpacking circuit, and send it to the MIPI data receiving end;

[0029] The forward unpacking circuit unpacks the third serial data frame received from the optoelectronic configuration module, sends the obtained third high-speed data to the second high-speed processing circuit, and sends the obtained third low-speed signal to the second low-speed processing circuit;

[0030] The reverse encapsulation circuit is used to combine and encapsulate the fourth low-speed signal obtained from the second low-speed processing circuit into a fourth serial data frame, and output it to the optoelectronic configuration module for high-speed transmission;

[0031] The optoelectronic configuration module is used to receive the third serial data frame transmitted through the electrical path and / or optical path in the at least one receiving unit, and to send the fourth serial data frame to be sent through the electrical path and / or optical path in the sending unit,

[0032] Each of the receiving units includes an electrical receiving circuit and an optical receiving circuit, which receive the third serial data frame transmitted at a high speed by means of circuit or optical transmission respectively;

[0033] The sending unit includes an electrical sending circuit and an optical sending circuit, which send the fourth serial data frame of high-speed transmission through circuit or optical transmission respectively.

[0034] Optionally, it also includes a channel configuration module, which is used to combine and configure multiple data channels in one or more of the second high-speed processing circuits to form a corresponding MIPI interface according to the channel configuration information transmitted from the forward unpacking circuit.

[0035] Optionally, the channel configuration module is further used to combine and configure the clock channel and the multiple data channels in one or more of the second high-speed processing circuits to form a corresponding MIPI interface.

[0036] Alternatively, the clock can be copied to the corresponding clock channel output or coupled to the data channel to restore multiple groups of MIPI signals.

[0037] Optionally, the number of data channels and clock channels in the high-speed processing circuit is set according to the number and type of configured MIPI interfaces.

[0038] Optionally, an idle detection circuit is also included to detect whether there is a signal input to the low-speed processing circuit and the receiving unit, and to notify the power management module to wake up from sleep.

[0039] Optionally, the receiving unit and the sending unit can independently select their own electrical path and optical path, and transmit only through the electrical path, or only through the optical path, or simultaneously through the electrical path and the optical path.

[0040] Optionally, a CDR module is also included, which is used to recover the clock signal coupled in the serial frame, output the correct clock, or embed the clock into the restored MIPI high-speed signal for output.

[0041] The present invention further discloses a MIPI transmission system supporting optical and electrical dual modes, comprising the above-mentioned serializer, the above-mentioned deserializer, and a cable;

[0042] The cable connects the serializer and the deserializer;

[0043] The sending unit of the serializer is connected to the receiving unit of the deserializer through the cable;

[0044] The receiving unit of the serializer is connected to the sending unit of the deserializer through the cable.

[0045] Optionally, the serializer is connected to at least one MIPI interface device at a MIPI data transmitting end, encapsulates the received first high-speed signal and the first low-speed signal into a first serial data frame, sends it to the deserializer through a transmitting unit of the serializer, and receives a second serial data frame from a receiving unit of the serializer;

[0046] The deserializer is connected to at least one MIPI interface located at the MIPI data receiving end, encapsulates the received fourth low-speed signal into a fourth serial frame, sends it to the receiving unit of the serializer through the sending unit of the deserializer, and receives a third serial data frame from the receiving unit of the deserializer.

[0047] Optionally, the MIPI interface is a D-PHY interface or a C-PHY interface. When it is a D-PHY interface, the high-speed processing circuit includes at least one clock channel;

[0048] One MIPI interface can transmit one MIPI interface device or multiple MIPI interface devices with the same source, frequency and phase clock signals.

[0049] Optionally, the electrical transmitting circuit and the electrical receiving circuit have pre-emphasis, de-emphasis, and receiving-end equalization, and use electrical media to perform bidirectional data transmission in a half-duplex manner on the same physical channel;

[0050] The optical transmitting circuit and the optical receiving circuit use optical media, and in a full-duplex mode, each of the receiving and transmitting uses an independent physical channel to perform bidirectional data transmission.

[0051] Optionally, the low-speed signal includes IIC, SPI, IIS, GPIOs and Master Clock, and forward and / or reverse data transmission is performed according to protocol regulations.

[0052] Optionally, the serializer and the deserializer also include a power management module, which performs power management based on information from an idle detection circuit, whether the optical receiving circuit has an optical signal, and whether there is a signal on the low-speed circuit. If no high-speed signal, optical signal or low-speed signal is obtained, the corresponding circuit is put into a sleep state; when a high-speed signal, optical signal or low-speed signal is obtained, the corresponding circuit in the sleep state is awakened.

[0053] Optionally, in the serializer and the deserializer:

[0054] The optical transmission circuit also has an encoding circuit for encoding the optical transmission signal;

[0055] The optical receiving circuit also has a decoding circuit for decoding the obtained optical signal.

[0056] The present invention also discloses a MIPI serializer supporting optical and electrical dual modes, comprising:

[0057] a first high-speed processing circuit, a first low-speed processing circuit, a forward packetizing circuit, a reverse unpacking circuit, an optoelectronic configuration module, at least one pin group, a low-speed transmission interface, at least one electrical drive circuit, at least one electrical high-speed interface, at least one encoding circuit, at least one optical drive circuit, and at least one light emitting interface;

[0058] The first high-speed processing circuit is used to receive the first high-speed data from the at least one pin group and provide it to the forward packet circuit;

[0059] The first low-speed processing circuit is used to receive the first low-speed data from the low-speed transmission interface and provide the first low-speed data to the forward packet circuit;

[0060] The forward packetizing circuit is used to package the received first high-speed data and / or the first low-speed data into a first serial data frame, and provide it to the optoelectronic configuration module;

[0061] The optoelectronic configuration module is used to provide the first serial data frame to the at least one electrical drive circuit and / or the at least one encoding circuit;

[0062] The at least one electric driving circuit is connected to the at least one electric high-speed interface in a one-to-one correspondence, wherein the electric driving circuit drives the corresponding electric high-speed interface to output a high-speed serial electric signal according to the received first serial data frame;

[0063] The at least one encoding circuit is connected to the at least one optical driving circuit in a one-to-one correspondence, and the at least one optical driving circuit is connected to the at least one light-emitting interface in a one-to-one correspondence, wherein the encoding circuit encodes the received first serial data frame and drives the corresponding optical driving circuit to output an optical signal through the corresponding light-emitting interface.

[0064] Optionally, the optoelectronic configuration module is further used to receive a second serial data frame from the electrical receiving circuit and / or the decoding circuit and provide it to the reverse unpacking circuit;

[0065] The electrical receiving circuit is connected to the at least one electrical high-speed interface and generates the second serial data frame based on one or more received high-speed serial electrical signals from the at least one electrical high-speed interface;

[0066] The decoding circuit is connected to the optical receiving circuit, the optical receiving circuit receives the optical signal from the optical receiving interface and generates an electrical signal to provide to the decoding circuit, and the decoding circuit generates the second serial data frame according to the electrical signal received from the optical receiving circuit;

[0067] The reverse unpacking circuit is used to obtain second low-speed data from the second serial data frame received through the optoelectronic configuration module, and provide the obtained second low-speed data to the first low-speed processing circuit;

[0068] The first low-speed processing circuit is further used to output the second low-speed data obtained from the reverse unpacking circuit through the low-speed transmission interface.

[0069] Optionally, the idle detection circuit is used to detect whether there is a signal input on the at least one pin group, at least one electrical high-speed interface and / or light receiving interface, and wake up and / or sleep through the power management module based on the detection result.

[0070] Optionally, the channel configuration module is used to configure the correspondence between the pins of the at least one pin group and the D-PHY interface or the C-PHY interface connected to the MIPI serializer.

[0071] Optionally, the at least one pin group includes a first pin group and a second pin group;

[0072] The first pin group is connected to the first high-speed processing circuit;

[0073] The second pin group is connected to the second high-speed processing circuit.

[0074] Optionally, the channel configuration module configures the first pin group to correspond to a first D-PHY interface;

[0075] The channel configuration module configures the second pin group to correspond to the second D-PHY interface.

[0076] Optionally, the channel configuration module configures all pins of the first pin group and a first part of or all pins of the second pin group to correspond to a first D-PHY interface, and processes a D-PHY interface whose number of channels exceeds the total number of pins in a group;

[0077] The channel configuration module configures a second portion of pins of the second pin group to correspond to a second D-PHY interface;

[0078] The channel configuration module configures the first high-speed processing circuit to receive first high-speed data from the configured first pin group and the first part of the pins of the second pin group;

[0079] The channel configuration module configures the second high-speed processing circuit to receive second high-speed data from a second portion of pins of the configured second pin group.

[0080] Optionally, the first pin group includes a plurality of data channels;

[0081] The channel configuration module configures the first high speed processing circuit to receive data from the plurality of data channels using a clock signal received from one of the pins of the first pin group.

[0082] It also includes a CDR module, which is used to recover a clock signal from a signal of a first pin of the first pin group and generate an internal clock, and the first high-speed processing circuit receives data from the first pin using the internal clock.

[0083] In summary, the present invention has the following advantages:

[0084] 1. Based on the expansion of MIPI signal usage scenarios, it can support both dielectric transmission and optical transmission, thus meeting both short-distance and long-distance working scenarios.

[0085] 2. The optical and dielectric transmission channels are independently controllable. Either one of them can be used alone or both can be used at the same time, thus ensuring the reliability of information transmission in important occasions or in harsh environments.

[0086] 3. One MIPI signal can simultaneously support multiple MIPI devices with the same source, frequency and phase clock, increasing the number of MIPI devices supported by the system.

[0087] 4. According to the characteristics of MIPI signals, the idle circuit working mode is improved. Only the first clock channel, or the first data channel, and the input reverse high-speed channel, that is, the receiving unit, are detected to notify the power management module to wake up from sleep, thereby reducing the power consumption of the idle system. BRIEF DESCRIPTION OF THE DRAWINGS

[0088] Figure 1 is a module diagram of a MIPI transmission system supporting optical and electrical dual modes using a MIPI serializer and a deserializer according to a specific embodiment of the present invention;

[0089] Figure 2 is a framework diagram of a MIPI serializer supporting optical and electrical dual modes in D-PHY mode according to a specific embodiment of the present invention;

[0090] Figure 3 is a framework diagram of a MIPI deserializer supporting optical and electrical dual modes in D-PHY mode according to a specific embodiment of the present invention;

[0091] Figure 4 is a framework diagram of a MIPI serializer supporting optical and electrical dual modes in C-PHY mode according to a specific embodiment of the present invention;

[0092] Figure 5 is a framework diagram of a MIPI deserializer supporting optical and electrical dual modes in C-PHY mode according to a specific embodiment of the present invention;

[0093] Figure 6 is a framework diagram of a MIPI deserializer supporting optical and electrical dual modes in D-PHY mode according to another specific embodiment of the present invention;

[0094] Figure 7 is a framework diagram of a MIPI deserializer supporting optical and electrical dual modes in C-PHY mode according to another specific embodiment of the present invention;

[0095] Figure 8 is a schematic diagram of connection between two MIPI interface devices using multiple channels in D-PHY mode according to a specific embodiment of the present invention;

[0096] Fig. 9 is a schematic diagram of connection between two MIPI interface devices using multiple channels in D-PHY mode according to a specific embodiment of the present invention;

[0097] Fig.10 is a schematic diagram of connection of four MIPI interface devices using 1 channel in C-PHY mode according to a specific embodiment of the present invention;

[0098] Fig.11 is a schematic diagram of connecting two MIPI interface devices with different numbers of channels in C-PHY mode according to a specific embodiment of the present invention;

[0099] Fig.12 It is a connection diagram of a MIPI transmission system with multiple MIPI interface devices according to a specific embodiment of the present invention.

[0100] The technical features indicated by the reference numerals in the figures are:

[0101] 1. Serializer; 11. First high-speed processing circuit; 12. First low-speed processing circuit; 13. Forward packetization circuit; 14. Reverse unpacking circuit; 2. Deserializer; 21. Second high-speed processing circuit; 22. Second low-speed processing circuit; 23. Forward unpacking circuit; 24. Reverse packetization circuit; 15 and 25 are optoelectronic configuration modules; 16 and 26 are channel configuration modules; 17 and 27 are idle detection circuits. DETAILED DESCRIPTION

[0102] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only parts related to the present invention, rather than all structures, are shown in the accompanying drawings.

[0103] In the present invention, the terms used are defined as follows:

[0104] MIPI interface devices refer to devices with MIPI interfaces, including but not limited to mobile phones, tablet computers, smart watches, cameras, camera CSI, display DSI, RF / baseband interface DigRF, and various interfaces applicable inside mobile phones.

[0105] MIPI data transmitter, one end used to send MIPI high-speed signals, usually connected to a MIPI interface device, used for unidirectional transmission of MIPI high-speed signals, also known as MIPI Master.

[0106] The MIPI data receiving end is used to receive the transmitted MIPI high-speed signal, which is called MIPI Slave.

[0107] High-speed signal, used to represent the signal sent by the MIPI interface device, or a general high-speed signal similar to the MIPI signal, such as single-edge or double-edge clock sampling.

[0108] Low-speed signals are used to indicate that the rates of IIC, SPI, IIS, GPIOs, etc. are lower than 10Mbps, and the Master Clock (MCLK) signal with a rate of no more than 50MHz for the image sensor. The transmission speed of this type of signal is lower than the rate of MIPI interface device signals, and some signals need to be transmitted in both directions.

[0109] Forward is used to indicate the transmission direction of MIPI high-speed signals, which refers to the direction from the MIPI data transmitter to the MIPI data receiver.

[0110] Reverse direction is used to indicate the opposite direction of the transmission direction of MIPI high-speed signals. It is usually used to transmit some low-speed signals that require bidirectional transmission. It refers to the direction from the MIPI data receiving end to the MIPI data sending end.

[0111] The present invention is to support serialization or deserialization of high-speed signals and low-speed signals in MIPI mode, and the data transmission interface includes an electrical channel and an optical channel, and can independently support data transmission through any one or both of them at the same time, thereby realizing simultaneous support for long and short distance scenarios.

[0112] For details, see Figure 1 , showing a block diagram of a MIPI transmission circuit supporting optical and electrical dual modes using a MIPI serializer and a deserializer.

[0113] Among them, the serializer 1 and the deserializer 2, the serializer is connected to at least one MIPI interface device located at the MIPI data sending end, and the deserializer is connected to at least one MIPI interface located at the MIPI data receiving end, and both form a reverse high-speed channel and at least one forward high-speed channel through their respective sending units and receiving units.

[0114] Serializer 1 is responsible for converting the received MIPI signal, such as D-PHY or C-PHY signal, into serial signals, and serializing the received low-speed signal, merging it into the serial signal of D-PHY or C-PHY, and sending it to deserializer 2 through the forward high-speed channel; and deserializing the data received from the reverse high-speed channel, restoring the low-speed signal and outputting it. Deserializer 2 is responsible for deserializing the serial signal received on the forward high-speed channel, restoring it into a MIPI signal, such as D-PHY or C-PHY signal, and outputting it, and also restoring and outputting the low-speed signal in the serial signal; and at the same time, converting the received low-speed signals, such as IIC, IIS, SPI, GPIO, MCLK, etc., into serial signals, and then outputting them to serializer 1 through the reverse high-speed channel.

[0115] Hereinafter, the present invention will take a camera with a MIPI interface in D-PHY mode and C-PHY mode as an example to illustrate the serializer 1 and the deserializer 2 of the present invention.

[0116] See also Figure 2 The MIPI serializer 1 supporting optical and electrical dual modes in D-PHY mode according to a specific embodiment of the present invention is shown. Figure 4 In FIG. 1 , a MIPI serializer 1 supporting optical and electrical dual modes in C-PHY mode is shown. The structures of the two are basically the same, including:

[0117] A first high-speed processing circuit 11, a first low-speed processing circuit 12, a forward packetizing circuit 13, a reverse unpacking circuit 14, an optoelectronic configuration module 15, a receiving unit and at least one transmitting unit;

[0118] Among them, there is at least one first high-speed processing circuit 11, and each high-speed processing circuit includes multiple data channels to support at least one MIPI interface located at the MIPI data sending end, which is used to receive the first high-speed signal to be transmitted in the MIPI interface, generate the first high-speed data and transmit it to the forward packet circuit 13 for serial conversion.

[0119] See also Figure 2 In this embodiment, the first high-speed processing circuit 11 has at least two, each of which can process 4 data channels and 2 clock channels. According to the MIPI protocol, each data channel or clock channel corresponds to 2 data lines. In one high-speed processing circuit, there are four data channels A0, A1, A2 and A3, two clock channels A0 and A1, and in another high-speed processing circuit, there are four data channels B0, B1, B2 and B3, two clock channels B0 and B1. Exemplarily, these two high-speed processing circuits can support 4 cameras, allowing each camera to use two data paths. If the number of data channels used by each camera needs to be increased, it is only necessary to increase the number of data channels in the diagram. Correspondingly, the number of the first high-speed processing circuit 11 can also be increased, and it can be configured according to the MIPI devices that need to be supported and the number of channels supported by each MIPI device.

[0120] exist Figure 2 In the figure, the D-PHY interface serializer 1 includes 4 clock channels and 8 data channels, and can connect up to 4 cameras at the same time, and each camera supports up to 2 data channels. In order to support more cameras and the number of data channels supported by each camera, the first high-speed processing circuit 11 can expand the number of channels. Figure 4In the example, the serializer 1 of the C-PHY interface can support up to 4 cameras. When supporting 4 cameras, the diagram only allows each camera to use 1 data channel. If you need to increase the number of data channels that can be used by each camera, you only need to increase the number of data channels in the diagram.

[0121] The first low-speed processing circuit 12 is used to receive the low-speed signal to be transmitted from the MIPI data sending end, send it to the forward packetizing circuit 13 for serial conversion, receive the second low-speed signal from the reverse unpacking circuit 14, generate a first low-speed signal and send it to the MIPI data sending end.

[0122] The forward packetizing circuit 13 is used to combine and encapsulate the received first high-speed data and the first low-speed data into a first serial data frame, and output the first serial data frame to the optoelectronic configuration module 15 .

[0123] The reverse unpacking circuit 14 is used to unpack the second serial data frame received from the optoelectronic configuration module 15 and send the obtained second low-speed data to the first low-speed processing circuit.

[0124] Specifically, the forward packet circuit 13, according to the configuration information input by the channel configuration module, encapsulates the received first high-speed data and the first low-speed data into a serial data frame in a certain arrangement and combination. Exemplarily, in order to reduce the amount of data after serialization, and considering that the change rate of the low-speed signal is very low, the serial data frame encapsulation can adopt time division multiplexing technology, and the low-speed data and some other configuration information occupy one or more bits in the serial data frame in a time-sharing manner. For example, if there are 10 data sampled at a time at low speed, which only occupies one bit in the serial data frame, then each serial data frame only transmits 1 bit of the 10 data, and 10 serial data frames are used to complete the transmission of the 10 data sampled once. Assuming that 6 serial data frames are used to complete the transmission of other configuration information, each frame only transmits 1 bit of the configuration information. Assuming that the transmission rate of the serial data frame is N frames / second, the sampling rate of the low-speed data is set to N / 16Hz, then the low-speed data transmission after each sampling can be completed.

[0125] The optoelectronic configuration module 15 is used to send the first serial data frame to be sent through the electrical path and / or optical path in the at least one sending unit, and receive the second serial data frame transmitted by the electrical path and / or optical path in the receiving unit.

[0126] Each of the transmitting units includes an electrical transmitting circuit and an optical transmitting circuit, which transmit the first serial data frame of high-speed transmission by circuit or optical transmission respectively;

[0127] The receiving unit includes an electrical receiving circuit and an optical receiving circuit, which receive the second serial data frame transmitted at a high speed through circuit or optical transmission respectively.

[0128] The optoelectronic configuration module 15 selects whether the serialized data is to go through the electrical interface, the optical interface, or both the electrical interface and the optical interface according to the register configuration or the pin configuration, and sends the data to or receives the data from these interfaces. The configuration of the forward transmission channel and the reverse transmission channel are independent, that is, the forward transmission channel can be configured as optical transmission, and the reverse transmission channel can be configured as electrical transmission, so as to achieve flexible configuration and meet different application scenarios. In addition, for application scenarios with relatively high reliability requirements, the physical transmission channels of the optical path and the circuit can exist at the same time, and the optoelectronic transmission is switched in a dynamic configuration mode to achieve the backup of the serial high-speed transmission channel.

[0129] The sending unit and the receiving unit can independently select their own electrical path and optical path, and transmit only through the electrical path, or only through the optical path, or transmit through both the electrical path and the optical path.

[0130] Specifically, the sending unit can be configured for optical transmission, while the receiving unit can be configured for electrical transmission, to achieve flexible configuration and meet different application scenarios. In addition, for application scenarios with relatively high reliability requirements, the physical transmission channels of the optical path and the circuit can exist at the same time, and through dynamic configuration, dynamic switching of optical and electrical transmission can be achieved, thereby realizing backup of serial high-speed transmission channels.

[0131] The MIPI serializer 1 also includes a channel configuration module 16, which is used to combine and configure multiple data channels in one or more of the first high-speed processing circuits 11, or when a clock channel exists, to form a corresponding MIPI interface, and transmit the channel configuration information to the forward packetization circuit 13 for encapsulation of the first serial data frame.

[0132] When the clocks of multiple MIPIs are the same, only one clock is used or one clock is recovered from the data channel, and the multiple MIPI interfaces are combined into one MIPI interface for forward packet transmission.

[0133] Specifically, the channel configuration module 16 is configured according to user configuration such as register settings or pin configuration. In a specific embodiment, the channel configuration module 16 can independently process the two first high-speed processing circuits 11 in the MIPI serializer 1 to support dual cameras. The output clocks of the two cameras have no dependency requirements and can be completely independent. In addition, they can each simultaneously support dual cameras with the same clock source, frequency and phase. When they both support dual cameras at the same time, that is, support four cameras, Figure 2 Only two data channels are allowed for each camera. Figure 4In the example of the C-PHY mode, if the clocks used by the two cameras are of the same source, frequency and phase, they can be supported by a first high-speed processing circuit and can allow each camera to connect to one data channel, that is, the first high-speed processing circuit only needs to rely on the clock in one camera to complete the data recognition of the dual cameras, thereby enabling the two high-speed processing circuits to support four cameras.

[0134] In the D-PHY signal mode, the first high-speed processing circuit 11 obtains the clock from the clock channel. If in the C-PHY signal mode, the first high-speed processing circuit 11 needs to include a CDR function, such as a CDR module, to recover the clock from the data channel.

[0135] Further, the channel configuration module 16 can configure the data channel according to whether there is a signal input on the clock channel and whether there is data input on the corresponding data channel. For example, if a camera that supports 6 channels is connected, the clock channel of the camera is connected to the clock channel A0, and the data channel of the camera is connected to the clock channel A1 in sequence. Figure 2 The channel configuration module 16 classifies the data channels A0~3 and the data channels B0~1 of the first high-speed processing circuit 11 into one D-PHY interface, configures one of the first high-speed processing circuits to collect data using the clock of the clock channel A0, and transmits the channel configuration information to the forward packet circuit 13, according to the fact that there is a clock on the clock channel A0, there is no clock on the clock channel A1 and the clock channel B0, and there is data on their corresponding data channels.

[0136] Specifically, the channel configuration module can implement channel configuration according to register settings or pin configuration, so as to achieve the purpose of mapping different MIPI interfaces to different processing circuits, and realize the mapping relationship between pins and MIPI interfaces.

[0137] Therefore, further, the number of data channels and clock channels in the first high-speed processing circuit 11 of the present invention is set according to the number of configured MIPI interfaces and the interface type, and the channel configuration module 16 is used to complete the corresponding combination of data channels and clock channels to adapt to the MIPI interface device to be connected.

[0138] The first high-speed data of each MIPI interface device forms a first serial data frame in the forward packet circuit 13 through the channel configuration module 16, and is transmitted through the same forward high-speed channel, that is, the same sending unit. Multiple first serial data frames corresponding to multiple MIPI interface devices are transmitted along different forward high-speed paths, that is, different sending units. In the present invention, multiple MIPI interface devices with the same source, frequency and phase clock signals are transmitted through the same MIPI interface.

[0139] Furthermore, it also has an idle (E-Idle, Electrical IDLE) detection circuit. The usual idle detection circuit is used to detect whether there are high-speed signals on the clock channel and the data channel, and give this status information to the channel configuration module for corresponding configuration, and to the power management module. In addition, it also detects whether there is a high-speed signal input to the receiving unit, whether there is a signal input to the first low-speed processing circuit 12, and gives it to the power management module. The idle detection circuit is also in the working mode in the sleep state, and is used to detect the arrival of high-speed signals and low-speed signals. The arriving signals are given to the power management module to wake up the corresponding circuits.

[0140] However, for serial circuits, due to the existence of multiple data channels or clock channels, if each channel is idle detected, there will be a lot of detection circuits, which will bring complexity and high power consumption in sleep mode, because in sleep mode, the idle detection circuit cannot sleep. To solve this problem, the characteristics of the MIPI interface and the pin constraints connected to the MIPI device are used to detect only the first clock channel (for the D-PHY interface), or the first data channel (for the C-PHY interface), and the input reverse high-speed channel, that is, the receiving unit, to notify the power management module to wake up from sleep mode.

[0141] In summary, Figure 4 The same or corresponding parts of the serializer 1 in the C-PHY mode have the same functions as the serializer 1 in the D-PHY mode, and the main difference is that each first high-speed processing circuit 11 only has multiple data channels but does not contain a separate clock channel, and the first high-speed processing circuit 11 contains a CDR function, such as a CDR module, to recover the clock from the data channel.

[0142] For further information, see Figure 3 The MIPI deserializer 2 supporting the optical-electrical dual mode in the D-PHY mode according to a specific embodiment of the present invention is shown. Figure 5 In FIG. 1 , a MIPI deserializer 2 supporting optical and electrical dual modes in C-PHY mode is shown. The structures of the two are basically the same, including:

[0143] A second high-speed processing circuit 21, a second low-speed processing circuit 22, a forward unpacking circuit 23, a reverse packing circuit 24, an optoelectronic configuration module, a transmitting unit and at least one receiving unit;

[0144] Among them, there is at least one second high-speed processing circuit 21, and each high-speed processing circuit includes multiple data channels to support at least one MIPI interface located at the MIPI data receiving end, which is used to receive the third high-speed data obtained by the forward unpacking circuit 23 to parse the third serial data frame for transmission to the MIPI interface.

[0145] exist Figure 3 In the deserializer 2, the corresponding data channel or clock channel is set as Figure 2 The serializer 1 corresponds to; Figure 5 The corresponding data channel or clock channel settings and Figure 4 The serializer 1 corresponds to the number of cameras supported, the use of the data path by each camera, and the number and specific configuration of data channels of each high-speed processing circuit and the deserializer as a whole.

[0146] The second low-speed processing circuit 22 is used to receive the fourth low-speed signal from the MIPI data receiving end and generate fourth low-speed data, and transmit the fourth low-speed data to the reverse packetization circuit for serial conversion, and receive the third low-speed data obtained from the forward unpacking circuit, and send it to the MIPI data receiving end;

[0147] The forward unpacking circuit 23 unpacks the third serial data frame received from the optoelectronic configuration module 25, sends the obtained third high-speed data to the second high-speed processing circuit 21, and sends the obtained third low-speed data to the second low-speed processing circuit 22;

[0148] The reverse encapsulation circuit 24 is used to combine and encapsulate the fourth low-speed data obtained from the second low-speed processing circuit 22 into a fourth serial data frame, and output it to the optoelectronic configuration module 25 for high-speed transmission;

[0149] The optoelectronic configuration module 25 is used to receive the third serial data frame transmitted through the electrical path and / or optical path in the at least one receiving unit, and to send the fourth serial data frame to be sent through the electrical path and / or optical path in the sending unit,

[0150] Each of the receiving units includes an electrical receiving circuit and an optical receiving circuit, which receive the third serial data frame transmitted at a high speed by means of circuit or optical transmission respectively;

[0151] The sending unit includes an electrical sending circuit and an optical sending circuit, which send the fourth serial data frame of high-speed transmission through circuit or optical transmission respectively.

[0152] The forward unpacking circuit performs reverse unpacking according to the packing rules of the forward packing circuit, and distributes the unpacked data to the corresponding high-speed processing circuit and low-speed processing circuit.

[0153] The reverse encapsulation circuit and reverse unpacking circuit are similar to the forward encapsulation circuit and forward unpacking circuit, except that they only encapsulate low-speed signals. Because optical transmission is not suitable for low-speed signal transmission, the reverse encapsulation circuit adopts the method of increasing the serial rate. Each frame contains the data of the low-speed signal obtained by each sampling, together with some information related to protocol analysis, etc., which are sent to the other end at one time. After receiving the data, the other end restores the data through the reverse unpacking circuit, and gives the accompanying protocol analysis related information to the low-speed processing circuit to restore the low-speed signal and realize the transmission of the low-speed signal.

[0154] Furthermore, it also includes a channel configuration module 26, which is used to combine and configure multiple data channels in one or more of the second high-speed processing circuits 21 to form a corresponding MIPI interface according to the channel configuration information transmitted from the forward unpacking circuit 23. Accordingly, the channel configuration module is also used to combine and configure the clock channel and multiple data channels in one or more of the second high-speed processing circuits to form a corresponding MIPI interface, so that the deserialized D-PHY signal or C-PHY signal is transmitted on the correct channel.

[0155] The channel configuration module can also copy the clock to the corresponding clock channel output or couple it to the data channel to restore multiple groups of MIPI signals.

[0156] For example, if it is recognized that two cameras are connected to the same group of channels, the clock is copied and output on another clock channel of the group to restore two groups of D-PHY signals.

[0157] Similar to the serializer 1, the number of data channels and clock channels in the second high-speed processing circuit is set according to the number and type of configured MIPI interfaces.

[0158] Furthermore, the deserializer 2 also includes an idle detection circuit for detecting whether there is a signal input to the low-speed processing circuit and the receiving unit, and notifying the power management module to perform sleep wake-up.

[0159] The receiving unit and the sending unit can independently select their own electrical path and optical path, and transmit only through the electrical path, or only through the optical path, or transmit through both the electrical path and the optical path.

[0160] It also includes a CDR module for recovering the clock signal coupled in the serial frame, outputting the correct clock or embedding the clock into the restored MIPI high-speed signal for output. Figure 3 and Figure 5 In the example, the number of CDR modules can be determined according to the supported MIPI interface.

[0161] For example, serializer 1 will generate an internal clock based on the received D-PHY clock or the clock recovered from the C-PHY data channel according to certain rules, such as X-multiplication and Y-division. This clock will be coupled to the high-speed serial data and recovered by the CDR module in deserializer 2 to become the internal clock of the deserializer. The deserializer can restore the frequency information of the D-PHY or C-PHY clock signal according to the same rules, and then output the correct D-PHY clock or embed the C-PHY clock into the restored C-PHY data for output according to the clock phase information attached to the high-speed serial data.

[0162] Therefore, if Figure 1 As shown, the present invention further discloses a MIPI transmission system supporting optical and electrical dual modes, including the above-mentioned serializer 1, deserializer 2, and a cable;

[0163] The cable connects the serializer 1 and the deserializer 2;

[0164] The sending unit of the serializer 1 is connected to the receiving unit of the deserializer 2 through the cable;

[0165] The receiving unit of the serializer 1 is connected to the sending unit of the deserializer 2 through the cable.

[0166] The serializer 1 is connected to at least one MIPI interface device at the MIPI data transmitting end, encapsulates the received first high-speed signal and the first low-speed signal into a first serial data frame, sends it to the deserializer 2 through the sending unit of the serializer 1, and receives a second serial data frame from the receiving unit of the serializer;

[0167] The deserializer 2 is connected to at least one MIPI interface located at the MIPI data receiving end, encapsulates the received fourth low-speed signal into a fourth serial frame, sends it to the receiving unit of the serializer through the sending unit of the deserializer, and receives a third serial data frame from the receiving unit of the deserializer.

[0168] In the present invention, the MIPI interface is a D-PHY interface or a C-PHY interface. When it is a D-PHY interface, the high-speed processing circuit includes at least one clock channel;

[0169] One MIPI interface can transmit one MIPI interface device or multiple MIPI interface devices with the same source, frequency and phase clock signals.

[0170] The electrical transmitting circuit and the electrical receiving circuit have pre-emphasis, de-emphasis, and receiving end equalization (EQ) methods, and use electrical media to perform bidirectional data transmission in a half-duplex manner on the same physical channel;

[0171] The optical transmitting circuit and the optical receiving circuit use optical media, and in a full-duplex mode, each of the receiving and transmitting uses an independent physical channel to perform bidirectional data transmission.

[0172] The optical transmitting circuit may include a VCSEL Driver or a Laser Driver, and the optical receiving circuit may include an LA (limiting amplifier) ​​or a TIA (transimpedance amplifier) ​​and an optical detection circuit, etc., which cooperate with the optical chip to support the optical signal transmission. It uses optical media such as glass optical fiber and plastic optical fiber.

[0173] The light receiving circuit may include a light detection circuit for detecting whether there is light and providing the information to the power management module for power management.

[0174] The serializer and the deserializer also include a power management module, which performs power management based on information from an idle detection circuit, whether the optical receiving circuit has an optical signal, and whether there is a signal on the low-speed circuit. If no high-speed signal, optical signal or low-speed signal is obtained, the corresponding circuit is put into a sleep state; when a high-speed signal, optical signal or low-speed signal is obtained, the corresponding circuit in the sleep state is awakened.

[0175] In the serializer and the deserializer:

[0176] The optical transmitting circuit also has an encoding circuit for encoding the optical transmission signal; the optical receiving circuit also has a decoding circuit for decoding the obtained optical signal. The encoding circuit and the decoding circuit can prevent the signal from being maintained at a level for a long time, which is not conducive to the transmission of optical signals. When the optical transmission scheme is selected, a certain algorithm is used to encode the data to be transmitted before data transmission, such as the 8b10b encoding method, and after receiving the data from the optical path, decoding and restoration are performed.

[0177] Multiple electrical high-speed interfaces are formed by the electrical transmitting circuit and the electrical receiving circuit respectively, and multiple light-emitting interfaces and light-receiving interfaces, namely optical high-speed transmission interfaces, are formed by the optical transmitting circuit and the optical receiving circuit respectively.

[0178] In addition, the MIPI transmission system of the present invention can also support different cables, that is, the cable can be an electrical cable, an optical cable, or an optical-electrical hybrid cable.

[0179] For further information, see Figure 61 shows a MIPI serializer 1 supporting optical and electrical dual modes in D-PHY mode according to another specific embodiment of the present invention. Figure 7 In FIG. 1 , a MIPI serializer 1 supporting optical and electrical dual modes in C-PHY mode is shown. The structures of the two are basically the same, including:

[0180] a first high-speed processing circuit, a first low-speed processing circuit, a forward packetizing circuit, a reverse unpacking circuit, an optoelectronic configuration module, at least one pin group, a low-speed transmission interface, at least one electrical drive circuit, at least one electrical high-speed interface, at least one encoding circuit, at least one optical drive circuit, and at least one light emitting interface;

[0181] The first high-speed processing circuit, such as high-speed processing circuit A and high-speed processing circuit B, is used to receive the first high-speed data from the at least one pin group and provide it to the forward packet circuit;

[0182] The first low-speed processing circuit is used to receive the first low-speed data from the low-speed transmission interface and provide the first low-speed data to the forward packet circuit;

[0183] The forward packetizing circuit is used to package the received first high-speed data and / or the first low-speed data into a first serial data frame, and provide it to the optoelectronic configuration module;

[0184] The optoelectronic configuration module is used to provide the first serial data frame to the at least one electrical drive circuit and / or the at least one encoding circuit;

[0185] The at least one electric driving circuit is connected to the at least one electric high-speed interface in a one-to-one correspondence, wherein the electric driving circuit drives the corresponding electric high-speed interface to output a high-speed serial electric signal according to the received first serial data frame;

[0186] The at least one encoding circuit is connected to the at least one optical driving circuit in a one-to-one correspondence, and the at least one optical driving circuit is connected to the at least one light-emitting interface in a one-to-one correspondence, wherein the encoding circuit encodes the received first serial data frame and drives the corresponding optical driving circuit to output an optical signal through the corresponding light-emitting interface.

[0187] exist Figure 6 and Figure 7 In the embodiment, there are respectively a sending unit A and a sending unit B, and each sending unit has a group of optical channels and electrical channels.

[0188] The receiving unit has a set of optical channels, and the electrical channels can be multiplexed with the electrical channels in the sending unit.

[0189] Further, the optoelectronic configuration module is also used to receive a second serial data frame from the electrical receiving circuit and / or the decoding circuit and provide it to the reverse unpacking circuit;

[0190] The electrical receiving circuit is connected to the at least one electrical high-speed interface and generates the second serial data frame based on one or more received high-speed serial electrical signals from the at least one electrical high-speed interface;

[0191] The decoding circuit is connected to the optical receiving circuit, the optical receiving circuit receives the optical signal from the optical receiving interface and generates an electrical signal to provide to the decoding circuit, and the decoding circuit generates the second serial data frame according to the electrical signal received from the optical receiving circuit;

[0192] The reverse unpacking circuit is used to obtain second low-speed data from the second serial data frame received through the optoelectronic configuration module, and provide the obtained second low-speed data to the first low-speed processing circuit;

[0193] The first low-speed processing circuit is further used to output the second low-speed data obtained from the reverse unpacking circuit through the low-speed transmission interface.

[0194] It also has an idle detection circuit and a power management module;

[0195] The idle detection circuit is used to detect whether there is a signal input on the at least one pin group and the input reverse high-speed channel, and wake up and / or sleep through the power management module according to the detection result.

[0196] In order to reduce the complexity of the circuit, the present invention utilizes the characteristics of the MIPI interface and the pin constraints connected to the MIPI device. The idle detection circuit of the serializer 1 can only detect the first clock channel (for the D-PHY interface), or the first data channel (for the C-PHY interface), and the input reverse high-speed channel, that is, the receiving unit, to notify the power management module to wake up from sleep.

[0197] The channel configuration module is used to configure the corresponding relationship between the pins of the at least one pin group and the D-PHY interface or the C-PHY interface connected to the MIPI serializer.

[0198] For further information, see Figure 8-Figure 11 , and may also have multiple high-speed processing circuits, including

[0199] a second high-speed processing circuit;

[0200] The at least one pin group includes a first pin group and a second pin group;

[0201] The first pin group is connected to the first high-speed processing circuit;

[0202] The second pin group is connected to the second high-speed processing circuit.

[0203] Therefore, the channel configuration module configures the first pin group to correspond to the first D-PHY interface;

[0204] The channel configuration module configures the second pin group to correspond to the second D-PHY interface.

[0205] The channel configuration module configures all pins of the first pin group and a first part of pins of the second pin group to correspond to a first D-PHY interface;

[0206] The channel configuration module configures a second portion of pins of the second pin group to correspond to a second D-PHY interface;

[0207] The channel configuration module configures the first high-speed processing circuit to receive first high-speed data from the configured first pin group and the first part of the pins of the second pin group;

[0208] The channel configuration module configures the second high-speed processing circuit to receive second high-speed data from a second portion of pins of the configured second pin group.

[0209] The first pin group includes a plurality of data channels;

[0210] The channel configuration module configures the first high speed processing circuit to receive data from the plurality of data channels using a clock signal received from one of the pins of the first pin group.

[0211] Therefore, in Figure 8-Figure 11 In the figure, it is shown that cameras with different channels are connected to C-PHY or D-PHY cameras with different numbers of channels, and data transmission is achieved through the configuration of the pins in pin group A and pin group B.

[0212] For example, Figure 8 Two 4-channel cameras are connected and transmitted through two 4-channel D-PHY interfaces.

[0213] Fig. 9 A 6-channel camera and a 2-channel camera are respectively connected through the D-PHY interface of the corresponding channel for transmission, wherein multiple pins in the pin group are combined and used under the configuration of the channel configuration module.

[0214] Fig.10 The four 1-channel cameras are connected and transmitted through the C-PHY interface of the corresponding channel, and two of the cameras are of the same source, frequency and phase, so that they can be transmitted through one MIPI interface.

[0215] Fig.11 A 1-channel camera and a 3-channel camera are respectively connected through the C-PHY interface of the corresponding channel for transmission, wherein multiple pins in the pin group are combined and used under the configuration of the channel configuration module.

[0216] Further, such as Fig.12 The present invention also shows a connection diagram of a MIPI transmission system having multiple MIPI interface devices. In this embodiment, four 1-channel MIPI cameras are connected through a C-PHY interface, and the MIPI serializer and the MIPI deserializer are connected through a cable.

[0217] As described above, according to the combination of the MIPI serializer and the MIPI deserializer transmitting circuit and the receiving circuit, the two can be connected only by an optical cable, only by a copper cable, or by a hybrid optical-electrical cable.

[0218] Although the above shows the MIPI type serializer 1 and deserializer 2 of the D-PHY signal and the C-PHY signal, the present invention is not limited to this. As defined in the terms of the present invention, the high-speed signal transmitted by the present invention can include a signal sent by a MIPI interface device, or a general high-speed signal similar to a MIPI signal such as a single-edge or double-edge clock sampling. Low-speed signals include but are not limited to IIC, SPI, IIS, GPIOs, etc. with a rate lower than 10Mbps, and Master Clock (MCLK) signals with a rate of no more than 50MHz for image sensors. The transmission speed of such signals is lower than the rate of MIPI interface device signals, and some signals need to be transmitted in both directions.

[0219] In summary, the present invention has the following advantages:

[0220] 1. Based on the expansion of MIPI signal usage scenarios, it can support both dielectric transmission and optical transmission, thus meeting both short-distance and long-distance working scenarios.

[0221] 2. The optical and dielectric transmission channels are independently controllable. Either one of them can be used alone or both can be used at the same time, thus ensuring the reliability of information transmission in important occasions or in harsh environments.

[0222] 3. One MIPI signal can simultaneously support multiple MIPI devices with the same source, frequency and phase clock, increasing the number of MIPI devices supported by the system.

[0223] 4. According to the characteristics of MIPI signals, the idle circuit working mode is improved. Only the first clock channel, or the first data channel, and the input reverse high-speed channel, that is, the receiving unit, are detected to notify the power management module to wake up from sleep, thereby reducing the power consumption of the idle system.

[0224] Obviously, those skilled in the art should understand that the above-mentioned units or steps of the present invention can be implemented by a general-purpose computing device, they can be concentrated on a single computing device, and optionally, they can be implemented by a program code executable by a computer device, so that they can be stored in a storage device and executed by the computing device, or they can be made into individual integrated circuit modules, or multiple modules or steps therein can be made into a single integrated circuit module for implementation. Thus, the present invention is not limited to any specific combination of hardware and software.

[0225] The above content is a further detailed description of the present invention in combination with a specific preferred embodiment. It cannot be determined that the specific embodiments of the present invention are limited to this. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as belonging to the protection scope of the present invention determined by the submitted claims.

Claims

1. A MIPI serializer supporting optical and electrical dual modes, characterized in that: include: A first high-speed processing circuit, a first low-speed processing circuit, a forward packetizing circuit, a reverse unpacking circuit, an optoelectronic configuration module, a receiving unit and at least one transmitting unit; There is at least one first high-speed processing circuit, and each high-speed processing circuit includes multiple data channels to support at least one MIPI interface located at the MIPI data transmitting end, and is used to receive the first high-speed signal to be transmitted in the MIPI interface, generate the first high-speed data and transmit it to the forward packet circuit for serial conversion; The first low-speed processing circuit is used to receive a first low-speed signal to be transmitted from a MIPI data transmitting end, generate first low-speed data and send it to the forward packetizing circuit for serial conversion, receive second low-speed data from a reverse unpacking circuit, and send it to the MIPI data transmitting end; The forward packetizing circuit is used to combine and encapsulate the received first high-speed data and the first low-speed data into a first serial data frame, and output it to the optoelectronic configuration module; The reverse unpacking circuit is used to unpack the second serial data frame received from the optoelectronic configuration module and send the obtained second low-speed data to the first low-speed processing circuit; The optoelectronic configuration module is used to send the first serial data frame to be sent through the electrical path and / or optical path in the at least one sending unit, and receive the second serial data frame transmitted by the electrical path and / or optical path in the receiving unit; Each of the transmitting units includes an electrical transmitting circuit and an optical transmitting circuit, which transmit the first serial data frame of high-speed transmission by circuit or optical transmission respectively; The receiving unit includes an electrical receiving circuit and an optical receiving circuit, which receive the second serial data frame transmitted at a high speed through circuit or optical transmission respectively.

2. The serializer according to claim 1, characterized in that It also includes a channel configuration module for combining and configuring multiple data channels in one or more of the first high-speed processing circuits to form a corresponding MIPI interface, and transmitting the channel configuration information to the forward packetization circuit for encapsulation of the first serial frame.

3. The serializer according to claim 2, characterized in that The first high-speed processing circuit also includes a clock channel, which is configured in combination with multiple data channels, or when the clocks of multiple MIPIs are the same, only one clock is used or one clock is recovered from the data channel, and the multiple MIPI interfaces are combined into one MIPI interface for forward packetization.

4. The serializer according to claim 3, characterized in that The number of data channels and clock channels in the high-speed processing circuit is set according to the number and type of configured MIPI interfaces.

5. A MIPI deserializer supporting optical and electrical dual modes, characterized in that: include: a second high-speed processing circuit, a second low-speed processing circuit, a forward unpacking circuit, a reverse packing circuit, an optoelectronic configuration module, a transmitting unit, and at least one receiving unit; There is at least one second high-speed processing circuit, and each high-speed processing circuit includes multiple data channels to support at least one MIPI interface located at the MIPI data receiving end, and is used to receive the third high-speed data obtained by the forward unpacking circuit parsing the third serial data frame for transmission to the MIPI interface; The second low-speed processing circuit is used to receive a fourth low-speed signal from the MIPI data receiving end and generate fourth low-speed data, and transmit the fourth low-speed data to the reverse packetization circuit for serial conversion, and receive the third low-speed data obtained from the forward unpacking circuit, and send it to the MIPI data receiving end; The forward unpacking circuit unpacks the third serial data frame received from the optoelectronic configuration module, sends the obtained third high-speed data to the second high-speed processing circuit, and sends the obtained third low-speed data to the second low-speed processing circuit; The reverse encapsulation circuit is used to combine and encapsulate the fourth low-speed data obtained from the second low-speed processing circuit into a fourth serial data frame, and output it to the optoelectronic configuration module for high-speed transmission; The optoelectronic configuration module is used to receive the third serial data frame transmitted through the electrical path and / or optical path in the at least one receiving unit, and to send the fourth serial data frame to be sent through the electrical path and / or optical path in the sending unit, Each of the receiving units includes an electrical receiving circuit and an optical receiving circuit, which receive the third serial data frame transmitted at a high speed by means of circuit or optical transmission respectively; The sending unit includes an electrical sending circuit and an optical sending circuit, which send the fourth serial data frame of high-speed transmission through circuit or optical transmission respectively.

6. The deserializer according to claim 5, characterized in that: It also includes a channel configuration module, which is used to combine and configure multiple data channels in one or more of the second high-speed processing circuits to form a corresponding MIPI interface according to the channel configuration information transmitted from the forward unpacking circuit.

7. The deserializer according to claim 6, characterized in that: The channel configuration module is also used to combine and configure the clock channels and multiple data channels in one or more of the second high-speed processing circuits to form a corresponding MIPI interface. Alternatively, the clock can be copied to the corresponding clock channel output or coupled to the data channel to restore multiple groups of MIPI signals.

8. The deserializer according to claim 7, characterized in that: The number of data channels and clock channels in the high-speed processing circuit is set according to the number and type of configured MIPI interfaces.

9. A MIPI transmission system supporting optical and electrical dual modes, characterized in that: Comprising the serializer according to any one of claims 1 to 4, the deserializer according to any one of claims 5 to 8, and a cable; The cable connects the serializer and the deserializer; The sending unit of the serializer is connected to the receiving unit of the deserializer through the cable; The receiving unit of the serializer is connected to the sending unit of the deserializer through the cable.

10. The MIPI transmission system according to claim 9, characterized in that: The serializer is connected to at least one MIPI interface device at the MIPI data transmitting end, encapsulates the received first high-speed signal and the first low-speed signal into a first serial data frame, sends it to the deserializer through the transmitting unit of the serializer, and receives a second serial data frame from the receiving unit of the serializer; The deserializer is connected to at least one MIPI interface located at the MIPI data receiving end, encapsulates the received fourth low-speed signal into a fourth serial frame, sends it to the receiving unit of the serializer through the sending unit of the deserializer, and receives a third serial data frame from the receiving unit of the deserializer.

11. A MIPI serializer supporting optical and electrical dual modes, characterized in that: include: a first high-speed processing circuit, a first low-speed processing circuit, a forward packetizing circuit, a reverse unpacking circuit, an optoelectronic configuration module, at least one pin group, a low-speed transmission interface, at least one electrical drive circuit, at least one electrical high-speed interface, at least one encoding circuit, at least one optical drive circuit, and at least one light emitting interface; The first high-speed processing circuit is used to receive the first high-speed data from the at least one pin group and provide it to the forward packet circuit; The first low-speed processing circuit is used to receive the first low-speed data from the low-speed transmission interface and provide the first low-speed data to the forward packet circuit; The forward packetizing circuit is used to package the received first high-speed data and / or the first low-speed data into a first serial data frame, and provide it to the optoelectronic configuration module; The optoelectronic configuration module is used to provide the first serial data frame to the at least one electrical drive circuit and / or the at least one encoding circuit; The at least one electric driving circuit is connected to the at least one electric high-speed interface in a one-to-one correspondence, wherein the electric driving circuit drives the corresponding electric high-speed interface to output a high-speed serial electric signal according to the received first serial data frame; The at least one encoding circuit is connected to the at least one optical driving circuit in a one-to-one correspondence, and the at least one optical driving circuit is connected to the at least one light-emitting interface in a one-to-one correspondence, wherein the encoding circuit encodes the received first serial data frame and drives the corresponding optical driving circuit to output an optical signal through the corresponding light-emitting interface.

12. The MIPI serializer according to claim 11, further comprising an electrical receiving circuit, a decoding circuit, an optical receiving circuit, and an optical receiving interface; The optoelectronic configuration module is further used to receive a second serial data frame from the electrical receiving circuit and / or the decoding circuit and provide the frame to the reverse unpacking circuit; The electrical receiving circuit is connected to the at least one electrical high-speed interface and generates the second serial data frame based on one or more received high-speed serial electrical signals from the at least one electrical high-speed interface; The decoding circuit is connected to the optical receiving circuit, the optical receiving circuit receives the optical signal from the optical receiving interface and generates an electrical signal to provide to the decoding circuit, and the decoding circuit generates the second serial data frame according to the electrical signal received from the optical receiving circuit; The reverse unpacking circuit is used to obtain second low-speed data from the second serial data frame received through the optoelectronic configuration module, and provide the obtained second low-speed data to the first low-speed processing circuit; The first low-speed processing circuit is further used to output the second low-speed data obtained from the reverse unpacking circuit through the low-speed transmission interface.

13. The MIPI serializer according to claim 11 or claim 12, characterized in that: Also includes a channel configuration module; The channel configuration module is used to configure the correspondence between the pins of the at least one pin group and the D-PHY interface or the C-PHY interface connected to the MIPI serializer; Also included is a second high speed processing circuit; The at least one pin group includes a first pin group and a second pin group; The first pin group is connected to the first high-speed processing circuit; The second pin group is connected to the second high-speed processing circuit.

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