Terminal structure with lateral variable doping and preparation method thereof

Abstract

The invention relates to the technical field of MOS (metal oxide semiconductor), and discloses a terminal structure with lateral variable doping, which comprises a metal drain, a semiconductor epitaxial layer and source metal, and is characterized in that the semiconductor epitaxial layer comprises a substrate layer and a diffusion layer, and the diffusion layer comprises an active region, a main junction and a multi-region junction terminal expansion structure; the source electrode metal comprises a left section and a right section, polycrystalline silicon is deposited in the left section of the source electrode metal and between the left section of the source electrode metal and the right section of the source electrode metal, an interlayer medium is deposited on the surface of the polycrystalline silicon, gate electrode metal is arranged between the left section of the source electrode metal and the right section of the source electrode metal, and the gate electrode metal is in ohmic contact with the polycrystalline silicon. According to the method, the device performance and the device reliability after ion implantation are subjected to sampling detection, and the sampling detection needs to be carried out according to the subthreshold slope of the semiconductor device, the difference value of the threshold voltage and the source-drain breakdown voltage, so that the electrical performance and the reliability of the sampled semiconductor device can be quickly judged.

Description

Technical Field

[0001] The present invention relates to the technical field of MOS semiconductors, and in particular to a terminal structure with lateral variable doping and a preparation method thereof. Background Art

[0002] High-voltage power devices have better electrothermal properties than traditional silicon devices and can work normally in more demanding environments, so they have broad application prospects in photovoltaic power generation, electric vehicles, aerospace, etc. In order to meet the development needs of high energy efficiency, high power density, and small and lightweight power electronic systems, new generation SiC power devices are developing in the direction of high voltage, high power, high frequency and low loss.

[0003] The existing patent discloses a semiconductor terminal structure with lateral variable doping and a preparation method (publication number CN114141858A), wherein the terminal structure includes an N-type semiconductor drift region, the N-type semiconductor drift region includes a P-type semiconductor main junction, a P-type semiconductor field limiting ring, a P-type semiconductor VLD region and an N+ type semiconductor field limiting ring, the P-type semiconductor field limiting ring is interconnected with one side of the P-type semiconductor VLD region, and the junction depth of the P-type semiconductor VLD region is greater than the junction depth of the P-type semiconductor main junction. In the technology disclosed in the existing patent, as the switching frequency of the power device continues to increase, when the power device is switched quickly, it is easy to cause instantaneous overvoltage or overheating damage due to the charging and discharging effect of the terminal structure, and it is very easy to be damaged during the high-speed switching process. Summary of the invention

[0004] The main technical problem solved by the present invention is to provide a terminal structure with lateral variable doping and a preparation method thereof, which solves the problems in the above-mentioned background technology.

[0005] To solve the above technical problems, according to one aspect of the present invention, more specifically, a terminal structure with lateral variable doping includes a metal drain, a semiconductor epitaxial layer and a source metal, wherein the semiconductor epitaxial layer includes a substrate layer and a diffusion layer, the diffusion layer includes an active region, a main junction and a multi-region junction terminal extension structure, the source metal includes two left and right sections, polysilicon is deposited inside the left section of the source metal and between the left and right sections of the source metal, an interlayer dielectric is deposited on the surface of the polysilicon, a gate metal is arranged between the left and right sections of the source metal, wherein the gate metal is in ohmic contact with the polysilicon; A P-type doping region 1 and an N-type doping region 1 are formed in the active region of the diffusion layer by ion implantation; A second P-type doped region, a first P-type heavily doped region and a second P-type heavily doped region are formed in the main junction of the diffusion layer by ion implantation; The multi-region junction terminal extension structure of the diffusion layer is formed into an N-type doped region and a second N-type doped region by ion implantation.

[0006] Furthermore, the P-type doped region 2 also includes a design of separate distribution on the left and right sides, wherein the P-type heavily doped region 1 is located in the P-type doped region 2 on the left, and the P-type heavily doped region 2 is located in the P-type doped region 2 on the right.

[0007] Furthermore, an isolation ring is formed between the P-type doping regions 2 on the left and right sides by ion implantation, wherein a plurality of isolation rings may be designed.

[0008] A method for preparing a terminal structure with lateral variable doping comprises the following steps: S1. Preparation of silicon substrate: Cut silicon wafers from high-purity silicon single crystal rods and then clean them with deionized water and chemical solutions; S2, Growth of silicon oxide: A silicon oxide layer is grown on the silicon substrate as an insulating layer in the MOS structure; S3, photolithography: using ultraviolet light to irradiate the photoresist through a mask for development to obtain a photolithography pattern; S4, ion implantation and diffusion: dopants are implanted into specific areas of the silicon wafer by accelerating ions, changing the conductivity of silicon to form P-type or N-type semiconductor regions; S5. Deposition of metal electrodes: depositing metal electrodes on the silicon oxide layer to form source, drain and gate electrodes; S6. Etching and cleaning: Remove unnecessary metal through etching technology.

[0009] Furthermore, in step S4, the device performance and device reliability after ion implantation are sampled and tested. The sampling test needs to judge whether the electrical performance and reliability of the sampled semiconductor device meet the standards based on the subthreshold slope, the difference in threshold voltage, and the source-drain breakdown voltage of the semiconductor device. There are: in, It indicates the probability coefficient of the electrical performance and reliability of the sampled semiconductor devices meeting the standards. represents the subthreshold slope of the sampled semiconductor device, represents the electrical stability factor of the sampled semiconductor device; and: In the formula, Indicates the threshold voltage actually detected by the sampling semiconductor device, Represents the threshold voltage of the semiconductor device design, Indicates the source-drain breakdown voltage actually detected by the sampled semiconductor. Represents the source-drain breakdown voltage of a semiconductor device design.

[0010] Furthermore, when When , it means that the electrical performance and reliability of the sampled semiconductor devices meet the use requirements; when When , it means that the electrical performance and reliability of the sampled semiconductor devices do not meet the use requirements.

[0011] Furthermore, in the step S5, copper metal is deposited on the surface of the semiconductor epitaxial layer by evaporation deposition.

[0012] Furthermore, the etching technology in step S6 adopts plasma etching, and the silicon wafer needs to be cleaned after etching to remove residual chemicals or etching by-products. Beneficial effects: 1. The present invention designs the main junction as a segmented structure and introduces an isolation ring to physically cut off the current path formed by the charging and discharging effect during the switching process of the power device, protect the sensitive position of the main junction, and improve the reliability of high-speed switching of the power device.

[0013] 2. The terminal structure proposed in the present invention is simple, and only the layout needs to be modified during the P-well layout design, without adjusting the process flow and adding process steps, and is fully compatible with the existing high-voltage power device process.

[0014] 3. The present invention performs sampling detection on the device performance and device reliability after ion implantation. The sampling detection needs to be based on the subthreshold slope, threshold voltage difference, and source-drain breakdown voltage of the semiconductor device, so that the electrical performance and reliability of the sampled semiconductor device can be quickly judged. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a structural schematic diagram of Embodiment 1 of the present invention; Figure 2 It is a structural schematic diagram of the second embodiment of the present invention.

[0016] In the figure: 1. Metal drain; 2. Substrate layer; 3. Diffusion layer; 4. P-type doped region 1; 5. N-type doped region 1; 6. Interlayer dielectric; 7. Polysilicon; 8. Source metal; 9. Gate metal; 10. Field oxide layer; 11. Doped region; 12. N-type doped region 2; 13. P-type heavily doped region 1; 14. P-type heavily doped region 2; 15. P-type doped region 2; 16. Isolation ring. DETAILED DESCRIPTION

[0017] In order to make the technical solution of the present invention clearer, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0018] like Figure 1 , 2As shown, a method for preparing a terminal structure with lateral variable doping includes the following steps: Step 1: Preparation of silicon substrate: Cut silicon wafers from high-purity silicon single crystal rods and then clean them with deionized water and chemical solutions; Step 2: Growth of silicon oxide: growing a silicon oxide layer on a silicon substrate as an insulating layer in the MOS structure; Step 3: Photolithography: Use ultraviolet light to irradiate the photoresist through a mask for development to obtain a photolithography pattern; Step 4: Ion implantation and diffusion: dopants are implanted into specific areas of the silicon wafer by accelerating ions, changing the conductivity of silicon to form P-type or N-type semiconductor regions; Step 5: Deposition of metal electrodes: depositing metal electrodes onto the silicon oxide layer to form source, drain and gate electrodes; depositing copper metal onto the surface of the semiconductor epitaxial layer by evaporation deposition.

[0019] Step 6: Etching and cleaning: Remove unnecessary metals through etching technology. The etching technology in this step uses plasma etching, and the silicon wafer needs to be cleaned after etching to remove residual chemicals or etching byproducts.

[0020] In step 4, the device performance and device reliability after ion implantation are sampled and tested. The sampling test needs to judge whether the electrical performance and reliability of the sampled semiconductor device meet the standards based on the subthreshold slope, threshold voltage difference, and source-drain breakdown voltage of the semiconductor device. There are: in, It indicates the probability coefficient of the electrical performance and reliability of the sampled semiconductor devices meeting the standards. represents the subthreshold slope of the sampled semiconductor device, represents the electrical stability factor of the sampled semiconductor device; and: In the formula, Indicates the threshold voltage actually detected by the sampling semiconductor device, Represents the threshold voltage of the semiconductor device design, Indicates the source-drain breakdown voltage actually detected by the sampled semiconductor. Represents the source-drain breakdown voltage of a semiconductor device design.

[0021] when When , it means that the electrical performance and reliability of the sampled semiconductor devices meet the use requirements; when When , it means that the electrical performance and reliability of the sampled semiconductor devices do not meet the use requirements.

[0022] The electrical performance and reliability test of any sampled semiconductor device X is performed, and the threshold voltage actually tested of the sampled semiconductor device X is taken as (V), the threshold voltage of semiconductor device X is designed to be (V), the source-drain breakdown voltage actually detected by sampling semiconductor X is (V), source-drain breakdown voltage of semiconductor device X (V), then we have: From the above calculation, we can know that the electrical stability coefficient of the sampled semiconductor device X is .

[0023] And, the subthreshold slope of the sampled semiconductor device X is (mV / decade, subthreshold slope refers to the subthreshold region of MOSFET, i.e. the switching transition region, which is the slope of the relationship between current and gate voltage. The smaller the subthreshold slope, the more sensitive the switching characteristics). Then we have: From the above calculation, we can know that the probability coefficient of the electrical performance and reliability of the sampled semiconductor device X meeting the standards is: That is, the electrical performance and reliability of the sampled semiconductor device X meet the use requirements.

[0024] Example 1 like Figure 1As shown, according to one aspect of the present invention, a terminal structure with lateral variable doping is provided, including a metal drain 1, a semiconductor epitaxial layer and a source metal 8, wherein the semiconductor epitaxial layer includes a substrate layer 2 and a diffusion layer 3, the diffusion layer 3 includes an active area, a main junction and a multi-region junction terminal extension structure, the source metal 8 includes two left and right sections, polysilicon 7 is deposited inside the left section of the source metal 8 and between the left and right sections of the source metal 8, an interlayer dielectric 6 is deposited on the surface of the polysilicon 7, a gate metal 9 is arranged between the left and right sections of the source metal 8, wherein the gate metal 9 is in ohmic contact with the polysilicon 7; a P-type doping region 14 and an N-type doping region 15 are formed in the active area of ​​the diffusion layer 3 by ion implantation; a P-type doping region 2 15, a P-type heavily doped region 13 and a P-type heavily doped region 2 14 are formed in the main junction of the diffusion layer 3 by ion implantation; the multi-region junction terminal extension structure of the diffusion layer 3 includes a doping region 11 and an N-type doping region 2 12 are formed by ion implantation. Since the terminal structure and the main junction are usually connected together, and the potential outside the terminal structure is high and the potential near the active area is low, a current will flow from the outside of the terminal to the active area during the switching process of the power device, causing the potential inside the main junction to rise. By designing the doping region 11 to decrease to the right, on the one hand, it can avoid the strong electric field breakdown of the dielectric layer above the main junction, and on the other hand, it can avoid the problem of increased leakage current causing the polysilicon gate potential to rise.

[0025] Example 2 like Figure 2 As shown, the P-type doping region 15 also includes a design with separate distribution on the left and right sides, wherein the P-type heavily doped region 13 is located in the P-type doping region 15 on the left, and the P-type heavily doped region 14 is located in the P-type doping region 15 on the right. An isolation ring 16 is formed between the P-type doping regions 15 on the left and right sides by ion implantation, wherein the isolation ring 16 can be designed to have several numbers. The main junction is segmented and an isolation ring structure (isolation ring 16) is introduced to block the current path formed by the charging and discharging effect of the terminal structure during the switching process of the power device from a physical level, to prevent the formation of a strong electric field and leakage current at the sensitive position of the main junction, and to protect the main junction and the cells adjacent to the active area from premature damage during high-speed switching.

[0026] The above-mentioned embodiments only express several implementation methods of the present invention, and the description thereof is relatively specific and detailed, but it cannot be understood as limiting the scope of the patent of the present invention. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, which all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A terminal structure with lateral variable doping, comprising a metal drain (1), a semiconductor epitaxial layer and a source metal (8), wherein the semiconductor epitaxial layer comprises a substrate layer (2) and a diffusion layer (3), and the diffusion layer (3) comprises an active region, a main junction and a multi-region junction terminal extension structure, characterized in that: The source metal (8) comprises two sections, a left section and a right section; polysilicon (7) is deposited inside the left section of the source metal (8) and between the left and right sections of the source metal (8); an interlayer dielectric (6) is deposited on the surface of the polysilicon (7); a gate metal (9) is provided between the left and right sections of the source metal (8), wherein the gate metal (9) is in ohmic contact with the polysilicon (7); A P-type doping region (4) and an N-type doping region (5) are formed in the active region of the diffusion layer (3) by ion implantation; A second P-type doped region (15), a first P-type heavily doped region (13) and a second P-type heavily doped region (14) are formed in the main junction of the diffusion layer (3) by ion implantation; The multi-region junction terminal extension structure of the diffusion layer (3) is formed by ion implantation into a doped region (11) and a second N-type doped region (12).

2. The terminal structure with lateral variable doping according to claim 1, characterized in that: The P-type doped region 2 (15) also includes a design with separate distribution on the left and right sides, wherein the P-type heavily doped region 1 (13) is located in the P-type doped region 2 (15) on the left, and the P-type heavily doped region 2 (14) is located in the P-type doped region 2 (15) on the right.

3. The terminal structure with lateral variable doping according to claim 2, characterized in that: An isolation ring (16) is formed between the two P-type doped regions (15) on the left and right sides by ion implantation, wherein a plurality of isolation rings (16) may be designed.

4. A method for preparing a terminal structure with lateral variable doping according to any one of claims 1 to 3, characterized in that: The following steps are involved: S1. Preparation of silicon substrate: Cut silicon wafers from high-purity silicon single crystal rods and then clean them with deionized water and chemical solutions; S2, Growth of silicon oxide: A silicon oxide layer is grown on the silicon substrate as an insulating layer in the MOS structure; S3, photolithography: using ultraviolet light to irradiate the photoresist through a mask for development to obtain a photolithography pattern; S4, ion implantation and diffusion: dopants are implanted into specific areas of the silicon wafer by accelerating ions, changing the conductivity of silicon to form P-type or N-type semiconductor regions; S5. Deposition of metal electrodes: depositing metal electrodes on the silicon oxide layer to form source, drain and gate electrodes; S6. Etching and cleaning: Remove unnecessary metal through etching technology.

5. The method for preparing a terminal structure with lateral variable doping according to claim 4, characterized in that: In step S4, the device performance and device reliability after ion implantation are sampled and tested. The sampling test needs to judge whether the electrical performance and reliability of the sampled semiconductor device meet the standards based on the subthreshold slope, the difference of the threshold voltage, and the source-drain breakdown voltage of the semiconductor device. The following are the steps: in, It indicates the probability coefficient of the electrical performance and reliability of the sampled semiconductor devices meeting the standards. represents the subthreshold slope of the sampled semiconductor device, represents the electrical stability factor of the sampled semiconductor device; and: In the formula, Indicates the threshold voltage actually detected by the sampling semiconductor device, Represents the threshold voltage of the semiconductor device design, Indicates the source-drain breakdown voltage actually detected by the sampled semiconductor. Represents the source-drain breakdown voltage of a semiconductor device design.

6. The method for preparing a terminal structure with lateral variable doping according to claim 5, characterized in that: when When , it means that the electrical performance and reliability of the sampled semiconductor devices meet the use requirements; when When , it means that the electrical performance and reliability of the sampled semiconductor devices do not meet the use requirements.

7. The method for preparing a terminal structure with lateral variable doping according to claim 1, characterized in that: In the step S5, copper metal is deposited on the surface of the semiconductor epitaxial layer by evaporation deposition.

8. The method for preparing a terminal structure with lateral variable doping according to claim 1, characterized in that: The etching technology in step S6 adopts plasma etching, and the silicon wafer needs to be cleaned after etching to remove residual chemicals or etching by-products.

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